NCP81142 Multiple-Phase Controller with SVID Interface for Desktop and Notebook CPU Applications

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Multiple-Phase Controller with SVID Interface for

Desktop and Notebook CPU Applications

The NCP81142 Multi−Phase buck solution is optimized for Intel® VR12.5 compatible CPUs with user configurations of 4/3/2/1 phases. The controller combines true differential voltage sensing, differential inductor DCR current sensing, input voltage feed−forward, and adaptive voltage positioning to provide accurately regulated power for both Desktop and Notebook applications. The control system is based on Dual−Edge pulse−width modulation (PWM) combined with DCR current sensing providing the fastest initial response to dynamic load events at reduced system cost. It has the capability to shed to single phase during light load operation and can auto frequency scale in light load conditions while maintaining excellent transient performance.

High performance operational error amplifiers are provided to simplify compensation of the system. Patented Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed−loop transient response and Dynamic VID performance. Patented Total Current Summing provides highly accurate digital current monitoring.

Features

•

Meets Intel VR12.5 Specifications

•

Current Mode Dual Edge Modulation for Fastest Initial Response to Transient Loading

•

High Performance Operational Error Amplifier

•

Digital Soft Start Ramp

•

Dynamic Reference Injection

•

Accurate Total Summing Current Amplifier

•

Dual High Impedance Differential Voltage and Total Current Sense Amplifiers

•

Phase−to−Phase Dynamic Current Balancing

•

“Lossless” DCR Current Sensing for Current Balancing

•

True Differential Current Balancing Sense Amplifiers for Each Phase

•

Adaptive Voltage Positioning (AVP)

•

Switching Frequency Range of 290 kHz – 590 kHz

•

Startup into Pre−Charged Loads While Avoiding False OVP

•

Power Saving Phase Shedding

•

Vin Feed Forward Ramp Slope

•

Over Voltage Protection (OVP) & Under Voltage Protection (UVP)

•

Over Current Protection (OCP)

•

VR−RDY Output with Internal Delays

•

These are Pb−Free Devices Applications

•

Desktop and Notebook Processors

MARKING DIAGRAM www.onsemi.com

See detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet.

ORDERING INFORMATION QFN32

CASE 485CD

A = Assembly Location L = Wafer Lot

Y = Year

W = Work Week G = Pb−Free Package (Note: Microdot may be in either location)

1

NCP 81142 ALYWG

G

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VRMP VSN

PWM4/ROSC PWM3/VBOOT PWM2/IMAX PWM1/INT_SEL DRON

VSP

TSENSE

SDIO

SCLK

VRDY VRHOT

ALERT

DIFFOUT FB COMP ILIM IOUT CSSUM CSREF CSCOMP

CSN4 CSP4 CSN2 CSP2 CSN3 CSP3 CSN1 CSP1

GND VCC ENABLE

+ −

Error DIFFAMP Amp

DAC GND CSREF

Current Measurement

& Limit

CS Amp

Thermal Monitor

SVID Interface Data

Registers ADC

OVP

DAC DAC

VR Ready Comparator

Enable VSP VSN DAC

MUX

VSP−VSN TSENSE VBOOT IOUT IMAX ADDR

Current Balance

PWM Generators

Power State Stage RAMP1

RAMP2 RAMP3 RAMP4

Enable

Ramp Generators

OVP COMP Enable

UVLO & EN IPH4

IPH3 IPH2 IPH1

OVP VSP

VSN

NCP81142

Figure 1. Block Diagram for NCP81142

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1 2 3 4 5 6 7 8

24 23 22 21 20 19 18 17

9 10 11 12 13 14 15 16

25 26 27 28 29 30 31 32

Figure 2. NCP81142 Pin Configurations

PWM4/ROSC PWM2/VBOOT PWM3/IMAX PWM1/INT_SEL DRON CSP1 CSN1 CSP3

ENABLE VCC VR_HOT#

SDIO ALERT#

SCLK VR_RDY TSENSE

VSP VSN DIFFOUT FB COMP VRMP IOUT ILIM

CSCOMP CSSUM CSREF CSN4 CSP4 CSN2 CSP2 CSN3 NCP81142

NCP81142 PIN DESCRIPTIONS

Pin No. Symbol Description

1 ENABLE Logic input. Logic high enables the output and logic low disables the output.

2 VCC Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground 3 VR_HOT# Thermal logic output for over temperature

4 SDIO Serial VID data interface

5 ALERT# Serial VID ALERT#.

6 SCLK Serial VID clock

7 VR_RDY Open drain output. High indicates that the output is regulating 8 TSENSE Temp Sense input for the multiphase converter

9 PWM4/ROSC Phase 4 PWM output. A resistance from this pin to ground programs the oscillator frequency 10 PWM2/VBOOT Phase 2 PWM output. Also as VBOOT input pin to adjust the boot−up voltage. During start up it is

used to program VBOOT with a resistor to ground

11 PWM3/IMAX Phase 3 PWM output. Also as ICC_MAX Input Pin. During start up it is used to program ICC_MAX with a resistor to ground

12 PWM1/INT_SEL Phase 1 PWM output. Also as Int_sel program pin. A resistor to ground on this pin programs the INT_Select value

13 DRON Bidirectional gate drive enable output

14 CSP1 Non−inverting input to current balance sense amplifier for phase 1 15 CSN1 Inverting input to current balance sense amplifier for phase 1

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NCP81142 PIN DESCRIPTIONS

Pin No. Symbol Description

17 CSN3 Inverting input to current balance sense amplifier for phase 3. Pull this Pin to VCC, configure as 1−phase operation

18 CSP2 Non−inverting input to current balance sense amplifier for phase 2

19 CSN2 Inverting input to current balance sense amplifier for phase 2. Pull this Pin to VCC, configure as 2−phase operation

20 CSP4 Non−inverting input to current balance sense amplifier for phase 4

21 CSN4 Inverting input to current balance sense amplifier. Pull this Pin to VCC, configure as 3−phase operation

22 CSREF Total output current sense amplifier reference voltage input, a capacitor on this pin is used to ensure CSREF voltage signal integrity

23 CSSUM Inverting input of total current sense amplifier 24 CSCOMP Output of total current sense amplifier

25 ILIM Over current shutdown threshold setting. Resistor to CSCOMP to set threshold 26 IOUT Total output current monitor.

27 VRMP Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control the ramp of PWM slope

28 COMP Output of the error amplifier and the inverting inputs of the PWM comparators

29 FB Error amplifier voltage feedback

30 DIFFOUT Output of the differential remote sense amplifier 31 VSN Inverting input to differential remote sense amplifier 32 VSP Non−inverting input to the differential remote sense amplifier 33 FLAG / GND Power supply return (QFN Flag)

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL INFORMATION

Pin Symbol V_MAX V_MIN

COMP VCC + 0.3 V −0.3 V

CSCOMP VCC + 0.3 V −0.3 V

VSN GND + 300 mV GND – 300 mV

DIFFOUT VCC + 0.3 V −0.3 V

VR_RDY VCC + 0.3 V −0.3 V

VCC 6.5 V −0.3 V

IOUT 2.0 V −0.3 V

VRMP +25 V −0.3 V

All Other Pins VCC + 0.3 V −0.3 V

*All signals referenced to GND unless noted otherwise.

THERMAL INFORMATION

Description Symbol Typ Unit

Thermal Characteristic QFN Package (Note 1)

R_qJA 68 _C/W

Operating Junction Temperature Range (Note 2) T_J −40 to +125 _C

Operating Ambient Temperature Range −40 to +100 _C

Maximum Storage Temperature Range T_STG −40 to +150 _C

Max Power Dissipation Pd 110 to 131 mW

Moisture Sensitivity Level QFN Package

MSL 1

*The maximum package power dissipation must be observed.

1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM 2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM

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ELECTRICAL CHARACTERISTICS

Unless otherwise stated: −40°C < T_A < 100°C; V_CC = 5 V; C_VCC = 0.1 mF

Parameter Test Conditions Min Typ Max Unit

ERROR AMPLIFIER

Input Bias Current @ 1.3 V −27 27 mA

Open Loop DC Gain CL = 20 pF to GND,

RL = 10 kW to GND

80 dB

Open Loop Unity Gain Bandwidth CL = 20 pF to GND,

RL = 10 kW to GND

20 MHz

Slew Rate DVin = 100 mV, G = −10 V/V,

DVout = 1.5 V – 2.5 V, CL = 20 pF to GND, DC Load = 10k to GND

20 V/ms

Maximum Output Voltage I_SOURCE = 2.0 mA 3.5 V

Minimum Output Voltage I_SINK = 2.0 mA 1 V

DIFFERENTIAL SUMMING AMPLIFIER

Input Bias Current VSP, VSN = 1.3 V −15 15 uA

VSP Input Voltage Range −0.3 3.0 V

VSN Input Voltage Range −0.3 0.3 V

−3dB Bandwidth CL = 20 pF to GND,

RL = 10 kW to GND 10 MHz

Closed Loop DC gain VS+ to VS− = 0.5 to 1.3 V

1.0 V/V

CURRENT SUMMING AMPLIFIER

Offset Voltage (Vos) −300 300 mV

Input Bias Current CSSUM = CSREF= 1 V −10 10 mA

Open Loop Gain 80 dB

Current Sense Unity Gain Bandwidth C_L = 20 pF to GND,

R_L = 10 kW to GND 10 MHz

CURRENT BALANCE AMPLIFIER

Maximum CSCOMP Output Voltage I_source = 2 mA 3.5 V

Minimum CSCOMP Output Voltage I_sink = 500 mA 0.1 V

Input Bias Current CSP₁₋₄ = CSN₁₋₄ = 1.2

−50 50

nA

Common Mode Input Voltage Range CSPx = CSNx 0 2.3 V

Differential Mode Input Voltage Range CSNx = 1.2 V −100 100 mV

Input Offset Voltage Matching CSPx = CSNx = 1.2 V,

Measured from the average

−1.5 1.5 mV

Current Sense Amplifier Gain 0 V < CSPx − CSNx < 0.1 V, 5.7 6.0 6.3 V/V

Multiphase Current Sense Gain Matching CSP−CSN = 10 mV to 30 mV −3 3 %

−3dB Bandwidth 8 MHz

INPUT SUPPLY

Supply Voltage Range 4.75 5.25 V

VCC Quiescent Current EN = high, PS0,1,2 Mode 25 mA

EN = high, PS3 Mode 15 mA

EN = low 30 mA

3. Guaranteed by design or characterization data, not in production test.

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INPUT SUPPLY

UVLO Threshold VCC rising 4.5 V

VCC falling 4 V

VCC UVLO Hysteresis 160 mV

UVLO Threshold VRMP rising 4.2 V

VRMP failing 3 V

DAC SLEW RATE

Soft Start Slew Rate 5 mv/ms

Slew Rate Slow 5 mv/ms

Slew Rate Fast 20 mv/ms

ENABLE INPUT

Enable High Input Leakage Current External 1k pull−up to 3.3 V 1.0 mA

Upper Threshold V_UPPER 0.8 V

Lower Threshold V_LOWER 0.3 V

Total Hysteresis V_UPPER – V_LOWER 90 mV

Enable Delay Time Measure time from Enable

transitioning HI to when DRON goes high

5 ms

DRON

Output High Voltage Sourcing 500 mA 3.0 V

Output Low Voltage Sinking 500 mA 0.1 V

Rise Time CL (PCB) = 20 pF,

DVo = 10% to 90% 156 ns

Fall Time 55 ns

Internal Pull Down Resistance EN = Low 70 kW

IOUT OUTPUT

Input Referred Offset Voltage Ilimit to CSREF −3.5 3.5 mV

Output Source Current Ilimit sink current = 80 mA 850 mA

Current Gain (IOUT_CURRENT) / (ILIMIT_CURRENT),

R_ILIM = 20k, R_IOUT = 5.0k , DAC = 0.8 V, 1.25 V, 1.52 V

9.5 10 10.5

OSCILLATOR

Switching Frequency Range 290 590 KHz

4 Phase Operation 600 kHz

OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)

Absolute Over Voltage Threshold During Soft Start CSREF 2.75 2.9 3 V

Over Voltage Threshold Above DAC VSP rising 350 400 425 mV

Over Voltage Delay VSP rising to PWMx low 50 ns

Under Voltage Ckt in development 300 mV

Under−voltage Delay Ckt in development 5 ms

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OVERCURRENT PROTECTION

ILIM Threshold Current (OCP shutdown after 50 ms delay)

(PS0) Rlim = 20k 9.0 10 11.0 mA

ILIM Threshold Current (immediate OCP shutdown) (PS0) Rlim = 20k 13.5 15 16.5 mA ILIM Threshold Current (OCP shutdown after 50 ms

delay)

(PS1, PS2, PS3) Rlim = 20k, N = number of phases in PS0 mode

10/N mA

ILIM Threshold Current (immediate OCP shutdown) (PS1, PS2, PS3) Rlim = 20k, N = number of phases in PS0 mode

15/N mA

MODULATORS (PWM Comparators)

0% Duty Cycle COMP voltage when the PWM

outputs remain LO

1.3 V

100% Duty Cycle COMP voltage when the PWM

outputs remain HI VRMP = 12.0 V

2.5 V

PWM Ramp Duty Cycle Matching COMP = 2 V, PWM Ton matching 1 %

PWM Phase Angle Error Between adjacent phases at 25° 5 deg

Ramp Feed−forward Voltage range 5 20 V

VR_HOT#

Output Low Voltage I_VRHOT = −4 mA 0.3 V

Output Leakage Current High Impedance State −1.0 1.0 mA

TSENSE

Alert# Assert Threshold 491 mV

Alert# De−assert Threshold 513 mV

VRHOT Assert Threshold 472 mV

VRHOT Rising Threshold 494 mV

TSENSE Bias Current 115 120 125 mA

ADC

Voltage Range 0 2 V

Total Unadjusted Error (TUE) −1 +1 %

Differential Nonlinearity (DNL) 8−bit 1 LSB

Power Supply Sensitivity ±1 %

Conversion Time 30 ms

Round Robin 90 ms

VR_RDY, (Power Good) OUTPUT

Output Low Saturation Voltage I_{VR_RDY} = 4 mA 0.3 V

Rise Time External pull−up of 1 kW to 3.3 V,

C_TOT = 45 pF, DVo = 10% to 90% 100 ns

Fall Time External pull−up of 1 kW to 3.3 V,

C_TOT = 45 pF, DVo = 90% to 10% 10 ns

Output Voltage at Power−up VR_RDY pulled up to 5 V via 2 kW 1.0 V

Output Leakage Current When High VR_RDY = 5.0 V −1.0 1.0 mA

VR_RDY Delay (rising) DAC=TARGET to VR_RDY 5 ms

VR_RDY Delay (falling) From OCP or OVP 5 ms

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PWM OUTPUTS

Output High Voltage Sourcing 500 mA

VCC – 0.2V

− − V

Output Mid Voltage No Load, SetPS = 02 1.9 2.0 2.1 V

Output Low Voltage Sinking 500 mA 0.7 V

Rise and Fall Time CL (PCB) = 50 pF,

DVo = GND to VCC 10 ns

PHASE DETECTION

CSN Pin Threshold Voltage 4.5 V

Phase Detect Timer 50 ms

STATE TRUTH TABLE

STATE VR_RDY Pin

Error AMP

Comp Pin OVP & UVP DRON Pin

Method of Reset POR

0 < VCC < UVLO

N/A N/A N/A Resistive pull down

Disabled EN < threshold UVLO > threshold

Low Low Disabled Low

Start up Delay &

Calibration EN > threshold UVLO > threshold

Low Low Disabled Low

DRON Fault EN > threshold UVLO > threshold DRON < threshold

Low Low Disabled Resistive pull up Driver must

release DRON to high Soft Start

EN > threshold UVLO > threshold

DRON > High

Low Operational Active /

No latch

High

Normal Operation EN > threshold UVLO >threshold

DRON > High

High Operational Active /

Latching

High N/A

Over Voltage Low N/A DAC + 150 mV High

Over Current Low Operational Last DAC Code Low

V_OUT = 0 V Low: if Reg34h:bit0 = 0;

High:if Reg34h:bit0 = 1

Clamped at 0.9 V

Disabled High, PWM outputs in low state

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Figure 3.

occurs Controller

POR

Disable

Calibrate

Phase Detection and Power On Configuration

EN = 1

EN = 0 Set DRVON High

VCCP > UVLO and DRVON High Check VBoot

Wait for SVID command

Boost Cap Refresh

First VID code programmed Cal Done

POC done

VBoot = 0 V VBoot > 0V

Boost cap done

Soft start done

Current Limit Occurs CSREF OVP

(VCCANDVRMP) > UVLO

(DAC + 400mV) OVP or CSREF OVP occurs

EN = 0

Soft Start Ramp Turn off Drive

VR_RDY = Low.

and monitor for OVP Current Limit

Maintain DAC voltage Occurs

OVP Latch off.

VR_RDY = Low Ramp output to 0V then force LS ON

(DAC + 400mV) OVP or CSREF OVP occurs

EN = 0 Normal Operation,

VR_RDY = High DAC = VID/offset programmed.

Power state = PS programmed

UVP Occurs

VR_RDY = Low DAC = VID/offset programmed.

Power state = PS programmed VCC < UVLO OR

VRMP < UVLO

EN = 0 DRVON Latch off

Turn off Drive

DRVON Pulled Low

DRVON Pulled Low DRVON

Pulled Low

DRVON Pulled Low

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General

The NCP81142 is a four phase dual edge modulated multiphase PWM controller, designed to meet the Intel VR12.5 specifications with a serial SVID control interface. It is designed to work in notebook, desktop, and server applications.

Serial VID interface (SVID)

For SVID Interface communication details please contact Intel Inc.

BOOT VOLTAGE PROGRAMMING

The NCP81142 has a Vboot voltage that can be externally programmed. The Boot voltage for the NCP81142 is set using VBOOT pin on power up. A 10uA current is sourced from the VBoot pin and the resulting voltage is measured. This is compared with the thresholds in table below. This value is set on power up and cannot be changed after the initial power up sequence is complete.

BOOT VOLTAGE TABLE

R VBoot Phase Number in PS1

30.1k 0 V 1

49.9k 1.65 V 1

69.8k 1.70 V 1

90.9k 1.75 V 1

130k 0 V 2

150k 1.65 V 2

169k 1.70 V 2

Open 1.75 V 2

Remote Sense Amplifier

A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to

V_DIFOUT+

ǒ

V_VSP*V_VSN

Ǔ

₎

ǒ

1.3 V*V_DAC

Ǔ

₎

ǒ

V_DROOP*V_CSREF

Ǔ

This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier output bias.

High Performance Voltage Error Amplifier

The Remote Sense Amplifier output is applied to a Type 3 compensation network formed by the error amplifier and external tuning components. The non−inverting input of the error amplifier is connected to the same reference voltage used to bias the Remote Sense Amplifier output. The integrating function of the Type 3 feedback compensation is performed internally and does not require external capacitor Cf1 (see below).

Vbias ERROR

COMP Cin Cf1

Cf

Rin2 Rin1

Rf

_ +

Figure 4. Traditional Type 3 External Compensation

Vbias ERROR

COMP Cin

Cf

Rin2 Rin1

Rf

_ +

Figure 5. NCP81142 Modified Type 3 External Compensation

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Rin1 = 1k, Rf = 3k IN NEW CONTROLLER Address Resistor

Divider Gain from Digital Integrator

Equivalent Cf1 in Type III Network

Equivalent Rf in Type III Network

10k 1 0.079n 3000

22k 2 0.157n 3000

26k 4 0.32n 3000

51k 8 0.63n 3000

68k 10 0.79n 3000

91k 12 0.95n 3000

120k 16 1.26n 3000

160k 32 2.52n 3000

220k 64 5.04n 3000

10k 1 0.047n 5000

22k 2 0.094n 5000

26k 4 0.19n 5000

51k 8 0.38n 5000

68k 10 0.47n 5000

91k 12 0.57n 5000

120k 16 0.76n 5000

160k 32 1.51n 5000

220k 64 3.02n 5000

Rin1 = 1k, Rf = 7.5k IN NEW CONTROLLER Address Resistor

10k 1 0.031n 7500

22k 2 0.063n 7500

26k 4 0.13n 7500

51k 8 0.25n 7500

68k 10 0.32n 7500

91k 12 0.38n 7500

120k 16 0.50n 7500

160k 32 1.01n 7500

220k 64 2.02n 7500

10k 1 0.024n 10000

22k 2 0.047n 10000

26k 4 0.09n 10000

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Equivalent Rf in Type III Network Equivalent Cf1 in Type III

Network Divider Gain from Digital

Integrator

51k 8 0.19n 10000

68k 10 0.24n 10000

91k 12 0.28n 10000

120k 16 0.38n 10000

160k 32 0.76n 10000

220k 64 1.51n 10000

Optimization of the traditional Type 3 compensation should be rechecked using the closest Type 3 Cf1 equivalent in order to determine if readjustment of other component values is needed.

Differential Current Feedback Amplifiers

Each phase has a low offset differential amplifier to sense that phase current for current balance. The inputs to the CSNx and CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN does not exceed 10 kW to avoid offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for accurate current balance. Fine tuning of this time constant is generally not required. The individual phase current is summed into the PWM comparator feedback this way current is balanced via a current mode control approach.

CCSN RCSN

DCR LPHASE

1 2

SWNx VOUT

CSPx CSNx

R_CSN+ L_PHASE C_CSN* DCR

Figure 6.

Total Current Sense Amplifier

The NCP81142 uses a patented approach to sum the phase currents into a single temperature compensated total current signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and CSREF. The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground, the capacitor is used to ensure that the CSREF voltage signal integrity. The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature.

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− +

U1A

Rph4 Rph3 Rph2 Rph1 Rref4 10 Rfer3 10 Rref2 10 Rref1 10

R9

R R10

R Cref 1nF

Ccs1

Ccs2

tRT1

100k CSREF

CSN2 CSN1

CSN4 CSN3

SWN2 SWN1

SWN4 SWN3

0

CSSUM

CSCOMP

Figure 7.

The DC gain equation for the current sensing:

VCSCOMP−CSREF+Rcs2)Rcs1^Rcs1*Rth)Rth

Rph *

ǒ

Iout_Total* DCR

Ǔ

Set the gain by adjusting the value of the Rph resistors. The DC gain should be set to the output voltage droop. If the voltage from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp.

This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain of the amplifier should be set to provide ~100mV across the current limit programming resistor at full load. The values of Rcs1 and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider.

The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. It is best to fine tune this filter during transient testing.

F_z+ DCR@25°C 2 * PI * L_Phase

Programming the Current Limit

The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on the CSCOMP−CSREF voltage as shown below.

R_LIMIT+

Rcs2)Rcs1*Rth Rcs1)Rth

Rph *ǒIout_LIMIT* DCRǓ

10m or R_LIMIT+lVCSCOMP−CSREF@ILIMIT

10m

Programming IOUT

The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates a 2 V signal on IOUT. A pull−up resistor from 5 V VCC can be used to offset the IOUT signal positive if needed.

R_IOUT+ 2.0 V * R_LIMIT 10 *

Rcs2)Rcs1*Rth Rcs1)Rth

Rph *

ǒ

^Iout_{ICC_MAX}^{* DCR}

Ǔ

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Programming ICC_MAX

A resistor to Ground is monitored on startup and this sets the ICC_MAX value. 10 mA is sourced from these pins to generate a voltage on the program resistor. The resistor value should be no less than 10k.

ICC_MAX+R * 10mA * 256 A 2 V

Programming TSENSE

A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter.

A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification table for the thermal sensing voltage thresholds and source current.

Rcomp2

8.2K RNTC

100K Cfilter

0.1uF

AGND AGND

Rcomp1 0.0 TSENSE

Figure 8.

Precision Oscillator

A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit.

This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 280 kHz to 650 kHz on the NCP81142 The graph below lists the resistor options and associated frequency setting.

NCP81142 Operating Frequency vs. R_osc

Figure 9. NCP81142 R_osc vs. Frequency

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The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other.

Programming the Ramp Feed−Forward Circuit

The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when the controller is disabled.

The PWM ramp time is changed according to the following, VRAMPpkäpkPP+0.1 * V_VRMP

Vin

Comp−IL Duty

Vramp_pp

PWM Comparators

The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP) and each phase current (I_L*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator generates the PWM output.

During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps.

PHASE DETECTION SEQUENCE

During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the CSN Pins. Normally, NCP81142 operates as a 4−phase Vcore PWM controller. Connecting CSN4 pin to VCC

programs 3−phase operation, connecting CSN2 and CSN4 pin to VCC programs 2−phase operation, connecting CSN2, CSN3 and CSN4 pin to VCC programs 1−phase operation. Prior to soft start, while ENABLE is high, CSN4 to CSN2 pins sink approximately 50 mA. An internal comparator checks the voltage of each pin versus a threshold of 4.5 V. If the pin is tied to VCC, its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold.

PWM1 is low during the phase detection interval, which takes 30 ms. After this time, if the remaining CSN outputs are not pulled to V_CC, the 50 mA current sink is removed, and NCP81142 functions as normal 4 phase controller. If the CSNs are pulled to V_CC, the 50 mA current source is removed, and the outputs are driven into a high impedance state.

The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP5901 and NCP5911 .Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one PWM output can be on at the same time to allow overlapping phases.

PROTECTION FEATURES

Under voltage Lockouts

There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81142 monitors the VCC Shunt supply. The gate driver monitors both the gate driver V_CC and the BST voltage. When the voltage on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will hold DRON low for a minimum period of time to allow the controller to hold off it’s startup sequence. In this case the PWM is set to the MID state to begin soft start.

Gate Driver UVLO Restart

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Figure 10.

Soft Start

Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the predetermined rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and for setting internal registers. After the configuration data is collected, if the controller is enabled the PWMs will be set to 2.0 V MID state to indicate that the drivers should be in diode mode. DRON will then be asserted. As the DAC ramps the PWM outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller is disabled the PWM signal will return to the MID state.

Figure 11.

Over Current Latch− Off Protection

The NCP81142 compares a programmable current−limit set point to the voltage from the output of the current−summing amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current I_CL.If the current generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (I_CL), an internal

m

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On startup a clim1/clim2 current limit protection is enabled once the output voltage has exceeded 250 mV or if the internal DAC voltage has increased above 300 mV, this allow for protection again a Vout short to ground. This is necessary because the voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current balance circuitry.

The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equation:

R_ILIM+I_LIM* DCR * R_CSńR_PH I_CL

Where I_CL= 10 mA

R_PH R_PH

R_CS

RLIM

ILIM

CSCOMP CSSUM

R_PH R_PH

CSREF

Figure 12.

Under Voltage Monitor

The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300mV below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.

Over Voltage Protection

The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the DAC will be ramped down to 0 V. At the same time, the high side gate drivers are all turned off and the low side gate drivers are all turned on until the voltage falls to new DAC voltage 0.2 V. The part will stay in this mode until the VCC voltage or EN is toggled.

UVLO RISING

2.9 V

DRON DAC

OVP Threshold

DAC + ~400 mV OVP Threshold Behavior VCC

Figure 13. OVP Threshold Behavior

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OVP Threshold

Vout

OVP Behavior at Startup

2.9 V

DAC

DRON

PWM

Figure 14. OVP Behavior at Startup

DAC

VSP_VSN OVP Threshold

Latch Off OVP

Triggered

PWM

Figure 15. OVP During Normal Operation Mode

During start up, the OVP threshold is set to 2.9 V. This allows the controller to start up without false triggering the OVP.

ORDERING INFORMATION

Device Package Shipping^†

NCP81142MNTXG QFN32

(Pb−Free)

4000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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QFN32 4x4, 0.4P CASE 485CD

ISSUE A

DATE 09 OCT 2012 SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

ÇÇÇ

D A

E B

C 0.10

PIN ONE REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

A

D2 K

E2 C C

0.10 C 0.05

C 0.05

A1 _SEATING

PLANE

e

32X

NOTE 3

b

32X

C C

A B

DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 b 0.15 0.25

D 4.00 BSC

D2 2.60 2.80

E 4.00 BSC

E2 2.60 2.80

e 0.40 BSC

L 0.25 0.45

9

17

25

32X

0.40PITCH 4.30

0.58

4.30

DIMENSIONS: MILLIMETERS

0.2532X 1

1

L

A3 0.20 REF

MOUNTING FOOTPRINT

NOTE 4

XXXXX = Specific Device Code A = Assembly Location L = Wafer Lot

Y = Year

W = Work Week G = Pb−Free Package

GENERIC MARKING DIAGRAM*

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present.

XXXXXX XXXXXX ALYWG

G

(Note: Microdot may be in either location) A3

DETAIL B

2.80

1 PACKAGE

OUTLINE DETAIL A

L1

DETAIL A L

ALTERNATE TERMINAL CONSTRUCTIONS

L

ÉÉ ÉÉ

DETAIL BÉÉ

MOLD CMPD EXPOSED Cu

ALTERNATE CONSTRUCTION

L1 −−− 0.15

DETAIL C

CORNER LEAD CONSTRUCTION

K2

DETAIL C

0.10 C A BB 0.10 C A BB

0.07 M

0.05 M

K2K 0.45 REF0.30 REF

RECOMMENDED

8XC0.08

4X

PACKAGE DIMENSIONS

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