Peak, valley and averaged Input Current (A)

(1)

Interleaved PFC

(2)

Agenda

Introduction:

Basics of interleaving

Main benefits

NCP1631: a novel controller for interleaved PFC

Out-of-phase management

The NCP1631 allows the use of smaller inductors

Main functions

Experimental results and performance

General waveforms

Efficiency

Conclusion

(3)

Two small PFC stages delivering (P_in(avg)/ 2) in lieu of a single big one

If the two phases are out-of-phase, the resulting currents (I_L(tot)) and (I_D(tot)) exhibit a dramatically reduced ripple.

Interleaved PFC

EMI Filter Ac line

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( )

V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( )

V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( )

V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

(4)

Interleaved Benefits

More components but:

A 150 W PFC is easier to design than a 300 W one

Modular approach

Better heating distribution

Extended range for Critical Conduction Mode (CrM)

Smaller components

(help meet strict form factor needs – e.g., flat panels)

Two DCM PFCs look like a CCM PFC converter…

• Eases EMI filtering and reduces the output rms current

(5)

Input and Output Current

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( ) V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( ) V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

LOAD

1 2 3

4 5

8

6 7

1 2 3

4 5

8

6 7

NCP1601 NCP1601

in( ) V t

Vout ( )

L tot

I I_L₂

1

IL

2

ID 1

ID

Cbulk

in( ) I t

( ) D tot

I

What is the ripple of the I_L(tot) total input

current?

What is the ripple of the I_D(tot) total output

current?

(6)

Input Current Ripple at Low Line

When V_in remains lower than V_out/ 2, the input current looks like that of a CCM, hysteretic PFC

(I_L(tot)) swings between two nearly sinusoidal envelops

Peak, averaged and valley current @ 90 Vrms, 320 W input (Vout = 390 V)

0 1 2 3 4 5 6 7

0.00% 25.00% 50.00% 75.00% 100.00%

time as a percentage of a period (%) Peak, valley and averaged Input Current (A)

Envelop for the peak currents

Envelop for the valley currents

I_in(t) I_L(tot)

(7)

Input Current Ripple at High Lline

When V_in exceeds (V_out/ 2), the valley current is constant!

It equates where R_in is the PFC input impedance

Peak, averaged and valley current @ 230 Vrms, 320 W input (Vout = 390 V)

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.00% 25.00% 50.00% 75.00% 100.00%

time as a percentage of a period (%) Peak, valley and averaged Input Current (A)

No ripple when V_in = V_out / 2

2

out in

V R

⎛ ⎞

⎜ ⎟

⎜ ⋅ ⎟

⎝ ⎠

( )

2

( ) 2

2

in avg out out in rms in

P V V

V R

⋅ =

⋅ ⋅ I_in(t)

I_L(tot)

(8)

Line Input Current

For each branch, somewhere within the sinusoid:

The sum of the two averaged, sinusoidal phases currents gives the total line current:

Assuming a perfect current balacing:

( ) ¹ ²

2

sw sw sw

in L tot T L T L T

I = I = I + I

1 2

2 2

sw sw

L T L T in

I I I

⋅ = ⋅ =

I_L1

1 s w

L T

I 2 1

L Ts w

⋅ I I_L1

1 s w

L T

I 2 1

L Ts w

⋅ I

(9)

Ac Component of the Refueling Current

The refueling current (output diode(s) current) depends on the mode:

Phase 1 Phase 2

Single phase CCM Single phase CrM Interleaved CrM

2 3

in in

out

I V

⋅ V 2

3

in in

out

I V

⋅ V

rms value over T_sw rms value

over T_sw rms value

over T_sw

in in

out

I V

⋅ V

2⋅I_in

Iin I_in I_in

(10)

A Reduced Rms Current in the Bulk Capacitor

Integration over the sinusoid leads to (resistive load):

Interleaving dramatically reduces the rms currents

Îreduced losses, lower heating, increased reliability Diode(s) rms

current (I_D(rms))

ID(tot)(rms) = 1.5 A I_C(rms) = 1.3 A I_D(rms) = 2.2 A

I_C(rms) = 2.1 A I_D(rms) = 1.9 A

I_C(rms) = 1.7 A 300 W,

V_out=390 V V_in(rms)=90 V

Capacitor rms current

(I_C(rms))

Interleaved CrM or FCCrM* PFC Single phase CrM or

FCCrM* PFC Single phase CCM

PFC

2

( )

32 2 9

out

out in rms out out

P

V V V

η π

⎛ ⎞

⋅ ⎜⎝ ⎟⎠ − ⎜⎛⎜ ⎞⎟⎟

⋅ ⋅ ⎝ ⎠

2

( )

16 2 9

out

P

V V V

η π

⎛ ⎞

⋅ ⎜⎝ ⎟⎠ − ⎜⎛⎜ ⎞⎟⎟

⋅ ⋅ ⎝ ⎠

2

( )

8 2 3

out

P

V V V

η π

⎛ ⎞

⋅ ⎜⎝ ⎟⎠ − ⎜⎛⎜ ⎞⎟⎟

⋅ ⋅ ⎝ ⎠

2

( )

2 8 2 3 3

out

in rms out

P

V V

η π

⎛ ⎞

⋅ ⎜ ⎟

⎝ ⎠

⋅ ⋅ ⋅

2

( )

2 8 2

3 3

out

in rms out

P

V V

η π

⎛ ⎞

⋅ ⎜ ⎟

⎝ ⎠

⋅ ⋅ ⋅

2

( )

8 2 3

out

in rms out

P

V V

η π

⎛ ⎞

⋅ ⎜ ⎟

⎝ ⎠

⋅ ⋅

(11)

Finally…

Interleaved PFC combines:

The advantages of CrM operations

• No need for low t_rr diode

• High efficiency

A reduced input current ripple and a minimized rms current in the bulk capacitor

A better distribution of heating

More components but “small” ones

Well adapted to slim form factor applications such as notebook adapters and LCD TVs

Refer to application note AND8355 for more details

(12)

Agenda

Introduction:

Main benefits

Main functions

General waveforms

Efficiency

Conclusion

(13)

NCP1631 Overview

Interleaved, 2-phase PFC controller

Frequency Clamped Critical conduction Mode (FCCrM) to optimize the efficiency over the load range.

Substantial out-of-phase operation in all conditions including start-up, OCP or transient sequences.

Feedforward for improved loop compensation

Eased design of the downstream converter:

pfcOK, dynamic response enhancer, standby management

High protection level:

Brown-out protection, accurate 1-pin current limitation, in-rush currents detection, separate pin for (programmable) OVP…

(14)

NCP1631 Overview

Interleaved, 2-phase PFC controller

Zero voltage detection (branch1)

• Fixes the max. on-time

• Feed-forward

One CS pin to sense the total input current for Over-

Current Protection and Inrush detection Latch input: if V_Latch > 2.5 V, the controller shutdowns Fixes the max. switching frequency

Adjusts the regulation loop bandwidth Adjusts the Frequency Foldback

characteristic

Brown-out detection with a 50-ms blanking delay to meet hold-up time requirements

Over and Under voltage protection (OVP, UVP)

High (5 V) when PFC is ready (steady state) Zero voltage

detection (branch2)

(15)

NCP1631 Typical Application

Synchronization of phases is completely internal

Vin

LOAD D

R

Vout

Cin

C I

1

2

3

4 13

16

14 15

5

6

7

8 9

12

10 11

Vcc pfcOK

Rocp Rzcd1 Rzcd2

2

bulk L2

L1

M1

M2

D1 coil2

Icoil1

Iin Cosc

Cp Cz Rz

Rt RFF Rout2

Rout1 Vout

Rbo1

Rbo2

Cbo2

OVPin OVPin

sense Vaux2

Vaux2

Rout3 FB

BO

1 current sense resistor Indicates the downstream converter that the PFC is ready

(16)

Interleaving: Master / Slave Approach…

The master branch operates freely

The slave follows with a 180° phase shift

Main challenge: maintaining the CrM operation (no CCM, no dead-time)

2 Tsw

Current mode: inductor unbalance Voltage mode: on-time shift

2 Tsw

L₂ < L₁

(17)

Interleaving: Interactive-Phase Approach…

Each phase properly operates in CrM

The two branches interact to set the 180° phase shift

Main challenge: to keep the proper phase shift

We selected this approach

2 Tsw

CrM operation is maintained but a perturbation of the on-time may

degrade the 180° phase shift On-time perturbation for one phase

(18)

Interleaving Management

The oscillator manages the out-of-phase operation

It acts as the interleaved clocks generator

5 V

4 V

(19)

Current Balancing between the 2 Branches

The NCP1631 operates in voltage mode

Same on-time and hence switching period in the two branches

An imbalance in the inductors:

Does not affect the switching period

“Only” causes a difference in the power amount conveyed by each branch

The two branches remains synchronized

CrM operation is kept (or FCCrM)

No alteration of the 180 degree phase shift

Phase 1 Phase 2

t_on time

t_on

L₁> L₂

(1) 2

(2) 1

in in

I L

I = L

(20)

Artificial Unbalancing

In this test, the 150 µH inductor of branch 1 is replaced by a 300 µH coil !!!!

Hence, more current is drawn by branch2 and MOSFET of branch2 is (normally) hotter

The following plots show how the PFC stage behaves in these extreme conditions and full load

(21)

Still Operates in a Robust Manner…

120 Vrms, 0.8 A (PF = 0.997, THD = 6%)

230 Vrms, 0.8 A (PF = 0.980, THD = 11%)

I_line(5 A/ div)

I_in(2 A/div) I_line(5 A/ div)

Zoom

DRV2 (10 V/div) DRV2 (10 V/div)

DRV2 (10 V/div)

DRV2 (10 V/div) I_in(5 A/div)

I_in(2 A/div) I_in(5 A/div)

DRV2 DRV2

OSC pin voltage (5 V/ div) OSC pin voltage (5 V/ div)

(22)

Switching Frequency Variations in CrM

Normalized fsw variations within the ac line sinusoid (Vin,rms = 90 V, Vout = 400 V)

0.00 0.50 1.00 1.50

0.00 1.00 2.00 3.00

ωt

Normalized f_sw (at the sinusoid top) vs V_in,rms

0.50 1.00 1.50 2.00 2.50

80 110 140 170 200 230 260 V_in,rms (V)

fsw / fsw(90)

The switching frequency varies versus the input power, the ac line amplitude and within the sinusoid

f_sw becomes high at light load, leading to large switching losses

f_sw should be limited

f_sw (normalized) vs P_in

0 5 10 15 20

0 50 100 150 200

fsw/ fsw(200W)

f_swbecomes large

V_in(t)

(23)

Limiting f

_sw

to Optimize the Efficiency

At the top of the sinusoid:

CrM operation requires large inductors to limit the switching losses at light load

Can’t we clamp f_sw not to over-dimension L?

Î Frequency Clamped Critical conduction Mode (FCCrM)

(

^,

)

,

2 4 1

in pk in pk

sw

in avg out

V V

f L P V

⎛ ⎞

= ⋅ ⋅ ⎜⎜⎝ − ⎟⎟⎠

(24)

Frequency Clamped Critical Conduction Mode

At light load, the current cycle is short

When shorter than the oscillator period, no new cycle until the oscillator period is elapsed Î dead-times (DCM)

On-times are increased to compensate the dead-times Î no PF degradation (ON proprietary)

(25)

NCP1631 Operation - FCCrM

In FCCrM, the switching frequency is clamped:

Fixed frequency in light load mode and near the line zero crossing

Critical conduction mode (CrM) achieved at full load.

FCCrM optimizes the efficiency over the load range.

FCCrM reduces the range of frequencies to be filtered (EMI)

FCCrM allows the use of smaller inductors

No need for large inductances to limit the frequency range!

E.g., 150 µH (PQ2620) for a wide mains 300-W application

Frequency Foldback reduces the clamp fequency at light load to further improve the efficiency

(26)

NCP1631 Frequency Foldback

The clamp frequency linearly decays when P_in goes below a preset level (P_LL)

P_LL is programmed by the pin6 resistor ^{( )}_{( )}ⁱⁿ ^FF ^pin⁶_1.66¹⁰⁵ ₁₅₈₁₀^pin⁶

in HL

P R µA R

P

= ⋅ ≅

Pin 6 pins out a voltage proportional to the power. The I_FFcurrent is clamped to

105µA and used to charge and discharge the oscillator capacitor

Gradual decay of the clamp frequency

No discontinuity in the operation

A resistor across the oscillator capacitor sets a minimum clamp frequency

Load (%)

Example: FF at 40% load and a 130 kHz nominal frequency

0 20 40 60 80 100 120 140 160

0 20 40 60 80 100

F_sw(max)nom F_sw(max)

I_FF

105 µA

(P_in)_HLis the max. power deliverable by the PFC stage

(27)

Light Load Operation

Full load, 90 V

CrM at heavy load conditions

Dead-time

Input current (2 A / div)

V_aux1 (10 V/div)

V_aux2(10 V/div)

25% load, 90 V

Frequency is reduced at light load Î Heavy DCM operation to reduce the switching losses

(28)

No Load Consumption

Measured on the 300 W NCP1631 demoboard

External V_cc, 3 * 680 kΩ resistors to discharge the X2 capacitors

Frequency Foldback improves the efficiency in light load but also in

230 115 230 115 230 115

Line Voltage

(V)

82

Frequency Foldback (R_FF= 4.7 kΩ) 38

one V_outsensing network for FB and OVP for a total 48-µA leakage on the V_out rail

134

Frequency Foldback (R_FF= 4.7 kΩ) 96

2 separate V_outsensing networks for FB and OVP for a total 185-µA leakage on the V_out rail (*)

138

No Frequency Foldback (pin6 grounded) 107

2 separate V_outsensing networks for FB and OVP for a total 185-µA leakage on theV_out rail

Input Power

(mW) Conditions

(29)

NCP1631 Fault Management

Brown-out

Undervoltage protection Latch-off condition

Die overtemperature

Too low current sourced by the Rt pin

Improper Vcc level for operation

In OFF mode, the major part of the circuit sleeps and consumption is minimized to < 500 µA

(30)

NCP1631 Over Current Protection

( CS in) ( OCP CS) ⁰ CS ^CS in OCP

R I R I I R I

− ⋅ + ⋅ = ⇒ = R ⋅

1) NCP1631 monitors a negative voltage, V_CS, proportional to the current drawn by

3) If I_CS exceeds 210uA, OCP is triggered 2) I_CScurrent maintains 0 V on CS pin

Select R_CS freely (optimally)

R_OCP sets the current limit

Minimized losses in R_CS

(31)

NCP1631 Overcurrent Protection

When I_CS > 210 μA, the OCP switch closes and a current equal to 0.5*(I_CS – 210 μA) is injected into the negative input of the V_TON processing opamp

Î the on-time sharply reduces proportionally to the magnitude of the over- current event.

No discontinuity in the operation, out-of- phase operation is maintained

No need for preventing OCP from tripping during a normal transient

The current can be accurately limited

I_line(2 A/div) I_in(2 A/ div)

V_control(1 V/div)

I_line(2 A/div) I_in(2 A/ div)

V_control(1 V/div)

(32)

NCP1631 In-rush Current Detection

Disables output drive when signal is high (I_CS > 14μA)

(7% of I_ILIMIT)

Circuitry to ground the In- rush protection once the circuit begins operation

When plugged into the mains, the bulk capacitor is abruptly charged to

the line voltage and the charge current (in-rush current) is huge.

Drive turn-on during this time can damage the MOSFETs.

(33)

NCP1631 Over Voltage Protection

Separate pins for FB and OVP (redundancy)

The two functions share the same 2.5 V internal reference for an eased and accurate setting of the OVP level

( ) 3

( ) 2

V^{out ovp} 1 ^out

out nom out

R V = + R

Method 1: One feed-back network for OVP and FB Method 2: Two separate feed-back networks

( ) 1 2 2

V_{out ovp} _ovp _ovp

out

out nom out out ovp

R R R

V R R R

= + ⋅

+

(34)

Brown-out Protection with a 50 ms Blanking Time

Mains interruptions shorter than 50 ms are ignored

The blanking time helps meet hold-up time requirements

Ac line current (2 A / div)

V_bulk(100 V/div)

V_in (100 V/div)

BO pin voltage (1 V/div)

For the blanking time, the BO pin voltage is maintained around the

BO threshold not to delay the circuit restart

when the line has recovered

20-ms line interruption

(35)

NCP1631 PfcOK / REF5V Signal

The pfcOK signal can be used to enable/disable the downstream converter.

It is high (5 V) when the PFC stage is in normal operation and low otherwise.

The pfcOK signal is low:

Any time the PFC is off because a major fault is detected

(UVLO condition, thermal shutdown,UVP, Brown-out, Latch-off / shutdown, R_t pin open)

For the start-up phase of the PFC stage until the nominal bulk voltage is obtained

The pfcOK pin can be used as a 5 V power source (5 mA capability)

(36)

A (simple but easy to use) Excel Spreadsheet (www.onsemi.com)

(37)

Agenda

Introduction:

Main benefits

Main functions

General waveforms

Efficiency

Conclusion

(38)

NCP1631 Demoboard

Wide mains, 300 W, PFC pre-converter

NCP1631

MUR550

(39)

+

- IN

U1 KBU6K

C5 100nF

C6 1µF Type = X2

CM1

85-265 Vrms L N Earth

C10 4.7nF Type = Y1

C16 4.7nF Type = Y1 C18

680nF

L4 150µH

D5 MUR550

R24 50m (3W) Vin

R18 560k

C2 100 µF/450V X7

Vcc R25

27k

R15 22k X6

IPP50R250

D4 MUR550

pfcOK X1

X4 IPP50R250

R1 1.8k R14

22k

Iin C25 R36 1µF 33k

R33 18k

R40 27k R46

120k

R37 4.7k

+ -

15V +

- 390V

R41 1800k

R42

1800k R43

1800k R44 1800k

C22 1nF

R38 1800k

R23 820k R39 1800k

R32 1800k

R31 1800k

C27 1nF R20

10k D15

1N4148

Q2 2N2907

R17 2.2

R11 10k D14

1N4148

Q1 2N2907

R7 2.2

DRV2 DRV2

C32 100 µF/25V

C33 100nF C30

100nF

D21 15V

R2 1k C34 10nF D16

1N5406

Vout

D17 1N5406 C20

150nF C15 220pF

C28 220nF

R34 270k

R121 680k

R122 680k R123 680k

R16 0

Vaux1

DRV1

Vaux2 R21

0

1 2 3 4 5

8 6 7

9 10 11 12 13 14 15 16

U2 S4

S5 D18

NC

D20 NC

DRV1 Vaux2

C21 NC

C29 NC

Vaux1

R6 1k D3 LED

D6 1N4148

D2 NC

C31 NC

D19 NC R47 NC Vaux1 OVPin

OVPin C7

NC

R12 NC D22

NC DRV1

D23 NC DRV2

NCP1631 Demoboard Schematic

300 W, wide mains PFC pre-converter

The circuit is latched off if V_cc exceeds 17.5 V.

Could be used for thermal protection

(40)

Input Voltage and Current

As expected, the input current looks like a CCM one

At high line, frequency foldback influences the ripple

Full load, 120 V_rms I_line (5 A/div)

V_in (100 V/div)

I_L(tot)(5 A /div)

I_line (5 A/div)

V_in (200 V/div)

I_L(tot)(2 A /div) Full load, 230 V_rms

(41)

Zoom of the Precedent Plots

These plots were obtained at the sinusoid top

The current swings at twice the frequency of each phase

At low and high line, the phase shift is substantially 180°

Full load, 90 V_rms Full load, 230 V_rms

I_L(tot) (2 A/div)

DRV1

I_L(tot) (1 A/div) DRV2

DRV1 DRV2

(42)

Refueling Sequences

CrM at low line with valley switching

Fixed frequency operation at high line (frequency clamp)

Out-of-phase operation in both cases

Full load, 90 V_rms Full load, 230 V_rms

I_L(tot) (2 A/div)

I_L(tot) (1 A/div)

V_ZCD1 V_ZCD2

V_ZCD1

V_ZCD2

(43)

Efficiency Measurements

The output voltage is generally 390 V

For a 300 W application, the output current is:

770 mA at full load

154 mA at 20% of the load

Both currents are generally measured with the same tool

If @ 20% of the load, the input power is 63 W

1-mA error in I_out leads to

I_out = 153 mA Î Eff = 100 x 390 x 0.153 / 63 = 94.7 %

I_out = 155 mA Î Eff = 100 x 390 x 0.155 / 63 = 95.9 %

A 1-mA error causes a 1.2% difference in the efficiency!

Measurements @ 10% and 20% of the load need care!!!

(44)

Efficiency Measurements

The efficiency does not only depend on the control mode

The inductor, the MOSFETs, diodes, EMI filter… play a role

For instance, if we compare the efficiency with a 200 µH PQ2625 inductor to that with a 150 µH PQ2620 one:

Efficiency @ 230 V

96.4 96.6 96.8 97.0 97.2 97.4 97.6 97.8 98.0 98.2

0 20 40 60 80 100 120

Efficiency (%)

200 µH 150 µH

Frequency Foldback limits the difference at

light load

(45)

Demoboard Efficiency

In the 20% to 100% range, the efficiency remains:

> 95.8% at low line

> 97.0 % at high line

Refer to NCP1631EVB/D at www.onsemi.com for details

92.00 93.00 94.00 95.00 96.00 97.00 98.00 99.00

0 20 40 60 80 100 120

Load (%)

Efficiency (%)

115V 230V

(46)

Tweaking Frequency Foldback …

A resistor can be added between

the pfcOK (5 V) and frequency foldback pins

2

1

R1

R2

pfcOK / 5V

FF pin

f_sw(max)

V_REGUL

2 105 R ⋅ µA f_sw(max)

V_REGUL

2 105 R ⋅ µA

(V is proportional to the PFC power) Programmable minimum frequency

Programmable nominal frequency ^fsw(max)

V_REGUL

( )

2 1

1 2

5 105

R V R µA

R R

⋅ + ⋅

+

2

1 2

5

REGUL

R V

V R R

= ⋅ +

f_sw(max)

V_REGUL

( )

2 1

1 2

5 105

R V R µA

R R

⋅ + ⋅

+

2

1 2

5

REGUL

R V

V R R

= ⋅

R1 addition +

Doing so, the frequency clamp decays more sharply:

(47)

Efficiency Improvement

A resistor on the oscillator pin sets the minimum frequency

With R₁, the PFC stage operates at the minimum frequency (20 kHz) at 10% and 20% of the load

The tweak further improves the light load efficiency

92.00 93.00 94.00 95.00 96.00 97.00 98.00 99.00

0 10 20 30 40 50 60 70 80 90 100

Load (%)

Efficiency (%)

115V 230V

92.00 93.00 94.00 95.00 96.00 97.00 98.00 99.00

0 10 20 30 40 50 60 70 80 90 100

Load (%)

Efficiency (%)

115V 230V

95% 95%

R1 addition

1% 1%

(48)

Agenda

Introduction:

Main benefits

Main functions

General waveforms

Efficiency

Conclusion

(49)

Conclusion

Interleaved PFC allows use of smaller components,

improves thermal performance, increases the CrM power range and reduces current ripple.

The NCP1631 provides a single IC solution which

incorporates all the features necessary for building a robust and compact 2-phase interleaved PFC stage with minimal external components.

Its FCCrM and frequency foldback allows an efficient operation over the load range with small inductors

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For More Information

View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com

View reference designs, design notes, and other material supporting the design of highly efficient power supplies at

www.onsemi.com/powersupplies