IMPACT OF IC TECHNOLOGY ON THE
POWER PROCESSING INDUSTRY
Dhaval Dalal Brant Johnson
Technical Marketing Director Senior Systems Engineer
PSMA Perspective - 5 Year Roadmap
Optimal Topologies Better ICs &
Power Semiconductors
Better Components Hot Swap Infrastructure
More Integration Better Components Higher Frequency ICs
Lower Losses Power Semi’s Optimal Topologies
Thermal Design Integration
Design Software Models Kit Solutions Technical Support
More Integration Better/Cost Effective
Components (ICs, Power Semi’s)
Optimal Topologies
Optimal Topologies Better Components
ICs
Power Semi’s
What drives the PSMA requirements and how do we satisfy them?
How is IC technology evolving?
What will this progress mean to the power industry?
How IC technology itself provides solutions to the problems we face.
Examples of how IC technologies are enablers for power solutions.
Moore’s Law in Action
From Intel Technology Symposium September 2003
IC technology progress will enable Intel to build processors with more than a billion transistors, running at about 20 GHz by 2010.
IC Technology -
Challenges to Overcome
¾ As Gate lengths continue to shrink, Gate leakage becomes excessive. SiO2 limit ~ 23 Angstroms
¾ Using higher K dielectrics (SiO2 = 4.5) required for thicker gate Tox
¾ Short channel lengths require shallower SD junctions.
Higher doping required to maintain low resistance.
¾ Limits approached as devices approach atomic dimensions.
Digital CMOS Technology Migration
Supply Voltage: Vdd = 5V 3.5V >> 2.5V 2.5V >> 2.0V < 1.5V <1.0V
Production Year: ’92 ’95 ’98 ’01 ’03 ‘04
Delay per Logic Stage (ps)
1000
100
10
3.0 um 2.0 um 1.0 um 0.5 um 0.3 um 0.2 um 0.1 um 0.05 um
Desktop CPU Current Trend
0 50 100 150 200 250
2000 2002 2004 2006 2008 2010 Year
Amps
Data from ITRS (International Technology Roadmap for Semiconductors)
BY 2008, Vcc will fall from 1.3 to 0.8 volts and Icc will rise to 150 amps.
Load slew rates will dictate higher controller bandwidth & lower Zout
60 Amp Transient Load Step
Step load from 10 to 70 amps
Load slew rate is approximately
150 amps / us
Three phase controller solution
from Fred Lee’s “High frequency solutions for 12 volt VR”
CPES September, 2003
¾New circuit techniques required as part of future solutions
Power Industry Challenges
¾ Increased current requirements at ever lower voltages
New power devices required
¾ Increased load transients caused by faster switching components.
Faster power switching required
¾ Current circuit approaches untenable due space constraints
New more space efficient circuit topology required.
Power solutions from this technology
¾ Shorter channel lengths lead to:
Improved RDS(on) cm2 Improved cells per cm2
¾ Single and dual Resurf from improved process control drive:
Higher voltage, higher cell density power devices
¾ Copper metallization
Lower thermal resistance Lower parasitic resistance
¾ Leadless packaging
Improved thermal resistance
Projected Power MOS Cell Density
0 60 120 180 240 300
1995 2000 2005 2010
Year
Cell Density M/in2
Current Conduction Channel Forms along the Gate Oxide Periphery Current Conduction Channel Forms along the Gate Oxide Periphery
Source Source Region Region
GateGate Oxide Oxide
Polysilicon or other Conductive Material Polysilicon or other Conductive Material
Minimum Minimum Cell Pitch Cell Pitch Minimum
Minimum Cell Pitch Cell Pitch
50% packing density improvement from strip to cell topology
0 0.5 1 1.5 2 2.5 3
10 100 1000
Cell Density (MCells / in2)
Effective Channel Density (um / um2)
Cell Stripe
Improved density using cells
Current stripe capability
Comparison of Trench and DMOS Structures
• Trench solves JFET issue
• proves higher cell density DMOS Structure
Trench Structure
N+N+
GateGate
Future Technology
Trench generated P regions and single Epi layer to
provide die size improvement
Existing Technology Existing Technology
Multiple
Multiple EpiEpi layerslayers Multiple P implants
Source Source
Multiple P implants
Multiple Multiple EpiEpi LayersLayers
P Regions shape space charge widening and allows device to
be smaller Drain
Drain
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Minimum Feature Size (um)
High Density BCD Tends
BCD Industry Trends BCD Industry Trends
01 02 03 04 05 06 07 08 09 10
Year
Packaging Technology…
SC-59
SOT-23 SC-70 SC-75
SOD-523 SOD-323
SC-101 1stgen.
SC-89
SOT-723 SC-88
Clip Bonded
Power Packages Smaller
Scale
Wire Bonded
Power Packages
6ld 5ld 3ld 2ld
SC-74A/TSOP5 SC-88A
DPAK D2PAK
SMB
SMA
PowerMite SOD-123FL
SO8-FL SC-59EP TSSOP
Technology Driver
+8ld
Micro-x
SOIC QFN
US-x
SC-74/TSOP6 SOT-563 SOT-963
SOT-953 SOT-553
SC-101 2ndgen.
SOD-123 SOD-723
SOT-89 SO8-FL
SC-59EP SOT-223
SMC
Existing 2004 2005
Fully integrated IC and Power delivery System
From Intel Technology Symposium September 2003
High Power Notebook Adapter with PFC
•Today’s mainstream power solutions are dominated by “ugly” passives (cost driven)
•Challenge for semiconductor vendors is to reduce the passive real estate with “smarter”
semiconductor solution kits – need optimum partitioning, advanced technologies
Power Trends Summary
¾ Insatiable demand for increased power density will drive innovative power designs to deliver
¾higher efficiency solutions.
¾low inductance thermally superior packaging.
¾ Higher frequency solutions will require higher levels of integration in lower inductance packages.
