This thesis reports emerging embedded nonvolatile memory solution for ultra low power microcontroller systems. This study is presented as measures to address the following three main points:
1. A dual-mode sensing scheme of capacitor-coupled EEPROM cell (Chapter 3) 2. A high-density and high-speed 1T-4MTJ MRAM with voltage offset self-reference
sensing scheme (Chapter 4)
3. A Power Management Scheme with Hierarchical Power Gating and Autonomous Standby Mode Transition Control for Normally-Off Multi-Sensor Network Applications (Chapter 5)
In Chapter 1, the background and objective of this study were prefaced. To realize the embedded nonvolatile memory solution for ultra-low power microcontroller systems, it should be overcome above mentioned challenges, which are low voltage operation, high reliability, high speed access, high density, low standby leakage current. In this thesis, author’s approach to overcome the challenge of embedded the nonvolatile memory and investigate that solution for ultra-low power microcontroller systems.
In Chapter 3, a dual-mode sensing (DMS) scheme of capacitor-coupled EEPROM cell for high speed accessibility and high reliability of write cycle endurance are proposed and estimated.
This memory cell combines an EEPROM cell with a DRAM cell, and the cell area penalty is estimated to be less than 10% compared with the conventional EEPROM cell. Using this DMS technique, the signal amplitude on the bit line is increased by 120% at 5 ns after word-line selection, and the sensing speed is enhanced by 36% at the cell current of 15 uA by virtue of the additional charge-mode sensing. Furthermore, the cell current can be decreased by 55%
compared with the current-mode only sensing scheme. Therefore, the stress applied to the tunnel oxide of the memory transistor can be relieved by decreasing the programming voltage and shortening the programming time, and it is possible to improve the endurance characteristics.
With this memory cell structure and sensing scheme, it is possible to realize high-speed sensing in low-voltage operation and high endurance. The capacitor-coupled EEPROM cell and the DMS scheme are promising candidates for high-performance EEPROM’s.
In Chapter 4, a high-density and high-speed 1T-4MTJ MRAM with voltage offset self-reference sensing scheme is proposed as the method for chip area reduction. A 1Mbit-MRAM with world’s first 1T-4MTJ cell structure has been verified by a 130nm CMOS process technology. By the self-reference sense amplifier with voltage offset scheme, high-speed
74
read access operation of 50MHz@4cycle and tAC=56nsec (Simulation result) has been achieved.
In 1T-4MTJ, the active area space in memory array is effectively utilized. The array area reduction of -35.7% become possible with the embedded WWL Driver architecture. By using 1T-1MTJ and 1T-4MTJ cells, on-chip hierarchical memory architecture composed of fast 1T-1MTJ cell for cache memory and small 1T-4MTJ cell for large-capacity memory is feasible.
An example of microcontroller design indicates a 20% chip size reduction with keeping a microcontroller performance, by incorporating data memory of 32Mb by 1T-4MTJ cell and fast program memory of 4Mb by 1T-1MTJ cell.
In Chapter 5, the low-power multi-sensor system with power management and nonvolatile memory access control for IoT applications, which achieves almost zero standby power at the no-operation modes, are presented. A power management scheme with activity localization can reduce the number of transitions between power-on and power-off modes with rescheduling and bundling task procedures. In addition, autonomously standby mode transition control selects the optimum standby mode of microcontrollers, reducing total power consumption. We demonstrate with evaluation board as a use case of IoT applications, observing 91 percent power reductions by adopting task scheduling and autonomously standby mode transition control combination.
Furthermore, we propose a new nonvolatile memory access control technology, and estimate the possibility for future low-power effect. These technologies are the most promising candidates for future embedded nonvolatile memory solution for ultra low power microcontroller systems.
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Publications
Major Papers
1) M. Hayashikoshi, H. Hidaka, K. Arimoto, and K. Fujishima, “A dual-mode sensing scheme of capacitor-coupled EEPROM cell,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp.
569-573, 1992.
2) Y. Terada, K. Kobayashi, T. Nakayama, M. Hayashikoshi, Y. Miyawaki, N. Ajika, H. Arima, T. Matsukawa, T. Yoshihara, “120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs,” IEEE J.
Solid-State Circuits, Vol. 24, no. 5, pp. 1244-1249, 1989.
3) K. Kobayashi, T. Nakayama, Y. Miyawaki, M. Hayashikoshi, Y. Terada, T. Yoshihara, “A high-speed parallel sensing architecture for multi-megabit flash E2PROMs,” IEEE J.
Solid-State Circuits, vol. 25, no. 1, pp. 79-83, 1990.
4) H. Hidaka, K. Arimoto, K. Hirayama, M. Hayashikoshi, M. Asakura, M. Tsukude, T. Oishi, S. Kawai, K. Suma, Y. Konishi, K. Tanaka, W. Wakamiya, Y. Ohno, K. Fujishima, “A 34-ns 16-Mb DRAM with controllable voltage down-converter,” IEEE J. Solid-State Circuits, vol.
27, no. 7, pp. 1020-1027, 1992.
5) M. Tsukude, K. Arimoto, H. Hidaka, Y. Konishi, M. Hayashikoshi, K. Suma, K. Fujishima,
“Highly reliable testing of ULSI memories with on-chip voltage-down converters,” IEEE Design & Test of Computers, vol. 10, no. 2, pp. 6-12, 1993.
6) T. Nakada, K. Okamoto, T. Komoda, S. Miwa, Y. Sato, H. Ueki, M. Hayashikoshi, T.
Shimizu, H. Nakamura, “Design Aid of Multi-core Embedded Systems with Energy Model,” IPSJ Transactions on Advanced Computing Systems, Vol. 7, No. 3, pp. 1 - 10, Aug., 2014.
7) T. Nakada, T. Hatanaka, H. Ueki, M. Hayashikoshi, T. Shimizu, and H. Nakamura, “An Energy-Efficient Task Scheduling for Near-realtime Systems with Execution Time Variation,” IEICE Trans. on Information and Systems, Vol. E100-D, No. 10, pp. 2493-2504, Oct. 2017.
8) M. Hayashikoshi, H. Ueki, H. Kawai, T. Shimizu, K. Nii, and Y. Matsuda, “Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications,” accepted to IEEE Transaction on Multi-Scale Computing Systems, 2018.
(9 pages)
82
Major Conferences
1) Y. Terada, K. Kobayashi, T. Nakayama, M. Hayashikoshi, Y. Miyawaki, N. Ajika, H. Arima, T. Matsukawa, T. Yoshihara, “120-ns 128 K*8b/64 K*16b CMOS EEPROMs,” Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International, pp. 136-137, 1989.
2) K. Kobayashi, T. Nakayama, M. Hayashikoshi, Y. Miyawaki, Y. Terada, H. Arima, T.
Matsukawa, T. Yoshihara, “A self-timed dynamic sensing scheme for 5V only multi-Mb flash E/sup 2/PROMs,” IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 39-40, 1989.
3) Y. Terada, T. Nakayama, K. Kobayashi, M. Hayashikoshi, S. Kobayashi, Y. Miyawaki, N.
Ajika, T. Yoshihara, “High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture,” IEEE Symposium on VLSI Circuits, Dig.
Tech. Papers, pp. 97-98, 1990.
4) M. Hayashikoshi, H. Hidaka, K. Arimoto, and K. Fujishima, “A Dual-mode Sensing Scheme Of Capacitor Coupled EEPROM Cell For Super High Endurance,” IEEE Symposium on VLSI Circuits, Dig. Tech. Papers, pp. 89-90, 1991.
5) K. Arimoto, H. Hidaka, M. Hayashikoshi, M. Asakura, K. Fujishima, T. Yoshihara, “A 34ns 16MbDRAM with controllable voltage down convertor,” Solid-State Circuits Conference, ESSCIRC '91. Proceedings - Seventeenth European, vol. 1, pp. 21-24, 1991.
6) M. Tsukude, K. Arimoto, H. Hidaka, Y. Konishi, M. Hayashikoshi, “A Testing Technique for ULSI Memory with On-chip Voltage Down Converter,” Test Conference, Proceedings., International, p. 615, 1992.
7) H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, H. Furuta, S. Ueno, T. Oishi, M.
Hayashikoshi, H. Hidaka, “A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme,” IEEE Asian Solid-State Circuits Conference, pp.
303-306, 2006.
8) H. Tanizaki, T. Tsuji, J. Otani, Y. Yamaguchi, Y. Murai, M. Hayashikoshi, H. Hidaka, “A 1Mb High-Density Toggle-MRAM with Symmetrical Read/Write Operations,” 22nd IEEE Non-Volatile Semiconductor Memory Workshop, pp. 63-65, 2007.
9) M. Hayashikoshi, Y. Sato, H. Ueki, H. Kawai, and T. Shimizu, "Normally-off MCU architecture for low-power sensor node," in Proc. 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 12-16, Jan. 2014.
10) T. Nakada, T. Shigematsu, T. Komoda, S. Miwa, H. Nakamura, Y. Sato, H. Ueki, M.
Hayashikoshi, T. Shimizu, “Data-aware power management for periodic real-time systems with non-volatile memory,” IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), pp. 1-6, 2014.
11) M. Hayashikoshi, H. Ueki, H. Kawai, and T. Shimizu, " Normally-Off MCU Architecture and Power Management Method for Low-Power Sensor Network," in Proc. 12th
International SoC Design Conference (ISOCC), pp.151-152, Nov. 2015.
12) T. Nakada, K. Yanagihashi, H. Ueki, T. Tsuchiya, M. Hayashikoshi, H. Nakamura,
“Energy-Efficient Continuous Task Scheduling for Near Real-time Periodic Tasks,” The 8th IEEE International Conference on Internet of Things, 2015.
13) T. Nakada, T. Hatanaka, H. Ueki, M. Hayashikoshi, T. Shimizu, H. Nakamura: "An adaptive energy-efficient task scheduling with energy model," Annual Meeting on Advanced Computing System and Infrastructure (ACSI), Jan. 28 2015.
14) M. Hayashikoshi, H. Noda, H. Kawai, and H. Kondo, “Low-Power Multi-Sensor System with Normally-off Sensing Technology for IoT Applications,” in Proc. 13th International SoC Design Conference (ISOCC), pp. 195-196, Oct. 2016.
15) T. Nakada, T. Hatanaka, H. Ueki, M. Hayashikoshi, T. Shimizu, H. Nakamura: "An Adaptive Energy-Efficient Task Scheduling under Execution Time Variation based on Statistical Analysis," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (poster), 7 pages, Sep. 2016.
16) M. Hayashikoshi, H. Noda, H. Kawai, K. Nii, and H. Kondo, “Low-Power Multi-Sensor System with Task Scheduling and Autonomous Standby Mode Transition Control for IoT Applications,” in Proc. IEEE Symposium in Low-Power and High-Speed Chips, pp. 1-3, Apr. 2017.
17) T. Nakada, H. Yanagihashi, K. Imai, H. Ueki, T. Tsuchiya, M. Hayashikoshi, H. Nakamura:,
"Energy-aware Task Scheduling for Near Real-time Periodic Tasks on Heterogeneous Multicore Processors," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6 pages, Oct. 2017.
84
books
1) T. Nakada and H. Nakamura, "Normally-Off Computing," Springer Japan, 978-4-431-56503-1, 2017.
M. Hayashikoshi is in charge of Chapter 3: Non-volatile Memories, Chapter 5: Technologies for Realizing Normally-Off Computing, and Chapter 6: Research and Development of Normally-Off Computing—NEDO Project
Patents
United States Patents
1) 5,554,868 Semiconductor nonvolatile memory device 2) 5,297,096 Oscillation switch device
3) 4,970,727 Semiconductor memory device
4) 5,132,928 Semiconductor nonvolatile memory device 5) 5,321,646 Semiconductor dynamic memory device 6) 6,011,428 Power supply circuit and semiconductor device 7) 6,097,180 Power supply circuit and semiconductor device
8) 5,835,419 Semiconductor memory device to prevent malfunction due to disconnection of column select line and word line
9) 5,825,694 Semiconductor memory device to prevent malfunction due to disconnection of column select line and word line
10) 5,986,915 Semiconductor memory device to prevent malfunction due to disconnection of column select line and word line
11) 6,304,503 Semiconductor memory device 12) 6,483,761 Semiconductor memory device 13) 5,233,610 Semiconductor memory device
14) 6,088,819 Semiconductor dynamic memory device and test method
15) 5,956,281 Semiconductor memory device with shallow substrate voltage with disturb test mode and self refresh mode
16) 6,337,814 Semiconductor memory device with substrate voltage generator 17) 8,508,986 Semiconductor device
86
Japanese Patents
1) 特開平4-222994 不揮発性半導体記憶装置
2) 特開平4-14871 不揮発性半導体記憶装置及びその消去及び書き込み方法
3) 特開平4-208566 不揮発性半導体記憶装置
4) 特開平4-159694 不揮発性半導体記憶装置
5) 特開平4-82091 不揮発性半導体記憶装置
6) 特開平1-105396 不揮発性半導体記憶装置
7) 特開平1-130394 半導体記憶装置
8) 特開平2-35692 電気的に書換え可能な不揮発性半導体メモリ
9) 特開平2-78099 半導体記憶装置
10) 特開平2-66798 不揮発性半導体記憶装置
11) 特開平3-14272 不揮発性半導体記憶装置
12) 特開平3-5995 不揮発性半導体記憶装置 13) 特開平5-62461 半導体記憶装置
14) 特開平11-328951 半導体記憶装置
15) 特開平6-259150 電圧供給回路および内部降圧回路
16) 特開平6-60648 パルス信号発生回路および半導体記憶装置
17) 特開平6-21377 半導体記憶装置 18) 特開平7-30386 出力回路
19) 特開平10-199296 ダイナミック型半導体記憶装置およびそのテスト方法
20) 特開平11-86536 半導体記憶装置 21) 特開2002-237197 半導体記憶装置
22) 特開 2010-044460 電源制御装置、計算機システム、電源制御方法、電源制御プログ
ラムおよび記録媒体
23) 特開2010-097655 ＭＲＡＭ制御装置およびＭＲＡＭ制御方法
24) 特開2011-060082 メモリ制御装置 25) 特開2013-239220 半導体装置 26) 特開2012-094201 半導体装置
27) 特開2012-074110 半導体装置5503480
28) 特開2014-203185 情報処理装置および情報処理方法
29) 特開2014-203148 メモリ制御回路
30) 特開2014-203192 車両運行管理システム、端末装置、制御装置、および車両運行管
理方法
31) 特開2015-011474 半導体装置
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