3.3 Implementation
3.3.1 Integrator using Ring Amplifier
Fully-Differential Ring Amplifier
Figure 3.3(a) shows the schematic diagram of proposed fully differential ring ampli-fier. The core of fully differential ring amplifier is shown in Figure 3.3(b). while CC are added to the input nodes of amplifier to realize the amplifier input offset cancel-lation for the integrator. The amplifier is the key components of the modulator to
+ -+- R-AMP Φ2Φ2d16Cu
Φ1d
+ -+- R-AMP Φ2Φ2d Vcm
Φ1 8Cu 8CuVcm
SAR Quantizer withPassive Adder(4-bit) VU,p
Vo1,pVo2,p Φ1Φ1d 1st. Integrator2nd. Integrator
R A
Φ1 Φ2 R AΦ1 VU,p
Vo1,p
ΦC Φ2dΦ3d Vcm
Φ2Cu Φ3 Vcm 16 sets
DWA Control signal(DDWA<1...15>) of DAC switches are generated by DWA
15-bit
4-bit Φ3d Vcm
Φ2Cu Φ3 VRFP,NDDWA*Φ2d 15 sets
ΦC Vo1,nVo2,n Bootstrapped SwitchTop plate
Bottom plate
(b) (a)
Φ
1Φ
2Φ
3Φ
C ResetIntegrateSample1st. Integrator2nd. Integrator
SAR ADC Idle
Sum&SAR operation IntegrateSampleIdleReset Sample(Vo2)Sample(Vo1)Sample(VU) ResetIntegrateSampleIdle
Sum&SAR operation IntegrateSampleIdleReset
Sample(Vo2)Sample(Vo1)Sample(VU) R:Reset mode of Ring amplifer
A:Amplification mode of Ring amplifer
DATAD3D2D1D0D3D2D1D0 4-bit DAC
FIGURE 3.2: Circuit implementation of Proposed 2nd-order feed-forward delta sigma modulator using ring amplifier (R-AMP). (a)
Schematic diagram. (b) Clock timing chart.
3.3. Implementation 39
(a)
(b)
Bias Circuit
Φ
2Φ
2Φ
1dΦ
1dV
CMFBV
CMFBV
BNV
BNV
BNV
ONV
CMV
OPV
CMV
IPV
INV
OPV
ONM
CPM
CNM
CPM
CNR
OSR
OSM3 M1
M5 M6 Vdd
C
CC
LAC
LAV
INΦ
RdΦ
RdΦ
RdΦ
AdΦ
AdΦ"
Φ"
V
CMV
OPC
CΦ
AdΦ
RdΦ
Ad- +
+
-Core of R-AMP
V
ONV
IP:Reset mode of R-AMP
:Amplification mode of R-AMP
Φ
RΦ
AFIGURE3.3: Schematic of fully differential R-AMP (Ring-Amplifier).
(a) R-AMP (Ring-Amplifier). (b) Core of R-AMP.
realize the integrator, and it is the most power-hungry circuit block in the modula-tor. Ring amplifier for multiplying digital-to-analog converter (MDAC) circuit has been proposed and demonstrated to reduce the power of the pipeline ADC [5]. In this paper, the integrator using the ring amplifier is proposed to reduce the power consumption.
Figure 3.3(b) shows the core of fully differential ring amplifier with the self bias circuit and the common-mode-feedback (CMFB) circuit. The fully differential ring amplifier is constructed with cascaded three stage inverters, it is similar to a ring oscillator. In order to stabilize the ring amplifier, The resistor ROSis inserted at the output of the 2nd stage inverter as shown in the figure 3.3(b) to generate the different offset voltages to the gate of MCP and MCN. Moreover, the high threshold voltage MOSFET MCPand MCN are used in the 3rd stage to extend the stable offset voltage range for the integrator. As a result, there is no static current though MCPand MCN, the power consumption of integrator can be reduced dramatically. Because, MCPand MCNdo not need to be biased in the saturated region like as conventional amplifier, the rail-to-rail output is allowed for the ring amplifier. The main structure of the ring amplifier in the proposed delta sigma modulator is based on the ring amplifier in [7], however, the simplified the bias and CMFB circuits are proposed for low supply voltage in this work. In [7], a cascaded PMOS is inserted between M5 and M3 to reduce the thermal noise of the amplifier. Because the thermal noise requirement on the amplifier in the delta sigma modulator can be relaxed much more than that in a Nyquist-rate ADC, the cascaded PMOS is removed to relax the headroom voltage of amplifier under low supply voltage. Furthermore, the bias circuit for ring amplifier can also be more simplified, only one PMOS and one NMOS are used to generate the bias voltage VBNfor the ring amplifier.
Action of Ring Amplifier
Because the operation of the integrator using inverter is similar as the operation of the ring amplifier’s 3rd-stage, the operation of ring amplifier is discussed by means of the integrator using inverter for understanding the ring amplifier’s action.
Figure 3.4 illustrates the schematic diagram of integrator using dynamic amplifier
3.3. Implementation 41
inverter
IN OUT
C
SC
CC
FΦ
AΦ
AΦ
RΦ
RΦ
RΦ
AFIGURE3.4: Integrator using dynamic amplifier consist of inverter.
consist of inverter. The CS and the CF are used as the sampling capacitor and the transition capacitor, respectively.
In sampling and reset mode, the input signal is sampled at the capacitor CS, while the input terminal and output terminal of inverter are shorted as shown in the 3.5(a).
Hence, the inverter forms a feed-back loop, that the both of the transistors (PMOS and NMOS of the inverter) are biased at the weak inversion region during the steady state can provide high DC-gain. The offset voltage between ground and inverter’s input terminal can be saved on the offset cancel capacitor CC.
In the transition mode, the input terminal of the inverter VX is changed to(VOFF− VI)as shown in the figure 3.5(b). When the input signal VI is greater than the com-mon mode voltage (VI > 0), the PMOS transistor is biased at the strong inversion region while the NMOS transistor is cut off. Oppositely, when the input signal VIis less than the common mode voltage ((VI< 0)), the NMOS transistor is biased at the strong inversion region while the PMOS transistor is cut off. As a result, the nega-tive feedback is formed, the charge on the sampling capacitor CSis transferred to the transition capacitor CF, and, the voltage of node VXis recovered to the offset voltage VOFF. When the charge transmission is completed, the both of the transistors (PMOS and NMOS) are operated at the weak inversion region again. Since, the transistor is operated at the strong inversion region during the transition mode for providing the high slew rate, the high slew rate can be realized with minimum static current.
Φ
R:
Sampling & ResetΦ
A:
AmplificationΦ
A:
Holdinverter
IN OUT
CS CC
CF
ΦA
ΦA ΦR
ΦR
ΦR
ΦA
IN
PMOS: weak inversion NMOS: weak inversion
The input signal is sampled at the capacitor Cs
Input and output of the inverter are shored to reset the offset cancel capacitor C!
OUT CS
VI
VI VOFF
VO
CC
CF
CF
ΦA ΦR
inverter
IN OUT
CS CC
CF
ΦA
ΦR
ΦR
ΦA
PMOS: strong inversion NMOS: cut off
OUT CS
-VI
-VI
VOFF
VOFF VI
VOFF VI
VO
VX
VX
VG
VG
CC
VI<0 VI>0
PMOS: cut off
NMOS: strong inversion
OUT CS
VI
VOFF
VO
CC
ΦA ΦR
inverter
IN OUT
CS CC
CF
ΦA
ΦR
ΦR
ΦA
PMOS: weak inversion NMOS: weak inversion
CF
OUT VOFF
VO
CC
(a)
(b)
(c)
FIGURE 3.5: Operation of integrator using dynamic amplifier con-sist of inverter. (a) Sampling mode & Reset mode. (b) Amplification
mode. (c) Hold mode.
3.3. Implementation 43
Through Rate of Ring Amplifier
Since the output current of ring amplifier is not limited by the bias current, the set-ting time is decided by the output resistor of ring amplifier Routand the load capac-itance CL, it can be calculated by
τsetting_time =nRoutCL, (3.1)
where, n is a constant associated with the SNR requirement on the actual circuit.
Performance of Ring Amplifier
According to SPICE simulation results [3], the DC gain of ring amplifier reached to 84 dB with 74◦ phase margin with a 1.1 V supply voltage while the ring amplifier is biased at Vdd/2.
Ring Amplifier Cascode OTA
Track Hold Circuit using Amplifier +
- +
-AMP Φ2 CF Φ2d
Φ2 CF Φ2d
Vout,p
Vin,p
Vout,n
Φ1d
Φ2d
Vcm
Φ1
CS
CS=CF
Φ2
Vcm
Φ2d CS Φ1
Φ2
Φ1d
Φ1d
Φ1d
Vcm Vcm
Vin,n
Φ1 : Sampling Phase Φ2 : Transfer Phase Load of Integrator
Φ1d
Φ2d
Vcm
Vcm
Vcm
Φ1
CS2
Φ2
Vcm
Φ2d CS2 Φ1
Φ2
Φ1d
Vcm Vcm
VDD
VIN
VIP
VOP
VON
Core
CMFB
CC
VIN
ΦRd ΦAd ΦAd
ΦAd ΦR
ΦRd ΦRd
ΦRd
VCM
ΦAd ΦRd
CLA CLA
CC ΦAd
ΦRd ΦAd
VCM
VIP Core
VOP
VON
ΦR
ΦR
FIGURE3.6: Track hold circuit using ring amplifier.
-140 -120 -100 -80 -60 -40 -20 0 Input level [dBFS]
-20 0 20 40 60 80 100 120 140
SNDR [dB]
SNDR vs. Input level
SNDR of R-AMP SNDR of OTA
-140 -120 -100 -80 -60 -40 -20 0
Input level [dBFS]
0 20 40 60 80 100 120 140 160
SFDR [dB]
SFDR vs. Input level
SFDR of R-AMP SFDR of OTA
(a)
(b)
FIGURE3.7: SNDR & SFDR versus Input level of T/H circuit using ring amplifier and OTA.
3.3. Implementation 45 The track hold circuit shown in the figure 3.6 is proposed for conforming the perfor-mance of ring amplifier and comparing with the cascode OTA. In this T/H circuit, capacitor and switch are ideal analog components, only the ring amplifier and the cascode OTA are transistor level circuits, thus the performance of integrator is de-cided by amplifier circuits. Performing a transient simulation on the T/H circuit, we can get the PSD of output signal of the integrator. The performances of the ring amplifier and the cascode OTA can be conformed by calculating the SNDR, SFDR and THD of the output signal of the integrator using ring amplifier.
-140 -120 -100 -80 -60 -40 -20 0
Input level [dBFS]
-160 -140 -120 -100 -80 -60 -40 -20 0
THD [dB]
THD vs. Input level
THD of R-AMP THD of OTA
FIGURE3.8: THD versus Input level of T/H circuit using ring ampli-fier and OTA.
Figure 3.7 shows the SNDR & SFDR versus input signal level of the T/H circuit using the ring amplifier and the cascode OTA, respectively, the SNDR and SFDR of the T/H using the ring amplifier are higher than that of the T/H using the cascode OTA. Figure 3.8 shows the THD versus input signal level of the T/H circuit using the ring amplifier and the cascode OTA, respectively. That the ring amplifier has lower THD than the cascode OTA means the linearity of the ring amplifier is better than the cascode OTA. As a result, the ring amplifier has the better performance than the cascode OTA at the same input level.
3.3.2 SAR Quantizer with Passive Adder