RSA
暗号用の高速乗算器を設計するにあたり、第2
章、第3
章で示した乗算 器がどの程度の性能を持つかを調べるために比較・検討を行った。比較対象の乗算器は
・
Wallace tree, CLA
を用いた乗算器（図4.1(a)
）・
2
次Booth, Wallace tree, BLCA
を用いた乗算器（図4.1(b)
）・ 冗長二進加算器を用いた乗算器（図
4.1(c)
）の三種類で、各
6,8,16
ビットの回路とした。それぞれの回路のブロック図を図4.1
に示す。部分積生成(AND回路)
桁上げ信号吸収(CLA)
部分積生成(2次Booth)
桁上げ信号吸収(BLCA)
部分積加算、桁上げ信号吸収
（冗長二進加算器）
部分積加算（Wallace tree）
部分積生成(AND回路)
部分積加算（Wallace tree）
(a) (b) (c)
図4.1
比較対象となる乗算器のブロック図比較項目は演算時間とゲート数である。比較の対象となる回路は
VHDL
で設 計し(
各6
ビット乗算器のVHDL
ソースコードは付録を参照)
、Synopsys
社のdesign analyzer
を使用して論理合成、最適化を行い、それぞれの回路に対する 演算時間、ゲート数のデータを出力した。なお、library
にはrohm035_h
を用 いた。論理合成した回路として、
6
ビットのものと8
ビットのものを図4.2(a),(b),(c)
に示す。回路図中の太線がクリティカルパスを示している。図
4.2(a)
6
ビット乗算器図
4.2(a)
8
ビット乗算器図
4.2(b)
6
ビット乗算器図
4.2(b)
8
ビット乗算器図
4.2(c)
6
ビット乗算器図
4.2(c)
8
ビット乗算器各乗算器の演算時間、ゲート数の算出結果を表
4.1
に示す。表
4.1
各回路のゲート数、演算時間の算出結果Bit Circuit The number of Gate
[gate]
Data arrival time [ns]
(a) 169 6.36
(b) 126 5.55
6
(c) 661 6.23
(a) 377 9.04
(b) 240 7.23
8
(c) 1215 6.38
(a) 1612 14.48 (b) 1087 11.54 16
(c) 5123 8.61
表
4.1
中のCircuit(a),(b),(c)
は図4.1
で示したようにそれぞれ、Wallace tree, CLA
を用いた乗算器、2
次Booth, Wallace tree, BLCA
を用いた乗算器、冗長 二進加算器を用いた乗算器である。表
4.1
から分かるように、演算時間の最も短い乗算器は冗長二進加算器を用い た乗算器である。しかし、通常の乗算器と違い各ビットが倍の長さを持つため、ゲート数は大幅に増加する。表
4.1
の演算時間をグラフで表したものが図4.3
、 ゲート数をグラフで表したものが図4.4
である。0 1000 2000 3000 4000 5000 6000
bit数 (bit)
The number of Gate (gate)
(a) (b) (c)
16bit 8bit
6bit
図
4.3
各乗算器の演算時間0 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
bit
数(bit)
Data arrival time (ns)
(a) (b) (c)
8bit 16bit
6bit
図
4.4
各乗算器のゲート数図
4.3
より、2
次Booth, Wallace tree, BLCA
を用いた乗算器と冗長二進加算 器を用いた乗算器の比較では8
ビット、16
ビットそれぞれの回路で冗長二進加 算器を用いた乗算器のほうが高速であるが、ビット数が増えた場合の演算時間 の増加率は冗長二進加算器を用いた乗算器のほうが小さい。よって、多ビット の入力の場合、高速性を求めるのであれば冗長二進加算器を用いた乗算器の回 路が有効であるといえる。第 5 章 おわりに
著者が提案した冗長二進加算器を用いた乗算器は、従来の
FA
を用いた乗算器 より高速であり、入力ビット数増加による演算時間の増加率が小さい回路であ るという結果が得られた。また、冗長二進加算器を用いた乗算器の部分積生成 回路であるAND
回路にBooth
デコーダを適用することで更なる高速化が期待 できる。しかし、冗長二進数を用いた乗算器では、
FA
を用いた乗算器と比べて入力ビ ット数が二倍になるため、回路規模は三倍程度増加したものとなった。そのた め、消費電力も増加する。これは、従来手法のFA
に相当する、冗長二進加算器 の回路規模がFA
と比べて大きくなったことが原因である。このため、高速性を 維持しながら回路規模の縮小、消費電力の低減をはかることが今後の課題であ る。謝辞
本研究を行うに際し、懇切丁寧な御指導を御鞭撻賜りました高知工科大学大 学院工学研究科基盤工学専攻電子・光システム工学コース矢野政顕教授に心か ら感謝いたします。また、同研究室の原央教授、橘昌良助教授、ほか矢野研究 室の皆様に心から感謝し、お礼申し上げます。
参考文献
路 ，培風館，
pp.155
‐171
，Octover1996.
[3]
有山一弘， 冗長2
進表現を用いた剰余数システムに関する研究 ，
http://www-tysm.ee.kanagawa-u.ac.jp/~toyo/data/master/1996Ariyama.pdf
，pp.14
‐25
，1996.
[4]
松村暢也，矢野政顕，RSA
暗号に使用されている乗算剰余演算器の高速化 ， 電気関係学会四国支部連合大会，p.189
，2003.
[1]
梶原裕輝，永田真，瀧和男，RSA
用高速べき乗剰余演算器の設計 ， 信学技報，Vol.102
，No.476
，pp.157
‐162
，November 2002.
[2]
榎本忠儀， 入門から実用までCMOS
集積回付録
6
ビット×6
ビットの各乗算器のVHDL
ソースコードを付録として示す。な．
Wallace tree, CLA
を用いた6
ビット乗算器のVHDL
ソースコードse IEEE.std_logic_1164.all;
us
ntity multiplier66_FA is
port (X : in std_logic_vector(5 downto 0);
Y : in std_logic_vector(
zero : in std_logic;
Z : out std_logic_vector(11 downto 0));
end multiplier66_FA;
architecture rtl of multiplier66_FA is
component FA
port (A : in std_logic;
B : in std_logic;
C : in std_logic;
S : out std_logic;
C_out : out std_logic);
end component;
component CLA_4
port (A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
C : in std_logic;
S : out std_logic_vector(3 downto 0);
C_out : out std_logic);
お、以下に示す
VHDL
ソースコードは最上位の階層のものである。1
---
library IEEE;
u
use IEEE.std_logic_arith.all;
e IEEE.std_logic_unsigned.all;
e
5 downto 0);
end component;
mponent HA
S : out std_logic;
4, X0Y5, X1Y0, X1Y1, X1Y2, X1Y3, X1Y4, X1Y5, X2Y0, 4, X2Y5, X3Y0, X3Y1, X3Y2, X3Y3, X3Y4, X3Y5, X4Y0, 4Y5, X5Y0, X5Y1, X5Y2, X5Y3, X5Y4, X5Y5, C00, C01, C02, C03, C04, C05, C06, C07, C08, C09, C10, C11, C12, C13, C14, C15, C16,
C21, C22, C23, C24, C25, S00, S01, S02, S03, S04, S05, S06, , S16, S17, S18, S19, S20, S21
: s
gnal A, B : std_logic_vector(7 downto 0);
egin
(0) <= X(0) and Y(0);
nd Y(0);
Y(1);
2Y1 <= X(2) and Y(1);
(1);
co
port (A : in std_logic;
B : in std_logic;
C : out std_logic);
end component;
signal X0Y1, X0Y2, X0Y3, X0Y X2Y1, X2Y2, X2Y3, X2Y X4Y1, X4Y2, X4Y3, X4Y4, X
C17, C18, C19, C20,
S07, S08, S09, S10, S11, S12, S13, S14, S15 td_logic;
si
signal CC : std_logic;
b
Z
X1Y0 <= X(1) a
X2Y0 <= X(2) and Y(0);
X3Y0 <= X(3) and Y(0);
X4Y0 <= X(4) and Y(0);
X5Y0 <= X(5) and Y(0);
X0Y1 <= X(0) and Y(1);
X1Y1 <= X(1) and X
X3Y1 <= X(3) and Y X4Y1 <= X(4) and Y(1);
X5Y1 <= X(5) and Y(1);
X0Y2 <= X(0) and Y(2);
X1Y2 <= X(1) and Y(2);
X2Y2 <= X(2) and Y(2);
X3Y2 <= X(3) and Y(2);
4Y2 <= X(4) and Y(2);
d Y(2);
Y(3);
5Y3 <= X(5) and Y(3);
; 3Y5 <= X(3) and Y(5);
= X(4) and Y(5);
5Y5 <= X(5) and Y(5);
X0Y1, X1Y0, Z(1), C00);
, X1Y1, X2Y0, S00, C01);
, X2Y1, X3Y0, S01, C02);
, X3Y1, X4Y0, S02, C03);
, X4Y1, X5Y0, S03, C04);
, X5Y1, zero, S04, C05);
X0Y4, X1Y3, S05, C06);
, X1Y4, X2Y3, S06, C07);
, X2Y4, X3Y3, S07, C08);
, X3Y4, X4Y3, S08, C09);
, X4Y4, X5Y3, S09, C10);
, X5Y4, zero, S10, C11);
S00, C00, Z(2), C12);
, S01, C01, S11, C13);
X
X5Y2 <= X(5) an
X0Y3 <= X(0) and Y(3);
X1Y3 <= X(1) and Y(3);
X2Y3 <= X(2) and Y(3);
X3Y3 <= X(3) and Y(3);
X4Y3 <= X(4) and X
X0Y4 <= X(0) and Y(4);
X1Y4 <= X(1) and Y(4);
X2Y4 <= X(2) and Y(4);
X3Y4 <= X(3) and Y(4);
X4Y4 <= X(4) and Y(4);
X5Y4 <= X(5) and Y(4);
X0Y5 <= X(0) and Y(5);
X1Y5 <= X(1) and Y(5);
X2Y5 <= X(2) and Y(5) X
X4Y5 <
X
U00 : FA port map(zero, U01 : FA port map(X0Y2 U02 : FA port map(X1Y2 U03 : FA port map(X2Y2 U04 : FA port map(X3Y2 U05 : FA port map(X4Y2 U06 : FA port map(zero, U07 : FA port map(X0Y5 U08 : FA port map(X1Y5 U09 : FA port map(X2Y5 U10 : FA port map(X3Y5 U11 : FA port map(X4Y5 U12 : FA port map(zero, U13 : FA port map(X0Y3
U14 : FA port map(S05, S02, C02, S12, C14);
S03, C03, S13, C15);
S04, C04, S14, C16);
X5Y2, C05, S15, C17);
C06, zero, S16, C18);
C07, C15, S17, C19);
C08, C16, S18, C20);
C09, C17, S19, C21);
C10, zero, S20, C22);
, C11, zero, S21, C23);
8&S17&S16&S12&S11;
19&C18&C14&C13&C12;
wnto 0), B(3 downto 0), zero, Z(6 downto 3), C24);
wnto 4), B(7 downto 4), C24, Z(10 downto 7), C25);
Z(11), CC);
nd rtl;
--- 6
ビット乗算器の---
to 0);
wnto 0);
U15 : FA port map(S06, U16 : FA port map(S07, U17 : FA port map(S08, U18 : FA port map(S13, U19 : FA port map(S14, U20 : FA port map(S15, U21 : FA port map(S09, U22 : FA port map(S10, U23 : FA port map(X5Y5
A <= S21&S20&S19&S1 B <= C22&C21&C20&C
U24 :
CLA_4 port map(A(3 do U25 :
CLA_4 port map(A(7 do U26 :
HA port map(C25, C23,
e
---2
．2
次Booth, Wallace tree, BLCA
を用いたVHDL
ソースコード---library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier66_2 is
Port ( X : in std_logic_vector(7 down Y : in std_logic_vector(7 do
one : in std_logic;
zero : in std_logic;
Z : out std_logic_vector(14 downto 0));
ownto 0);
nto 0);
Y_minus : in std_logic;
to 0);
o 0);
A2 : out std_logic_vector(5 downto 0);
A_bar_g0 : out std_logic;
A_bar_g2 : out std_logic;
C1 : out std_logic;
nd component;
Port ( A0 : in std_logic_vector(5 downto 0);
td_logic_vector(5 downto 0);
ar1 : in std_logic;
C2 : in std_logic;
std_logic;
ector(9 downto 0);
end multiplier66_2;
architecture Behavioral of multiplier66_2 is
component Booth_six is
Port ( X : in std_logic_vector(5 d X_minus : in std_logic;
Y : in std_logic_vector(5 dow
A0 : out std_logic_vector(5 down A1 : out std_logic_vector(5 downt
A_bar_g1 : out std_logic;
C0 : out std_logic;
C2 : out std_logic);
e
component Wallace_tree_six is
A1 : in std_logic_vector(5 downto 0);
A2 : in s
A_bar0 : in std_logic;
A_b
A_bar2 : in std_logic;
C0 : in std_logic;
C1 : in std_logic;
one : in
zero : in std_logic;
S : out std_logic_vector(10 downto 0);
C_out : out std_logic_v
C_minus : out std_logic);
omponent BLCA_six is
);
B : in std_logic_vector(10 downto 0);
: in std_logic;
ic;
ic;
downto 0));
gnal A downto 0);
_logic_vector(10 downto 0);
ignal C_out : std_logic_vector(9 downto 0);
nto 0), zero, A0(5 downto 0), A1(5 downto 0), _bar_g1, A_bar_g2, C0, C1, C2);
map
0), A2(5 downto 0), A_bar_g0, A_bar_g1, A_bar_g2,
s;
, zero, zero, one, one, zero, one, end component;
c
Port ( A : in std_logic_vector(10 downto 0
g_minus1
q_minus1 : in std_logic;
g_minus_bar1 : in std_log q_minus_bar1 : in std_logic;
g_minus2 : in std_log q_minus2 : in std_logic;
g_minus_bar2 : in std_logic;
q_minus_bar2 : in std_logic;
C_minus : in std_logic;
S : out std_logic_vector(10 end component;
si 0, A1, A2 : std_logic_vector(5
signal A_bar_g0, A_bar_g1, A_bar_g2, C0, C1, C2, C_minus : std_logic;
signal S, CC : std s
begin
compBooth : Booth_six port map (X(5 downto 0), zero, Y(5 dow A2(5 downto 0), A_bar_g0, A compWallace : Wallace_tree_six port (A0(5 downto 0), A1(5 downto
C0, C1, C2, one, zero, S(10 downto 0), C_out(9 downto 0), C_minus);
CC <= C_out(9 downto 0) & C_minu compBLCA : BLCA_six port map
(S(10 downto 0), CC(10 downto 0), zero, one, one
Z(10 downto 0));
end Behavioral;
---
のVHDL
ソースコード---
o 0);
(11 downto 0);
std_logic_vector(23 downto 0));
nd multiplier66_RB;
Port ( A : in std_logic_vector(1 downto 0);
B : in std_logic_vector(1 downto 0);
A_minus : in std_logic;
o 0));
ignal X0Y1, X0Y2, X0Y3, X0Y4, X0Y5, X1Y0, X1Y1, X1Y2, X1Y3, X1Y4, X1Y5, X2Y0, , X3Y0, X3Y1, X3Y2, X3Y3, X3Y4, X3Y5, X4Y0, X4Y1, X4Y2, X4Y3, X4Y4, X4Y5, X5Y0, X5Y1, X5Y2, X5Y3, X5Y4, X5Y5, C00,
6, C07, C08, C09, C10, C11, C12, C13, C14, C15, C16,
---3
．冗長二進加算器を用いた6
ビット乗算器---library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplier66_RB is
Port ( X : in std_logic_vector(11 downt
Y : in std_logic_vector
zero : in std_logic;
Z : out e
architecture rtl of multiplier66_RB is component RBcell
B_minus : in std_logic;
C_minus : in std_logic_vector(1 downto 0);
S : out std_logic_vector(1 downto 0);
C : out std_logic_vector(1 downt end component;
s
X2Y1, X2Y2, X2Y3, X2Y4, X2Y5 C01, C02, C03, C04, C05, C0
C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31,
C32, C33, S00, S01, S02, S03, S04, S05, S06, S07, S08, S09, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, zz : std_logic_vector(1 downto 0);
3) nand Y(1)) nand (X(2) nand Y(0));
d (X(2) nand Y(1));
(X(4) nand Y(0));
nand Y(1));
3Y0(0) <= (X(7) nand Y(1)) nand (X(6) nand Y(0));
0)) nand (X(6) nand Y(1));
nd Y(0));
nand (X(10) nand Y(0));
Y(1));
d Y(3)) nand (X(0) nand Y(2));
0Y1(1) <= (X(1) nand Y(2)) nand (X(0) nand Y(3));
(X(2) nand Y(2));
1Y1(1) <= (X(3) nand Y(2)) nand (X(2) nand Y(3));
nand Y(3)) nand (X(4) nand Y(2));
and Y(3));
nd Y(2));
nd (X(6) nand Y(3));
nd (X(8) nand Y(2));
));
d Y(2));
Y(3));
nand Y(5)) nand (X(0) nand Y(4));
0Y2(1) <= (X(1) nand Y(4)) nand (X(0) nand Y(5));
begin
Z(0) <= (X(1) nand Y(1)) nand (X(0) nand Y(0));
Z(1) <= (X(1) nand Y(0)) nand (X(0) nand Y(1));
X1Y0(0) <= (X(
X1Y0(1) <= (X(3) nand Y(0)) nan X2Y0(0) <= (X(5) nand Y(1)) nand X2Y0(1) <= (X(5) nand Y(0)) nand (X(4) X
X3Y0(1) <= (X(7) nand Y(
X4Y0(0) <= (X(9) nand Y(1)) nand (X(8) na
X4Y0(1) <= (X(9) nand Y(0)) nand (X(8) nand Y(1));
X5Y0(0) <= (X(11) nand Y(1))
X5Y0(1) <= (X(11) nand Y(0)) nand (X(10) nand X0Y1(0) <= (X(1) nan
X
X1Y1(0) <= (X(3) nand Y(3)) nand X
X2Y1(0) <= (X(5)
X2Y1(1) <= (X(5) nand Y(2)) nand (X(4) n X3Y1(0) <= (X(7) nand Y(3)) nand (X(6) na X3Y1(1) <= (X(7) nand Y(2)) na
X4Y1(0) <= (X(9) nand Y(3)) na
X4Y1(1) <= (X(9) nand Y(2)) nand (X(8) nand Y(3 X5Y1(0) <= (X(11) nand Y(3)) nand (X(10) nan X5Y1(1) <= (X(11) nand Y(2)) nand (X(10) nand X0Y2(0) <= (X(1)
X
X1Y2(0) <= (X(3) nand Y(5)) nand (X(2) nand Y(4));
X1Y2(1) <= (X(3) nand Y(4)) nand (X(2) nand Y(5));
X2Y2(0) <= (X(5) nand Y(5)) nand (X(4) nand Y(4));
X2Y2(1) <= (X(5) nand Y(4)) nand (X(4) nand Y(5));
X3Y2(0) <= (X(7) nand Y(5)) nand (X(6) nand Y(4));
X3Y2(1) <= (X(7) nand Y(4)) nand (X(6) nand Y(5));
X4Y2(0) <= (X(9) nand Y(5)) nand (X(8) nand Y(4));
X4Y2(1) <= (X(9) nand Y(4)) nand (X(8) nand Y(5));
) <= (X(11) nand Y(5)) nand (X(10) nand Y(4));
5Y2(1) <= (X(11) nand Y(4)) nand (X(10) nand Y(5));
X5Y2(0 X
X0Y3(0) <= (X(1) nand Y(7)) nand (X(0) nand Y(6));
X0Y3(1) <= (X(1) nand Y(6)) nand (X(0) nand Y(7));
X1Y3(0) <= (X(3) nand Y(7)) nand (X(2) nand Y(6));
X1Y3(1) <= (X(3) nand Y(6)) nand (X(2) nand Y(7));
X2Y3(0) <= (X(5) nand Y(7)) nand (X(4) nand Y(6));
X2Y3(1) <= (X(5) nand Y(6)) nand (X(4) nand Y(7));
X3Y3(0) <= (X(7) nand Y(7)) nand (X(6) nand Y(6));
X3Y3(1) <= (X(7) nand Y(6)) nand (X(6) nand Y(7));
X4Y3(0) <= (X(9) nand Y(7)) nand (X(8) nand Y(6));
X4Y3(1) <= (X(9) nand Y(6)) nand (X(8) nand Y(7));
X5Y3(0) <= (X(11) nand Y(7)) nand (X(10) nand Y(6));
X5Y3(1) <= (X(11) nand Y(6)) nand (X(10) nand Y(7));
X0Y4(0) <= (X(1) nand Y(9)) nand (X(0) nand Y(8));
X0Y4(1) <= (X(1) nand Y(8)) nand (X(0) nand Y(9));
X1Y4(0) <= (X(3) nand Y(9)) nand (X(2) nand Y(8));
X1Y4(1) <= (X(3) nand Y(8)) nand (X(2) nand Y(9));
X2Y4(0) <= (X(5) nand Y(9)) nand (X(4) nand Y(8));
X2Y4(1) <= (X(5) nand Y(8)) nand (X(4) nand Y(9));
X3Y4(0) <= (X(7) nand Y(9)) nand (X(6) nand Y(8));
X3Y4(1) <= (X(7) nand Y(8)) nand (X(6) nand Y(9));
X4Y4(0) <= (X(9) nand Y(9)) nand (X(8) nand Y(8));
X4Y4(1) <= (X(9) nand Y(8)) nand (X(8) nand Y(9));
X5Y4(0) <= (X(11) nand Y(9)) nand (X(10) nand Y(8));
X5Y4(1) <= (X(11) nand Y(8)) nand (X(10) nand Y(9));
X0Y5(0) <= (X(1) nand Y(11)) nand (X(0) nand Y(10));
X0Y5(1) <= (X(1) nand Y(10)) nand (X(0) nand Y(11));
X1Y5(0) <= (X(3) nand Y(11)) nand (X(2) nand Y(10));
X1Y5(1) <= (X(3) nand Y(10)) nand (X(2) nand Y(11));
X2Y5(0) <= (X(5) nand Y(11)) nand (X(4) nand Y(10));
X2Y5(1) <= (X(5) nand Y(10)) nand (X(4) nand Y(11));
X3Y5(0) <= (X(7) nand Y(11)) nand (X(6) nand Y(10));
X3Y5(1) <= (X(7) nand Y(10)) nand (X(6) nand Y(11));
X4Y5(0) <= (X(9) nand Y(11)) nand (X(8) nand Y(10));
X4Y5(1) <= (X(9) nand Y(10)) nand (X(8) nand Y(11));
X5Y5(0) <= (X(11) nand Y(11)) nand (X(10) nand Y(10));
ownto 2), C00);
C00, S00, C01);
C01, S01, C02);
C02, S02, C03);
C03, S03, C04);
, S04, C05);
C06);
, C06, S06, C07);
, C07, S07, C08);
C08, S08, C09);
C09, S09, C10);
, S10, C11);
wnto 4), C12);
Z(7 downto 6), C13);
11, C14);
12, C15);
13, C16);
14, C17);
, C18);
, C19);
, C20);
20, S18, C21);
21, S19, C22);
22, S20, C23);
23, S21, C24);
S22, C25);
nto 8), C26);
(11 downto 10), C27);
X5Y5(1) <= (X(11) nand Y(10)) nand (X(10) nand Y(11));
zz <= zero & zero;
comp00 : RBcell port map(X0Y1, X1Y0, zero, zero, zz, Z(3 d comp01 : RBcell port map(X1Y1, X2Y0, X0Y1(1), X1Y0(1), comp02 : RBcell port map(X2Y1, X3Y0, X1Y1(1), X2Y0(1), comp03 : RBcell port map(X3Y1, X4Y0, X2Y1(1), X3Y0(1), comp04 : RBcell port map(X4Y1, X5Y0, X3Y1(1), X4Y0(1), comp05 : RBcell port map(X5Y1, zz, X4Y1(1), X5Y0(1), C04 comp06 : RBcell port map(X0Y3, X1Y2, zero, zero, zz, S05, comp07 : RBcell port map(X1Y3, X2Y2, X0Y3(1), X1Y2(1) comp08 : RBcell port map(X2Y3, X3Y2, X1Y3(1), X2Y2(1) comp09 : RBcell port map(X3Y3, X4Y2, X2Y3(1), X3Y2(1), comp10 : RBcell port map(X4Y3, X5Y2, X3Y3(1), X4Y2(1), comp11 : RBcell port map(X5Y3, zz, X4Y3(1), X5Y2(1), C10 comp12 : RBcell port map(S00, X0Y2, zero, zero, zz, Z(5 do comp13 : RBcell port map(S01, S05, S00(1), X0Y2(1), C12, comp14 : RBcell port map(S02, S06, S01(1), S05(1), C13, S comp15 : RBcell port map(S03, S07, S02(1), S06(1), C14, S comp16 : RBcell port map(S04, S08, S03(1), S07(1), C15, S comp17 : RBcell port map(C05, S09, S04(1), S08(1), C16, S comp18 : RBcell port map(zz, S10, C05(1), S09(1), C17, S15 comp19 : RBcell port map(zz, C11, zero, S10(1), C18, S16 comp20 : RBcell port map(X0Y5, X1Y4, zero, zero, zz, S17 comp21 : RBcell port map(X1Y5, X2Y4, X0Y5(1), X1Y4(1), C comp22 : RBcell port map(X2Y5, X3Y4, X1Y5(1), X2Y4(1), C comp23 : RBcell port map(X3Y5, X4Y4, X2Y5(1), X3Y4(1), C comp24 : RBcell port map(X4Y5, X5Y4, X3Y5(1), X4Y4(1), C comp25 : RBcell port map(X5Y5, zz, X4Y5(1), X5Y4(1), C24, comp26 : RBcell port map(S11, X0Y4, zero, zero, zz, Z(9 dow comp27 : RBcell port map(S12, S17, S11(1), X0Y4(1), C26, Z