ᚑ᮶ࡢ CMOS ㄽ⌮࢖ࣥࣂ࣮ࢱࡢ SPICE ࢩ࣑࣮ࣗࣞࢩࣙࣥ࠿ࡽᚓࡓᾘ

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

^-1

10

frequency [Hz]

e n er gy [fJ /c

CMOS-0.5V-simulation CMOS-0.5V-dynamic CMOS-0.5V-static

CMOS-0.5V-approximation CMOS-1.8V-simulation

CMOS-1.8V-dynamic CMOS-1.8V-static

CMOS-1.8V-approximation

72 6.3. ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

6.3 ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

ᚑ᮶ࡢ᩿⇕ⓗㄽ⌮ᅇ㊰ࡣ㸪㟼ⓗCMOSㄽ⌮࡜ྠᵝ࡟㸪RC➼౯ᅇ㊰ࢆ⏝࠸࡚ືⓗ

࢚ࢿࣝࢠ࣮ࡀồࡵࡽࢀ࡚࠸ࡿ㸬ࡲࡓ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ㸪ᚑ᮶ࡢCMOSㄽ⌮࡜ྠᵝ࡜

ࡉࢀ࡚࠸ࡿ㸬ࡇࡇ࡛ࡣ㸪᩿⇕ⓗㄽ⌮ᅇ㊰ࡢືⓗ࢚ࢿࣝࢠ࣮ࡢᑟฟ㐣⛬ࢆ♧ࡋ㸪ᾘ㈝

࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࡜SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥ࠿ࡽᚓࡓᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑ࢆ

♧ࡍ㸬

6.3.1 ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢືⓗ࢚ࢿࣝࢠ࣮ࡢᑟฟ

඘㟁ືస᫬ࡢCMOS࢖ࣥࣂ࣮ࢱࡢRC➼౯ᅇ㊰ࢆᅗ6.8(a)࡟♧ࡍ㸬ᅇ㊰ࢆ᩿⇕ື

సࡉࡏࡿࡓࡵࡢ㟁※࡜ࡋ࡚ࣛࣥࣉἼࢆ⪃࠼ࡿ㸬ࣛࣥࣉἼ㟁※VP CࡢἼᙧࢆᅗ6.8(b)

࡟♧ࡍ㸬

㼢^㼜㼏㻔㼠㻕 㻾^㻼

㻾^㻺

㻯^㻸 㼢^㼥㻔㼠㻕 㻵^㼜㼏㻔㼠㻕

㼢^㼜㼏㻔㼠㻕 㻴㼕㼓㼔䊻㻸㼛㼣

t vpc(t)

V^DD

τ

(a) (b)

ᅗ 6.8: (a)඘㟁ືస᫬ࡢ࢖ࣥࣂ࣮ࢱࡢRC➼౯ᅇ㊰ (b)㟁※VP CࡢἼᙧ.

㟁ᅽࡀ0V࠿ࡽVDDࡲ࡛ୖ᪼ࡍࡿ᫬㛫ࢆτ࡜ࡍࡿ㸬PMOSഃࡢࢫ࢖ࢵࢳࡀON࡜

࡞ࡾ㸪㟁※vP C(t)ࡀ᢬ᢠRP ࡜㈇Ⲵᐜ㔞CL࡜᥋⥆ࡉࢀࡿ㸬ࡇࡢ࡜ࡁࡢ㛵ಀᘧࡣ vP C(t) = RPiP C(t) +vy(t) (6.53)

vy(t) = 1 CL

_t

0−

iP C(τ)dτ (6.54)

࡜࡞ࡿ㸬ᘧ(6.53)㸪(6.54)ࡼࡾ

vP C(t) = RPiP C(t) + 1 CL

t 0−

iP C(τ)dτ (6.55)

Vy(s) =

sCLIP C(s) +

s . (6.57)

ึᮇ≧ែ࡛ࡣᐜ㔞CLࡣ඘㟁ࡉࢀ࡚࠸࡞࠸ࡓࡵ㸪vy(0) = 0࡛࠶ࡿ㸬ࡼࡗ࡚ᘧ(6.56)

ࡼࡾ

IP C(s) = 1 RP

sVP C(s) s+_C ¹

LRP

(6.58)

ࡲࡓ㸪ᘧ(6.57)㸪(6.58)ࡼࡾ

Vy(s) = 1 CLRP

VP C(s) s+ _C ¹

LRP

(6.59)

࡜࡞ࡿ㸬ᅗ6.8(b)࡟♧ࡋࡓࣛࣥࣉἼࡢᘧࡣ௨ୗࡢࡼ࠺࡟࡞ࡿ㸬 vP C(t) = VDD

τ {u(t)−u(t−τ)}+VDDu(t−τ) (6.60) ᘧ(6.60)ࢆࣛࣉࣛࢫኚ᥮ࡍࡿ࡜

VP C(s) = VDD

τ 1

s²(1−e^{−τ s}) (6.61)

࡛࠶ࡿ㸬ᘧ(6.61)ࢆᘧ(6.58)࡜ᘧ(6.59)࡟㸪ࡑࢀࡒࢀ௦ධࡍࡿ࡜

IP C(s) = VDD

τRP

(1−e^{−τ s}) s(s+_C ¹

LRP) (6.62)

Vy(s) = VDD

τCLRP

(1−e^{−τ s}) s²(s+ _C ¹

LRP). (6.63)

ᘧ(6.62)㸪(6.63)ࢆ㏫ࣛࣉࣛࢫኚ᥮ࡋ࡚, iP C(t) = CLVDD

τ

(1−e^−CLRPt )−(1−e^{−CLRPt−τ} )u(t−τ)

(6.64)

vy(t) = VDD

τ

t−CLRP(1−e^−CLRPt )

−

(t−τ)−CLRP(1−e^−CLRPt )

u(t−τ)

(6.65)

74 6.3. ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

㼢^㼜㼏㻔㼠㻕 㻾^㻼

㻾^㻺

㻯^㻸 㼢^㼥㻔㼠㻕 㻵^㼜㼏㻔㼠㻕

㼢^㼜㼏㻔㼠㻕 㻸㼛㼣䊻㻴㼕㼓㼔

t vpc(t)

VDD

τ

(a) (b)

ᅗ 6.9: (a)ᨺ㟁ືస᫬ࡢ࢖ࣥࣂ࣮ࢱࡢRC➼౯ᅇ㊰ (b)㟁※VP CࡢἼᙧ.

࡜࡞ࡿ㸬CL࡟඘㟁ࡉࢀࡿ࢚ࢿࣝࢠ࣮ࡣ, wc(t) =

t 0−

pc(τ)dτ+wc(0)

= t

0−

iP C(τ)vP C(τ)dτ (6.66)

࡜࡞ࡿ㸬ࡼࡗ࡚㸪඘㟁ືసࡀ᏶஢ࡋࡓ࡜ࡁ࡟㸪CL࡟⵳࠼ࡽࢀࡿ࢚ࢿࣝࢠ࣮ࡣ㸪 wc(∞) = 1

2CLVDD² . (6.67)

࡛࠶ࡿ㸬᢬ᢠRP ࡛ࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡣ㸪 wr(t) =

t

0 pr(τ)dτ+wr(0),

= t

0−

RPi²P C(τ)dτ (6.68)

࡛࠶ࡿ㸬ᘧ(6.68)ࡼࡾ㸪඘㟁ືసࡀ᏶஢ࡋࡓ࡜ࡁࡢRP ࡛ࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡣ wr(∞) = RPCL²VDD²

τ

1− CLRP

τ (1−e^−CLRPτ )

(6.69)

࡜࡞ࡿ㸬

ᨺ㟁ືస᫬ࡢCMOS࢖ࣥࣂ࣮ࢱࡢRC➼౯ᅇ㊰ࢆᅗ6.9(a)࡟♧ࡍ㸬ࡲࡓ㸪㟁ᅽ ࡀVDD࠿ࡽ0Vࡲ࡛᫬㛫τࢆ࠿ࡅ࡚ୗࡀࡿ㟁※VP CࡢἼᙧࢆᅗ6.9(b)࡟♧ࡍ㸬ࡇࡢ

࡜ࡁ㸪

vP C(t) = RNiP C(t) +vy(t), (6.70)

CL 0−

࡛࠶ࡿ㸬ᘧ(6.70)㸪(6.71)ࢆࡑࢀࡒࢀࣛࣉࣛࢫኚ᥮ࡍࡿ࡜

VP C(s) =RNIP C(s) + 1

sCLIP C(s) + vy(0₋)

s , (6.73)

Vy(s) = 1

sCLIP C(s) + vy(0₋)

s . (6.74)

඘㟁ືస࡟ࡼࡾᐜ㔞CLࡣ඘㟁ࡉࢀ࡚࠾ࡾ㸪vy(0₋) = VDD ࡛࠶ࡿ㸬ࡼࡗ࡚ᘧ(6.73)

ࡼࡾ

I_{P C}(s) = 1 RN

sVP C(s)−vy(0₋) s+_C ¹

LRN

(6.75)

࡛࠶ࡿ㸬ࡲࡓ㸪ᘧ(6.74)㸪(6.75)ࡼࡾ

Vy(s) = 1 CLRN

VP C(s) +CLRNvy(0) s+ _C ¹

LRN

(6.76)

࡛࠶ࡿ㸬ᅗ6.9(b)࡟♧ࡋࡓࣛࣥࣉἼࡢᘧࡣ௨ୗࡢࡼ࠺࡟࡞ࡿ㸬 vP C(t) =VDD

τ−t

τ {u(t)−u(t−τ)} (6.77) ᘧ(6.77)ࢆࣛࣉࣛࢫኚ᥮ࡍࡿ࡜

VP C(s) = VDD

1

s −1−e^{−τ s} τs²

(6.78)

࡛࠶ࡿ㸬ᘧ(6.78)ࢆᘧ(6.75)࡜ᘧ(6.76)࡟㸪ࡑࢀࡒࢀ௦ධࡍࡿ࡜

IP C(s) = −VDD

RN

1−e^{−τ s} s(s+_C ¹

LRN), (6.79)

Vy(s) = VDD

τCLRN

τCLRNs²+{τs−(1−e^{−τ s})} s²(s+_C ¹

LRN) . (6.80)

ᘧ(6.79)㸪(6.80)ࢆ㏫ࣛࣉࣛࢫኚ᥮ࡋ࡚, iP C(t) = CLVDD

τ

(1−e^−CLRNt )−(1−e^{−CLRNτ−t} )u(t−τ)

(6.81)

76 6.3. ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

vy(t) = VDDe^−CLRNt (6.82)

࡜࡞ࡿ㸬ᨺ㟁ືసࡀ᏶஢ࡋࡓ࡜ࡁ㸪CL࡟⵳࠼ࡽࢀࡿ࢚ࢿࣝࢠ࣮ࡣ㸪

wc(∞) = 0 (6.83)

࡛࠶ࡿ㸬ࡲࡓᨺ㟁ືసࡀ᏶஢ࡋࡓ࡜ࡁࡢ㸪RN ࡛ࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡣ wr(∞) = 2RNCL²VDD²

τ

1− CLRN

τ (1−e^−CLRNτ )

(6.84)

࡜࡞ࡿ㸬τ >> CLRP ࡜ࡍࡿ࡜㸪1>> CLRP/τ ࡜࡞ࡿࡢ࡛㸪 wr(∞) = 2RPCL²VDD²

τ (6.85)

࡜࡞ࡿ㸬

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

10

⁹

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

10

frequency [Hz]

e n er gy [fJ /c

proposed-1.8V-simulation proposed-1.8V-approximation approximation-dynamic

approximation-static proposed-0.5V-simulation

proposed-0.5V-approximation approximation-dynamic

approximation-static

ᅗ6.10: ᥦ᱌ࡋࡓ᩿⇕ⓗㄽ⌮࢖ࣥࣂ࣮ࢱࡢSPICEࢩ࣑࣮ࣗࣞࢩࣙࣥ࠿ࡽᚓࡓᾘ㈝࢚

ࢿࣝࢠ࣮࡜㸪ᘧ(6.8)ࢆ⏝࠸࡚ồࡵࡓᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑.

6.3.2 ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࡜ SPICE ࢩ࣑ࣗ

࣮ࣞࢩࣙࣥࡢẚ㍑

᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝࡣ㸪ືⓗ࢚ࢿࣝࢠ࣮ࡢᘧ(6.85)࡜㟼

ⓗ࢚ࢿࣝࢠ࣮ࡢᘧ(6.52)ࢆ㊊ࡋྜࢃࡏ࡚ᘧ(6.8)࡜࡞ࡿ㸬ᘧ(6.8)ࢆ⏝࠸࡚ồࡵࡓᾘ

㈝࢚ࢿࣝࢠ࣮࡜㸪SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥ࡟ࡼࡾồࡵࡓ㸪᩿⇕ⓗㄽ⌮࢖ࣥࣂ࣮ࢱࡢ ᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑ࢆᅗ6.10࡟♧ࡍ㸬1.8V࡛ືసࡋࡓ࡜ࡁࡢᾘ㈝࢚ࢿࣝࢠ࣮ࢆ

୕ゅࡢࣉࣟࢵࢺ㸪0.5V࡛ືసࡉࡏࡓ࡜ࡁࡢᾘ㈝࢚ࢿࣝࢠ࣮ࢆᅄゅࡢࣉࣟࢵࢺ࡛♧ࡋ ࡓ㸬᩿⇕ⓗㄽ⌮ᅇ㊰࡛ࡣ1.8Vືసࡢ࡜ࡁ㸪ⓑᢤࡁࡢࣉࣟࢵࢺ࡛♧ࡋࡓSPICEࢩ࣑ࣗ

࣮ࣞࢩࣙࣥࡢ⤖ᯝ࡜㸪㯮ࡢࣉࣟࢵࢺ࡛♧ࡋࡓᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࠿ࡽồࡵࡓ

⤖ᯝ࡟ᕪࡀฟ࡚࠸ࡿ㸬≉࡟㟼ⓗ࢚ࢿࣝࢠ࣮ࡢ⤖ᯝ࡟ᕪࡀฟ࡚ࡋࡲࡗ࡚࠸ࡿ㸬ࡲࡓ㸪ࢧ

ࣈࢫࣞࢵࢩࣙࣝࢻ㡿ᇦ࡛࠶ࡿ0.5Vືసࡢ࡜ࡁࡣ㸪ືⓗ࢚ࢿࣝࢠ࣮㸪㟼ⓗ࢚ࢿࣝࢠ࣮

࡜ࡶ࡟SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥࡢ⤖ᯝ࡜ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝࡢ⤖ᯝ࡟ᕪࡀฟ

78 6.3. ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

࡚ࡋࡲࡗ࡚࠸ࡿ㸬௨ୖ࡟ࡼࡾ㸪ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰᩿⇕ⓗㄽ⌮ᅇ㊰

࡛ࡣ㟼ⓗ࢚ࢿࣝࢠ࣮㸪ືⓗ࢚ࢿࣝࢠ࣮࡜ࡶ࡟㸪ᚑ᮶ࡢᩘ⌮ࣔࢹ࡛ࣝࡣSPICEࢩ࣑ࣗ

࣮ࣞࢩࣙࣥࡢᾘ㈝࢚ࢿࣝࢠ࣮≉ᛶࢆ⾲⌧࡛ࡁ࡞࠸ࡇ࡜ࡀゝ࠼ࡿ㸬

ࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮≉ᛶࢆ⾲⌧࡛ࡁࡿᩘ⌮ࣔࢹࣝࢆᥦ᱌ࡍࡿ㸬

6.4.1 ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢືⓗ࢚ࢿࣝࢠ࣮

ᅗ6.10࡟♧ࡋࡓࡼ࠺࡟㸪ࢧࣈࢫࣞࢵࢩࣙࣝࢻ㡿ᇦ࡛ືసࡍࡿ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢື

ⓗ࢚ࢿࣝࢠ࣮ࡣ㸪ᚑ᮶ࡢᩘ⌮ࣔࢹ࡛ࣝࡣṇࡋࡃ㏆ఝࡀ࡛ࡁ࡚࠸࡞࠿ࡗࡓ㸬ᚑ᮶ࡢᩘ⌮

ࣔࢹ࡛ࣝࡣ㸪࿘Ἴᩘࡀ10ಸ࡟࡞ࡿ࡜㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡶ10ಸࡢ್࡟࡞ࡿ㸬ᘧ(6.8) ࡢືⓗ࢚ࢿࣝࢠ࣮ࡢ㡯࡟࠾࠸࡚㸪ศẕ࡟࠶ࡿτ ࡣ㸪㟁※㟁ᅽࡀ0V࠿ࡽVDDࡲ࡛ୖ

᪼ࡍࡿࡢ࡟࠿࠿ࡿ᫬㛫࡛࠶ࡿࡓࡵ㸪࿘Ἴᩘ࡟ࡣ཯ẚ౛ࡍࡿ್࡛࠶ࡿ㸬ࡇࡢࡇ࡜࠿ࡽ

ࡶ࿘Ἴᩘࡀ10ಸ࡟࡞ࡿ࡜㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡀ10ಸ࡟࡞ࡿࡇ࡜ࡀศ࠿ࡿ㸬ࡋ࠿ࡋ㸪ᅗ 6.10࡟♧ࡋࡓࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢSPICEࢩ࣑࣮ࣗࣞࢩࣙࣥࡢ⤖ᯝ ࡣ㸪࿘Ἴᩘࡀ10ಸ࡟࡞ࡗࡓ᫬࡟㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡣ⣙3ಸࡢ್࡟࡞ࡗ࡚࠸ࡿ㸬ࡇࡢ ኚ໬㔞ࢆ⪃៖ࡍࡿ࡜㸪ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢືⓗ࢚ࢿࣝࢠ࣮ࡢᩘ⌮

ࣔࢹࣝࡣ௨ୗࡢࡼ࠺࡟࠶ࡽࢃࡍࡇ࡜ࡀ࡛ࡁࡿ㸬 wsub−adia−dyn = αξRC√

τCVDD² , (6.86)

ᘧ(6.86)ࢆ⏝࠸ࡿ࡜㸪࿘Ἴᩘࡀ10ಸ࡟࡞ࡗࡓ࡜ࡁ㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡀ⣙3ಸ࡜࡞ࡿ

ࡓࡵSPICEࢩ࣑࣮ࣗࣞࢩࣙࣥࡢ⤖ᯝ࡜୍⮴ࢆࡉࡏࡿࡇ࡜ࡀ࡛ࡁࡿ㸬

6.4.2 ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ㟼ⓗ࢚ࢿࣝࢠ࣮

ᅗ6.10ࡼࡾ㸪SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥࡢ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ㸪ᚑ ᮶ࡢᩘ⌮ࣔࢹࣝ࠿ࡽồࡵࡓ㟼ⓗ࢚ࢿࣝࢠ࣮ࡼࡾࡶᑠࡉࡃ࡞ࡿࡇ࡜ࡀศ࠿ࡿ㸬᩿⇕ⓗ

ㄽ⌮ᅇ㊰࡛ࡣ㸪࿘ᮇἼ㟁※ࢆ⏝࠸࡚࠸ࡿࡓࡵ㟁ᅽࡀ᫬㛫ⓗ࡟ኚ໬ࢆࡍࡿ㸬ᚑ᮶ࡢᾘ

㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹ࡛ࣝࡣࡑࡢᙳ㡪ࢆ⪃៖࡛ࡁ࡚࠸࡞࠸㸬᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ࿘ᮇ Ἴ㟁※ࡢἼᙧࡀ㸪㟼ⓗ࢚ࢿࣝࢠ࣮࡟୚࠼ࡿᙳ㡪ࢆ☜ㄆࡍࡿࡓࡵ㸪ᅗ6.11࡟♧ࡍ3ࡘ ࡢ㥑ືἼᙧࡢሙྜࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࢆࡑࢀࡒࢀồࡵࡿ㸬

㻹㻝 㻹㻞

㼂 㻴㼕㼓㼔 㻸㼛㼣

㼛㼚 㻹㻝 㼛㼒㼒

㻹㻞

㼂

㻸㼛㼣 㻴㼕㼓㼔

㼛㼚

㼛㼒㼒

(a) 0<t<2τ (b) 2τ<t<4τ

ᅗ 6.12: (a) 0 < t < 2τࡲ࡛ࡢ࢖ࣥࣂ࣮ࢱࡢ≧ែ. (b) 2τ < t <4τࡲ࡛ࡢ࢖ࣥࣂ࣮

ࢱࡢ≧ែ.

࡛࠶ࡿ㸬ᘧ(6.89)ࡼࡾ㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡣ wstatic−nmos(t) =

t

0 pstatic−nmos(τ)dτ (6.89)

࡛࠶ࡿ㸬᫬้2τࡲ࡛ࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡣ

wstatic−nmos(2τ) =τIoe^−nVTVth VDD (6.90)

࡜࡞ࡿ㸬

ḟ࡟㸪2τ < t <4τࡢ࡜ࡁ㸪PMOSࡀ࢜ࣇ㸪NMOSࡀ࢜ࣥ࡜࡞ࡿࡓࡵ㸪PMOS࡟ ὶࢀࡿ㟁ὶ࡟ࡼࡿᾘ㈝࢚ࢿࣝࢠ࣮ࡀ㸪㟼ⓗ࢚ࢿࣝࢠ࣮࡜࡞ࡿ㸬ࡇࡢ࡜ࡁࡢᾘ㈝㟁ຊ ࡣpstatic−pmos=IsubVdsp࡛࠶ࡿ㸬

VdspࡣVdsn࡜ྠᵝࡢኚ໬ࢆࡋ࡚࠸ࡿࡓࡵ㸪2τ < t <4τ ࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ0 <

t <2τ ࡢᾘ㈝࢚ࢿࣝࢠ࣮࡜ྠ➼࡟࡞ࡿ㸬ࡑࡢࡓࡵ㸪

wstatic−pmos(2τ) =τIoe^−nVTVth VDD (6.91) ᘧ(6.90)㸪(6.91)ࡼࡾ㸪ࢧ࢖ࣥἼ࢖ࣥࣂ࣮ࢱࡢ1࿘ᮇࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ

Wsin−static = 2τIoe^−nVTVthVDD (6.92)

82 6.4. ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

0 0.5 1 1.5

10^-13 10^-12 10^-11 10^-10 10^-9 10^-8 10^-7 10^-6 10^-5 10^-4

V_GS [V]

IDS [A]

ᅗ 6.13: Vdsnࢆኚ໬ࡉࡏࡓ࡜ࡁࡢ㸪NMOSࢺࣛࣥࢪࢫࢱࡢIds−Vgs≉ᛶ.

࡜࡞ࡿ㸬

0.5 0 1 1.5 V

PC

0 1 2 V

in

0 1 2 V

PCB

0.5 0 1 1.5 V

dsn

-1 0 1 V

gsp

0.5 0 1 1.5 V

dsp

0 1 2

V

gsn

2τ 4τ

ᅗ 6.14: ࢧ࢖ࣥἼ࢖ࣥࣂ࣮ࢱࡢືసἼᙧ.

84 6.4. ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

2PC2ALࡢሙྜ ᅗ6.15࡟2PC2AL࢖ࣥࣂ࣮ࢱࡢືసἼᙧࢆ♧ࡍ㸬ᅇ㊰ࡣࢧ࢖ࣥ

Ἴࡢ࡜ࡁ࡜ྠᵝ࡟ᅗ6.12࡛࠶ࡿ㸬0< t <2τࡢ࡜ࡁ㸪Vgsnࡀ0V௨ୗ࡞ࡢ࡛NMOS ࡀ࢜ࣇ≧ែ࡜࡞ࡗ࡚࠸ࡿ㸬ࡇࡢ࡜ࡁNMOSࡢࢯ࣮ࢫࢻࣞ࢖ࣥ㛫㟁ᅽVdsnࡣ㸪ฟຊ 㟁ᅽ࡜VP Cࡢᕪ࡟࡞ࡿ㸬

vout(t) = VDD

2 {u(t)−u(t−2τ)}+ VDD

2τ t{u(t)−u(t−τ)}̭

−VDD

2τ (t−2τ){u(t−τ)−u(t−2τ)} (6.93)

vP C(t) =−VDD

2τ (t−τ){u(t)−u(t−τ)} +VDD

2τ (t−τ){u(t−τ)−u(t−2τ)} (6.94)

࡞ࡢ࡛㸪

vdsn = VDD

τ t−2VDD

τ (t−τ)u(t−τ) + VDD

τ (t−2τ)u(t−2τ) (6.95)

࡜࡞ࡿ㸬ࡇࢀࡣᘧ(6.87)࡟♧ࡋࡓ㸪ࢧ࢖ࣥἼືస࢖ࣥࣂ࣮ࢱࡢࢯ࣮ࢫࢻࣞ࢖ࣥ㛫㟁 ᅽ࡜ྠࡌ࡛࠶ࡿ㸬ࡼࡗ࡚2PC2AL࢖ࣥࣂ࣮ࢱࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ㸪ࢧ࢖ࣥἼືస࢖

ࣥࣂ࣮ࢱ࡜ྠ➼࡛࠶ࡿ࡜࠸࠼ࡿࡓࡵ㸪2PC2AL࢖ࣥࣂ࣮ࢱࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ W₂P C2AL−static = 2τIoe^−nVTVth VDD (6.96)

࡜࡞ࡿ㸬

0.5 0 1 1.5 V

PC

0 1 2 V

in

0 1 2 V

PCB

0.5 0 1 1.5 V

dsn

0 V

gsp

1

0.5 0 1 1.5 V

dsp

0 V

gsn

1

2τ 4τ

ᅗ 6.15: 2PC2AL࢖ࣥࣂ࣮ࢱࡢືసἼᙧ.

86 6.4. ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

ᥦ᱌᪉ἲࡢሙྜ ᅗ6.16࡟ᥦ᱌࢖ࣥࣂ࣮ࢱࡢືసἼᙧࢆ♧ࡍ㸬ᅇ㊰ࡣᅗ6.12࡛࠶

ࡿ㸬ᥦ᱌᪉ἲ࡛ࡣ㸪㟁※㟁ᅽVP C࡜VP Cࡢᘧࡣ vP C(t) = VDD

τ (t+ 1

2τ){u(t)−u(t−1 2τ)}

−VDD

τ (t−3

2τ){u(t− 1

2τ)−u(t− 3 2τ)} +VDD

τ (t− 3

2τ){u(t− 3

2τ)−u(t−2τ)} (6.97)

vP C(t) = −VDD

τ (t− 1

2τ){u(t)−u(t− 1 2τ)} +VDD

τ (t− 1

2τ){u(t− 1

2τ)−u(t−τ)}

−VDD

τ (t− 3

2τ){u(t−τ)−u(t− 3 2τ)} +VDD

τ (t− 3

2τ){u(t− 3

2τ)−u(t−2τ)} (6.98)

࡜⾲ࡏࡿ㸬

0< t <2τࡢ࡜ࡁ㸪NMOSࡢࢻࣞ࢖ࣥࢯ࣮ࢫ㛫㟁ᅽVdsn =vP C(t)−vP C(t)࡞ࡢ

࡛Vdsnࡣ௨ୗࡢᘧ࡛⾲ࡉࢀࡿ㸬 vdsn = 2VDD

τ tu(t)−4VDD

τ (t−1

2τ)u(t−1

2τ) + 2VDD

τ (t−τ)u(t−τ) (6.99) ࡇࡢ࡜ࡁࡢᾘ㈝㟁ຊࡣpnmos−static=Isubvdsn࡛࠶ࡾ㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡣwnmos−static = ₂τ

0 pnmos−static(τ)dτ࡜⾲ࡉࢀࡿࡢ࡛

wnmos−static = 1

2τIoe^−nVTVth VDD (6.100)

࡜࡞ࡿ㸬

2τ < t <4τࡢ༊㛫࡛ࡶ㸪࢜ࣇ≧ែࡢPMOS࡟ྠᵝࡢ㟁ὶ㸪㟁ᅽࡀຍࢃࡿࡓࡵྠ

㔞ࡢ࢚ࢿࣝࢠ࣮ࡀᾘ㈝ࡉࢀࡿ㸬ࡼࡗ࡚㸪0< t < 4τ ࡢ1࿘ᮇ࡛ᥦ᱌࢖ࣥࣂ࣮ࢱࡀᾘ

㈝ࡍࡿ㟼ⓗ࢚ࢿࣝࢠ࣮ࡣ

wprop−static =τIoe^−nVTVthVDD (6.101)

࡜࡞ࡿ㸬

0.5 0 1 1.5 V

PC

0 1 2 V

in

0 1 2 V

PCB

0 V

dsn

1

-1 0 1 V

gsp

0 V

dsp

1

0 V

gsn

1

2τ 4τ

ᅗ 6.16: ᥦ᱌࢖ࣥࣂ࣮ࢱࡢືసἼᙧ.

88 6.4. ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ

10

⁰

10

¹

10

²

10

³

10

⁴

10

⁵

10

^-4

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

²

10

³

proposed-0.5V-simulation

proposed-0.5V-NEW-approximation NEW-approximation-dynamic

NEW-approximation-static frequency [Hz]

en e rgy [fJ /c yc le ]

ᅗ 6.17: ᥦ᱌࢖ࣥࣂ࣮ࢱࡢ᪂ࡓ࡞ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࡜㸪SPICEࢩ࣑࣮ࣗࣞ

ࢩࣙࣥ࠿ࡽᚓࡓᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑.

6.4.3 ᥦ᱌ࡋࡓᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࡜ SPICE ࢩ࣑࣮ࣗࣞࢩࣙ

ࣥࡢẚ㍑

᪂ࡓ࡞㟼ⓗ࢚ࢿࣝࢠ࣮ࡢᘧ(6.101)࡜ືⓗ࢚ࢿࣝࢠ࣮ࡢᘧ(6.86)࠿ࡽ㸪ᥦ᱌ࡋࡓࢧ

ࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝࡣ௨ୗࡢࡼ࠺࡟࠶ࡽ

ࢃࡍࡇ࡜ࡀ࡛ࡁࡿ㸬

wsub−adia−rev = τVDDIsub+αξRC√

τCVDD² , (6.102)

ᘧ(6.102)ࢆ⏝࠸࡚ồࡵࡓᾘ㈝࢚ࢿࣝࢠ࣮࡜㸪SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥ࡟ࡼࡾᚓࡓ㸪

ᥦ᱌࢖ࣥࣂ࣮ࢱࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑ࢆᅗ6.17࡟♧ࡍ㸬ᚑ᮶ࡢ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࠿ࡽ㸪ືⓗ࢚ࢿࣝࢠ࣮ࡢ࿘Ἴᩘኚ໬࡟ࡼࡿഴࡁࡀᨵၿࡉ

7.1 ࡲ࡜ࡵ

࢚ࢿࣝࢠ࣮ࣁ࣮࣋ࢫࢸ࢕ࣥࢢᢏ⾡࡛ࡣ㸪ప㟁ᅽ࡛㥑ືࡀྍ⬟࡛࠶ࡿࡇ࡜㸪஺ὶ㟁

※࡛㥑ືࡀྍ⬟࡛࠶ࡿࡇ࡜㸪᭦࡟పᾘ㈝㟁ຊ࡞ࢹࣂ࢖ࢫࡀồࡵࡽࢀ࡚࠸ࡿ㸬ࡇࢀࡽ

ࡢ㥑ື᮲௳࡟㐺ᛂࡍࡿᢏ⾡࡜ࡋ࡚㸪᩿⇕ⓗㄽ⌮ᅇ㊰㸪ࢧࣈࢫࣞࢵࢩࣙࣝࢻᅇ㊰ࡀᗈ ࡃ◊✲㸪㛤Ⓨࢆࡉࢀ࡚࠸ࡓ㸬ᮏㄽᩥ࡛ࡣࡇࢀࡽ஧ࡘࡢᢏ⾡ࢆ⤌ࡳྜࢃࡏࡓࢧࣈࢫࣞࢵ

ࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᥦ᱌ࢆ⾜ࡗࡓ㸬ᥦ᱌ࡋࡓࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮

ᅇ㊰ࡣ㸪2┦ࡢ࿘ᮇἼ㟁※࡟ࡼࡾ㥑ືࡉࢀ࡚࠾ࡾ㸪㟁※㛫ࡢ㟁఩ᕪࡀ᭱ᑠ࡜࡞ࡿࡼ

࠺࡟ࡑࢀࡒࢀࡢ㟁※ࡢ࿘ᮇ㸪㟁ᅽࢆタᐃࡍࡿࡇ࡜࡟ࡼࡾᅇ㊰ࡢ㟼ⓗ࢚ࢿࣝࢠ࣮ࢆ๐ ῶ࡛ࡁࡿࡼ࠺࡟ࡋࡓ㸬ᥦ᱌ࡋࡓࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰࡟ࡼࡾᇶᮏᅇ㊰㸪 4×4-bit஌⟬ჾࢆタィࡋ㸪SPICEࢩ࣑࣮ࣗࣞࢩࣙࣥ㸪࠾ࡼࡧᐇ⿦ࡋࡓLSIࢳࢵࣉࡢ  ᐃ࠿ࡽ㸪ᚑ᮶ᅇ㊰࡜ືస࿘Ἴᩘ㸪ᾘ㈝࢚ࢿࣝࢠ࣮ࡢẚ㍑ࢆ⾜ࡗࡓ㸬ࡲࡓࢧࣈࢫࣞࢵ

ࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢᾘ㈝࢚ࢿࣝࢠ࣮ࡣ㸪ᚑ᮶ࡢᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࡜

ࡣ␗࡞ࡗࡓ࿘Ἴᩘ≉ᛶࢆࡶࡗ࡚࠾ࡾ㸪≉ᛶࢆ㏆ఝࡍࡿࡓࡵ᪂ࡓ࡞ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ

⌮ࣔࢹࣝࡢᥦ᱌ࢆ⾜ࡗࡓ㸬⤖ᯝࢆ௨ୗ࡟ࡲ࡜ࡵࡿ㸬

1. ᐇ⿦ࡋࡓ4×4-bit஌⟬ჾ࡟࠾࠸࡚㸪ᥦ᱌ࡋࡓࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ

㊰ࡣᚑ᮶ࡢCMOSㄽ⌮ᅇ㊰࡜ẚ㍑ࡋ࡚⣙1/20㸪ࢧࣈࢫࣞࢵࢩࣙࣝࢻCMOSㄽ

⌮ᅇ㊰࡜ẚ㍑ࡋ࡚⣙2/3ࡢᾘ㈝࢚ࢿࣝࢠ࣮࡜࡞ࡗࡓ㸬

2. ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ᪂ࡓ࡞ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔࢹࣝ࠿ࡽ㸪 㟼ⓗ࢚ࢿࣝࢠ࣮ࡣࢧ࢖ࣥἼືస㸪2PC2ALࡢሙྜ㸪ᚑ᮶CMOSㄽ⌮ࡢ1/2㸪ᥦ

᱌᪉ἲࡢሙྜ㸪ᚑ᮶CMOSㄽ⌮ࡢ1/4࡜࡞ࡿࡇ࡜ࡀศ࠿ࡗࡓ㸬ࡲࡓ㸪ືⓗ࢚

ࢿࣝࢠ࣮ࡣ࿘ᮇT࡟ᑐࡋ࡚1/√

τ ࡢ๭ྜ࡛ኚ໬ࡋ࡚࠸ࡃࡇ࡜ࡀศ࠿ࡗࡓ㸬

91

92 7.2. ௒ᚋࡢㄢ㢟

7.2 ௒ᚋࡢㄢ㢟

ᮏ◊✲࡛ࡣࣉࣟࢭࢫ࡟0.18μmࢆ⏝࠸࡚࠾ࡾ㸪ࢺࣛࣥࢪࢫࢱࢧ࢖ࢬࡀ1.0μ/1.0μm

࡛࠶ࡗࡓ㸬㟼ⓗ࢚ࢿࣝࢠ࣮ࡢᙳ㡪ࡀᙉࡃ࡞ࡿ᭱᪂ࡢCMOSᢏ⾡(65nm, 46nm࡞࡝)

ࢆ⏝࠸ࡓᅇ㊰ࡢࢩ࣑࣮ࣗࣞࢩࣙࣥ㸪ィ ࠿ࡽ㸪ᥦ᱌᪉ἲࡢᛶ⬟ࢆホ౯ࡋࡓ࠸㸬ࡲࡓᥦ

᱌ࡋࡓࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢࢩ࣑࣮ࣗࣞࢩࣙࣥ⤖ᯝ࠿ࡽ㸪ືⓗ࢚ࢿ

ࣝࢠ࣮࡛ࡣᚑ᮶ࡢ᩿⇕ⓗㄽ⌮ᅇ㊰࡛࠶ࡿ2PC2ALࡢ࡯࠺ࡀపᾘ㈝࢚ࢿࣝࢠ̿࡜࡞ࡗ ࡓ㸬ືⓗ࢚ࢿࣝࢠ࣮ࡶ⪃៖࡟ධࢀࡓ㸪࠶ࡽࡓ࡞ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰

ࡢᥦ᱌ࢆࡍࡿ㸬ࢧࣈࢫࣞࢵࢩࣙࣝࢻ᩿⇕ⓗㄽ⌮ᅇ㊰ࡢ᪂ࡓ࡞ᾘ㈝࢚ࢿࣝࢠ࣮ᩘ⌮ࣔ

ࢹࣝ࡟࠾࠸࡚㸪ືⓗ࢚ࢿࣝࢠ࣮ࡀ࿘ᮇT࡟ᑐࡋ࡚1/√

τࡢ๭ྜ࡛ኚ໬ࡋ࡚࠸ࡃせᅉ

ࢆゎ᫂ࡍࡿ㸬

㈷ࡾࡲࡋࡓ㸬῝ࡃឤㅰ࠸ࡓࡋࡲࡍ㸬

㧗ᶫᗣᏹ෸ᩍᤵ࡟ࡣ᪥㡭࠿ࡽ◊✲ࢆ㏻ࡌከࡃࡢ㠃࡛ࡈᣦᑟࢆ࠸ࡓࡔࡁࡲࡋࡓ㸬῝

ࡃឤㅰࡋࡓࡋࡲࡍ㸬

◊✲ᐊࡢᏛ⏕ㅖẶ࡞ࡽࡧ࡟㸪Ꮫ఍➼࡛ᅜෆእࡢከࡃࡢ◊✲⪅ࡢ᪉ࠎ࡟ᵝࠎ࡞㆟ㄽ㸪

࢔ࢻࣂ࢖ࢫࢆ࠸ࡓࡔࡁࡲࡋࡓࡇ࡜ࢆឤㅰ࠸ࡓࡋࡲࡍ㸬

᭱ᚋ࡟㸪௒᪥࡟⮳ࡿࡲ࡛ᵝࠎ࡞㠃࠿ࡽᨭ࠼࡚࠸ࡓࡔ࠸ࡓ⚾ࡢᐙ᪘㸪཭ே࡟ᚰ࠿ࡽ

ឤㅰࡢពࢆ⾲ࡋࡲࡍ㸬

ⓙᵝ㸪࡝࠺ࡶ࠶ࡾࡀ࡜࠺ࡈࡊ࠸ࡲࡋࡓ㸬

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ㄽᩥ

1. Kazunari Kato, Y. Takahashi, and T. Sekine, “Two Phase Clocked Subthresh-old Adiabatic Logic Circuit,” IEICE Electronics Express, Vol. 12(2015), No.

20, pp. 20150695

ᅜ㝿఍㆟ :

1. Kazunari Kato, Y. Takahashi, and T. Sekine, “Two Phase Clocking Subthresh-old Adiabatic Logic,” Proc. IEEE ISCAS 2014, pp. 598–601, June 1–5, Mel-bourne, Australia.

2. Kazunari Kato, Y. Takahashi, and T. Sekine, “Skew Tolerance Analysis and Layout Design of 4×4 multiplier Using Two Phase Clocking Subthreshold Adi-abatic Logic,”Proc. IEEE APCCAS 2014, pp. 495–498, Nov. 17–20, Okinawa, Japan.

3. Kazunari Kato, Y. Takahashi, and T. Sekine, “A 4×4-bit Multiplier LSI Im-plementation of Two Phase Clocking Subthreshold Adiabatic Logic,” Proc.

IEEE NEWCAS 2015, pp. 1–4, June. 7–10, Grenoble, France.

ᅜෆ఍㆟ :

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