5. Experimental Results
In this section, we show experimental results for evaluat- ing our RTL path mapping method by mapping RTL paths and RTL false paths identified with the method proposed in . We used three RTL benchmark circuits, LWF, Tseng and Paulin and an industrial circuit, MPEG. In these exper- iments, we used only the datapath part of each circuit and tried to map all the paths in the datapath. Table 1 shows the circuit characteristics of the circuits. Columns “#bit”, “#PI”, “#PO” and “#reg” show the bit width, the number of primary inputs, that of primary outputs and that of regis- ters, respectively. Sub columns “MIP-LS” and “Arbitrary” under “Area (#gates)” show the circuit area synthesized by MIP-LS  and that without restriction, respectively. From the area comparison, we confirmed that our method elim- inates the impact on logic synthesis results. In these ex- periments, we used Synopsys DesignCompiler to perform logic synthesis, Synopsys TetraMax to generate test patterns for gate level circuits synthesized with “Arbitrary”, Cadence Encounter Test and Diagnostics as a fault diagnostic engine, Synopsys Formality to perform equivalence checking and Synopsys PrimeTime to enumerate the gate level paths on Sun Microsystems Sun Fire X4100 (Opteron 256 (3 GHz), 16 GB memories).
key words: design-for-testability, scan design, generalized feedback/feed-
forward shift registers, security, scan-based side-channel attack 1. Introduction
Scan design is a powerful design-for-testability (DFT) tech- nique that warrants high controllability and observability over a chip and yields high fault coverage . However, this also accommodates reverse engineering, which contradicts security. There is a demand to protect secrete data from side- channel attacks and other hacking schemes. Hence, it is im- portant to find an efficient DFT approach that satisfies both security and testability. Various approaches to secure scan design have been reported . We reported a secure and testable scan design approach by using extended shift regis- ters called “SR-equivalents” that are functionally equivalent but not structurally equivalent to shift registers , . In , we considered a scan-based side-channel attack with re- set called differential-behavior attack and proposed several classes of SR-equivalent scan circuits using dummy flip- flops in order to protect the scan-based differential behav- ior attack. In , , linear structured circuits were con- sidered. We then expanded them into non-linear structured circuits and introduced two classes of generalized shift reg- isters (GSRs, for short) which are generalized feed-forward shift registers (GF 2 SRs, for short) ,  and generalized feedback shift registers (GFSRs, for short) , to consider their application to secure scan design.
NBTI, which is the dominant transistor aging mechanism in the latest process technology, increases the threshold voltage of a PMOS transistor stressed with negative gate voltages over a couple of decades. In order to improve reliability, other various aging mechanisms as well as NBTI, such as Hot Carrier Injection (HCI), Electro Migration (EM), Stress Migration (SM), and Time Dependent Dielectric Breakdown (TDDB), need to be taken into consideration [1, 6]. HCI, which increases the threshold voltage of an NMOS transistor under a source-drain voltage stress, cause gradual delay degradation like NBTI. EM and SM, which respectively occur due to an excessive current density stress or a structural stress, increase wire resistance, and thus lead to open or short faults. These phenomena cause sudden delay degradation or failure. TDDB, in which continuous stresses to a gate oxide film causes the insulating film breakdown, results in slow delay degradation up to a certain point and sudden delay degradation or a failure as shown in Fig. 1 . However, delay
T LB = max(T LB 1 , T
LB ) (8)
4.3 Schedule Optimization through Rectangle Packing We now introduce the concept of rectangles to represent core tests, then explain a flexible scheduling methodology based on NoC bandwidth sharing, which is inspired by the scheduling algorithm in . The use of rectangles have previously been proposed in ,  for dedicated TAM based scheduling approach. In this paper, the height of a rectangle represents the required NoC bandwidth to ob- tain the test application time represented by the horizontal length. Figure 7 illustrates two pairs of rectangles, each representing the test of Core 6 of p93791 circuit (ITC’02 benchmark ) when B max = 2000 Mbps and 800 Mbps,