トップPDF C111 2004 11 WRTLT 最近の更新履歴 Hideo Fujiwara

C111 2004 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C111 2004 11 WRTLT 最近の更新履歴 Hideo Fujiwara

It is, therfore, imperative to allow the BIST hardware be subjected (during the analysis) to the same defect level (impurity) as the functional circuits themselves. possibl[r]

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11 WRTLT pptx 最近の更新履歴  Hideo Fujiwara

11 WRTLT pptx 最近の更新履歴 Hideo Fujiwara

The security level of the secure scan architecture is determined by the probability that an attacker can identify the structure of the SR- quasi-equivalent circuit. Hence the attack p[r]

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J112 e IEICE 2004 3 最近の更新履歴  Hideo Fujiwara J112 e IEICE 2004 3

J112 e IEICE 2004 3 最近の更新履歴 Hideo Fujiwara J112 e IEICE 2004 3

All test vectors are applied but they can be partitioned into several sub test sets. In scan testing each test vector is shifted in (scanned in), and after a capture cycle, the test response is shifted out (scanned out), and at the same time the next test vec- tor is shifted in. The shift process contributes to a major part of the testing time. The shift time at a core depends on the number of wrapper-chains (the number of partitions of the scanned elements, i.e. the scan-chains and the wrap- per cells). The test time can be reduced by assigning a higher number of wrapper-chains to the core, which will make each wrapper-chain shorter (it includes less scanned elements). For systems composed of hard cores (a fixed number of scan-chains of fixed length), several test schedul- ing approaches have been proposed [6]–[9], [11]–[14], [16]. Aerts and Marinssen [1] investigated scan-chain partition- ing for soft cores (only flip-flops are given) where the con- straints are defined by available pins (bandwidth).
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J114 e JETTA 2004 6 最近の更新履歴  Hideo Fujiwara J114 e JETTA 2004 6

J114 e JETTA 2004 6 最近の更新履歴 Hideo Fujiwara J114 e JETTA 2004 6

Received February 24, 2003; Revised February 12, 2004 Editor: K.K. Saluja Abstract. This paper suggests three techniques on non-scan DFT of sequential circuits. The proposed techniques guarantee 100% fault efficiency by using combinational ATPG tool. In all the techniques, an additional circuit called CRIS is proposed to reach unreachable states on the state register of a machine. The second and third techniques use an additional hardware DL to uniquely identify a state appearing in a state register. The design of DL is universal. Test length and hardware overhead outperform the similar approaches.
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J111 e IEICE 2004 3 最近の更新履歴  Hideo Fujiwara J111 e IEICE 2004 3

J111 e IEICE 2004 3 最近の更新履歴 Hideo Fujiwara J111 e IEICE 2004 3

Table 4 Test application time (select from either Scan or NS-DFT). of the SoC. The 2nd column shows the maximum TAM width of each SoC. The 3rd column denotes the core num- ber denoted in Table 1. The 4th column shows the selected TAM width of each core. The 5th column shows the power consumption. The power consumption results are shown relative to the normal operation figures of the original core No.1. The 6th column shows the area size of each core. The 7th column shows the test application time of each core. The 8th column and the 9th column show test schedule of each core. “Start” denotes the test start time, and “end” denotes test end time. The 10th column shows maximum power con- sumption of each SoC under this test schedule. The 11th col- umn shows the total area size of each SoC. The 12th column shows the total test application time of each SoC, either.
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11 WRTLT 最近の更新履歴  Hideo Fujiwara

11 WRTLT 最近の更新履歴 Hideo Fujiwara

fujiwara@ogu.ac.jp Abstract—Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by using extended shift registers called “SR-equivalents” that are functionally equivalent but not structurally equivalent to shift registers [14-17]. In this paper, to further extend the class of SR- equivalents we introduce a wider class of circuits called “SR- quasi-equivalents” which still satisfy the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi- equivalents for several linear structural circuits, and also present the actual number of SR-quasi-equivalents obtained by the enhanced program SREEP.
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11 WRTLT pptx 最近の更新履歴  Hideo Fujiwara

11 WRTLT pptx 最近の更新履歴 Hideo Fujiwara

The security level of the secure scan architecture is determined by the probability that an attacker can guess right the structure of the. GF 2 SR circuit[r]

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S11 IEEE D&T 2004 7 最近の更新履歴  Hideo Fujiwara S11 IEEE D&T 2004 7

S11 IEEE D&T 2004 7 最近の更新履歴 Hideo Fujiwara S11 IEEE D&T 2004 7

Das (Jadavpur University, India), Hideo Fujiwara (Nara Institute of Science and Technology, Japan), Yungang Li (Beijing Huahong IC Design, China), Yinghua Min (Institute of Computing Tec[r]

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C112 2004 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C112 2004 11 WRTLT 最近の更新履歴 Hideo Fujiwara

Table1 shows a relation between input spaces and a sequence of instructions shown in Fig.1. An execution of each instruction consists of multiple cycles, and a state and values of inputs of a controller at each cycle are shown. During the execution, we fix and to , respectively. Symbols ’-’ and ’h’ means an unknown value and the same value as the previous cycle, respectively, and ’x’ means any value can be as- signed. From the table, we can find that inputs are up- dated at some specific cycles (temporal constraints) as well as their values are restricted (spatial constraints). An input temporal spatial constraint of a module is a sequence of input constraints, where an input constraint represent a set of values of inputs of the module that are constrained by values at the present and the last cycle. In Table1, each row corresponds to a input constraint, and any continuous cycles correspond to a input tempo- ral spatial constraint.
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C113 2004 11 ATS 最近の更新履歴  Hideo Fujiwara

C113 2004 11 ATS 最近の更新履歴 Hideo Fujiwara

Problem 1: Minimize the hardware overhead of a given data path under a boundary non-scan BIST, and a test scheduling algorithm, subject to a given power constrai[r]

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C115 2004 11 ATS 最近の更新履歴  Hideo Fujiwara

C115 2004 11 ATS 最近の更新履歴 Hideo Fujiwara

T J (k•n) = O(τ(k•n)) (11) Condition 2 of definition 4 implies that for any pair of states (s i , s if ), there exists a fault propagation sequence and hence no backtrack occurs between fault propagation, state justification and derivation of excitation. It also guarantees that the fault effect can be propagated to a primary output within sequence length of k. This means the fault propagation is performed on the combinational part duplication of size at most k•n. Generally, the time complexity of the fault propagation T D for an activated fault is τ–bounded. Therefore,
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C116 2004 11 ATS 最近の更新履歴  Hideo Fujiwara

C116 2004 11 ATS 最近の更新履歴 Hideo Fujiwara

The above Lemma basically reaches the definition of cover relation, as described in [9]. 2.4 Maximum TEG Definition 11: Given a TG G, a TEG E which cannot be covered by any other TEG of the TG except by its equivalent TEG, is called a maximal TEG of G. If number of maximal TEGs is one, then that maximal TEG is called as the maximum. If a TG has a maximum TEG, how can we find out that? One method may be to attempt to draw all TEGs, and then find the maximum TEG among

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C114 2004 11 ATS 最近の更新履歴  Hideo Fujiwara

C114 2004 11 ATS 最近の更新履歴 Hideo Fujiwara

E-mail: {kazuk-ka, kounoe, fujiwara}@is.naist.jp Abstract This paper presents a method of template generation for instruction-based self test of processor cores. A test pro- gram template is an instruction sequence with unspecified operands, and represents paths for justification of test pat- terns and propagation of test responses for a module un- der test (MUT). In order to justify value of MUT inputs, we introduce a concept of adjacent registers of the MUT that makes it possible to consider input spaces of the MUT de- termined by signals from other modules as well as signals directly from registers. We efficiently generate possible tem- plates considering dependence of instructions each of which invokes one or more data transfers between registers. The method also generates multiple templates in effective order to detect faults, which may cover different input spaces, and therefore, different detectable fault sets.
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EPUB11田丸pdf 最近の更新履歴  epubcafé

EPUB11田丸pdf 最近の更新履歴 epubcafé

• を技術仕様 採用 こ 時点 文 未定義 あ 3.1 実装 • ン 文 移動 (Unicode 1.1 互換性消失 ) • ( 技術仕様 JIS X 0213:2004 対応 ) 2.1 1998 38,952 • 通貨記号追加 多少数 記号定義変更 3.0 1999 49,259 • CJK 統合漢 拡張 A 漢 6,582 文 追加 3.1 2001 94,205

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11 IEICE 最近の更新履歴  Hideo Fujiwara

11 IEICE 最近の更新履歴 Hideo Fujiwara

ものを除き, k 段 SR 等価回路数 N (k) はちょうど, N (k) = 2 k !/k! − 1 となる. 表 2 に , I 2 SR , LF 2 SR , LFSR , LF 2 SR+I 2 SR , LFSR+I 2 SR 5 種 類 ク ラ ス に つ い て , SR 等 価 回 路 数 を 示 し た が , LF 2 SR+LFSR , LF 2 SR+LFSR+I 2 SR

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EPUB11田嶋pdf 最近の更新履歴  epubcafé

EPUB11田嶋pdf 最近の更新履歴 epubcafé

▪ 環境によって化ける可能性がある文字② フォントバージョンによる変化  過去に印刷データ制作時に発生していたと同様、フォント字形差による字形変化問題も存在し ます。具体的には、小塚ゴシック Pro やリュウミン Pr5/Pr6 など、JIS90 字形を基準としたフォントで作 られた印刷データをもとに電子書籍を制作し、今後一般的に使用されると思われる JIS2004 字形を基準と したフォントを採用した電子書籍ビューアで読んだ場合、JIS 規格例示字形改正に伴って字形が変化 する可能性がある文字が 168 文字あります。Windows Vista メイリオで字形が変わって一時話題になっ た「葛飾区」と「葛城市」「葛」字などが有名な例です。なおこの変化は「字形が変わる可能性があ る」であって「必ず字形が変わる」わけではありません。各フォントベンダー方針によって変化する文 字に幅があります。
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C107 2004 5 ETS 最近の更新履歴  Hideo Fujiwara

C107 2004 5 ETS 最近の更新履歴 Hideo Fujiwara

E-mail: {tsuyo-i, ohtake, fujiwara}@is.naist.jp Abstract This paper proposes a non-scan design scheme to en- hance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that can- not be detected by using the original behavior, we design an extra logic, called an invalid test state and transition gen- erator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.
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C108 2004 5 ETS 最近の更新履歴  Hideo Fujiwara

C108 2004 5 ETS 最近の更新履歴 Hideo Fujiwara

The complexity of scan tree architecture generation to find the optimal solution depends on the number of test patterns and scan cells.. This problem is NP-complete.[r]

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NewsLetter11 最近の更新履歴  GCOEアジア保全生態学 NewsLetter11

NewsLetter11 最近の更新履歴 GCOEアジア保全生態学 NewsLetter11

already been reported (e.g. Kumagai et al. 2004; Saitoh et al. 2005). However, several phenomena such as the effects of unpredictable intra-annual dry spells on gas exchange properties via the physiological processes of the trees and carbon consumption within the forest ecosystems have yet to be clarified. To better understand these phenomena, as part of a global centre of excellence (GCOE) project, we re-initiated hydrometeorological observations in 2009. In addition to several researchers, some GCOE graduated students have been also conducting field research at this site for their doctoral theses. Here, we briefly describe these studies.
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Lec1 11 最近の更新履歴  yyasuda's website

Lec1 11 最近の更新履歴 yyasuda's website

The classical measure of welfare change is consumers’ surplus (CS) , which is the area below the Marshallian demand curve and above market price... That is, EV (resp. CV ) requires to ke[r]

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