General Description - PDF pci b & pcit1 MegaCore Function User Guide

The pci_b MegaCore function (ordering code: PLSM-PCI/B) is a hardware-tested, high-performance, flexible implementation of the 32-bit, 33-MHz PCI master/target interface. The pcit1 MegaCore function (ordering code: PLSM-PCIT1) is an implementation of the 32-bit, 33-MHz PCI target interface. Because these functions handle the complex PCI protocol and stringent timing requirements internally, designers can focus their engineering efforts on value-added custom development, significantly reducing time-to-market.

Optimized for Altera

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APEX 20K, FLEX 10K, and FLEX 6000

architectures, the pci_b and pcit1 functions support configuration, I/O,

and memory transactions. With the high density of FLEX devices,

designers have ample resources for custom local logic after implementing

the PCI interface. The high performance of FLEX devices also enables the

functions to support unlimited cycles of zero-wait-state memory-burst

transactions, thus achieving 132 Mbytes per second throughput, which is

the theoretical maximum for a 32-bit, 33-MHz PCI bus.

In the pci_b function, the master and target interface can operate independently, allowing maximum throughput and efficient usage of the PCI bus. For instance, while the target interface is accepting zero-wait state burst write data, the local logic may simultaneously request PCI bus mastership, thus minimizing latency. In addition, the pci_b function’s separate local master and target data paths allow independent data prefetching and posting. Depending on the application, first-in first-out (FIFO) functions of variable length, depth, and type can be implemented in the local logic.

To ensure timing and protocol compliance, the functions have been vigorously hardware tested. See “Compliance Summary” on page 30 for more information on the hardware tests performed.

As parameterized functions, pci_b and pcit1 have configuration registers that can be modified upon instantiation. These features provide scalability, adaptability, and efficient silicon usage. As a result, the same MegaCore functions can be used in multiple PCI projects with different requirements. For example, both functions offer up to six base address registers (BARs) for multiple local-side devices. However, some applications require only one contiguous memory range. PCI designers can choose to instantiate only one BAR, which reduces logic cell consumption. After designers define the parameter values, the

MAX+PLUS II software automatically and efficiently modifies the design and implements the logic.

This user guide should be used in conjunction with the latest PCI specification, published by the PCI Special Interest Group (SIG). Users should be fairly familiar with the PCI standard before using this function.

Figure 1 shows the symbol for the pci_b function.

Figure 1. pci_b Symbol

LM_REQN LM_LASTN LM_BUSYN LM_ADI[31..0]

LM_CBEN[3..0]

Master Outputs LM_ACKN TRDYRN LM_DATO[31..0]

LM_TSR[7..0]

Target Inputs LT_DATI[31..0]

LT_RDYN LT_DISCN LT_ABORTN Target Outputs LT_FRAMEN LT_ACKN IRDYRN LT_ADR[31..0]

LT_CMD[3..0]

LT_DATO[31..0]

LT_BEN[3..0]

BAR_HIT[5..0]

EXP_ROM_HIT Interrupt Req L_IRQN PCI Signals

CLK RSTN IDSEL

AD[31..0]

CBEN[3..0]

PAR

PERRN SERRN

INTAN

PCI_B

MSTR_ENA MWI_ENA PERR_ENA SERR_ENA

MABORT_RCVD SERR_SIG PERR_DET Local Signals

TABORT_RCVD TABORT_SIG PERR_REP Status Reg IO_ENA MEM_ENA Command Reg Arbitration

GNTN REQN Address/Data

Control

Interrupt Parity Error

Cache Line Reg CACHE[7..0]

System Master Inputs

FRAMEN_IN FRAMEN_OUT IRDYN_IN IRDYN_OUT DEVSELN_IN DEVSELN_OUT TRDYN_IN TRDYN_OUT STOPN_IN STOPN_OUT

BAR0="H"FF000000""

BAR0_DEFAULT="H"FF000000""

BAR0_DEFAULT_ENA="NO"

BAR1="H"FF000000""

BAR1_DEFAULT="H"FF000000""

BAR1_DEFAULT_ENA="NO"

BAR2="H"FF000000""

BAR2_DEFAULT="H"FF000000""

BAR2_DEFAULT_ENA="NO"

BAR3="H"FF000000""

BAR3_DEFAULT="H"FF000000""

BAR3_DEFAULT_ENA="NO"

BAR4="H"FF000000""

BAR4_DEFAULT="H"FF000000""

BAR4_DEFAULT_ENA="NO"

BAR5="H"FF000000""

BAR5_DEFAULT="H"FF000000""

BAR5_DEFAULT_ENA="NO"

NUMBER_OF_BARS=1 EXP_ROM_ENA="NO"

EXP_ROM_BAR="H"FF000000""

EXP_ROM_DEFAULT_ENA="NO"

EXP_ROM_DEFAULT="H"00000000""

CAP_LIST_ENA="NO"

CAP_PTR="H"40""

CIS_PTR_ENA="NO"

CIS_PTR="H"00000000""

INTERRUPT_PIN_REG="H"01""

MAX_LATENCY=0 MIN_GRANT=0 CLASS_CODE=H"FF0000"

DEVICE_ID=H"0002"

REVISION_ID=H"01"

SUBSYSTEM_VENDOR_ID=H"0000"

SUBSYSTEM_ID=H"0000"

VENDOR_ID=H"1172"

INTERRUPT_ACK_ENA="NO"

HOST_BRIDGE_ENA="NO"

INTERNAL_ARBITER="NO"

TARGET_DEVICE="EPF10K30RC240"

Figure 2 shows the symbol for the pcit1 function.

Figure 2. pcit1 Symbol

PCI Signals CLK RSTN IDSEL AD[31..0]