EDSFair2007

T. Kuroda (1/70)

ユビキタス情報社会を創る

システムLSI

慶應義塾大学理工学部電子工学科

黒田忠広

www.kuroda.elec.keio.ac.jp

Challenges and Opportunities

３つのレベルで課題と展望を議論 １）デバイス（物理学）

２）集積回路（電子工学）

T. Kuroda (3/70)

CMOSスケーリングの終焉?

„ ITRS roadmap:

solutions are not known (red)

„ “Life after CMOS: Imminent or Irrelevant?” (DAC 2002, session)

„ “Changing Vectors of Moore’s Law” (IEDM 2002, luncheon)

„ “Workshop on Implications of Near-Limit CMOS on Circuits

and Applications” (ISSCC 2002, workshop)

„ “Scaling Limit in a Power Limited Environment, Architecture

versus Circuit Design” (Symp. VLSI Circuits 2002, panel)

„ “For The LAST Time, Who is Going to Solve the POWER

Problem!” (IEDM 2003, panel)

量産年 単位 2003 2004 2005 2006 2007 2008 2009 2012 2015 2018 ゲート長 nm 45 37 32 28 25 22 20 14 10 7 Equivalent Oxide Thickness (EOT) Å 13 12 11 10 9 8 8 7 6 5 ゲート空乏化、 反転層厚 Å 8 8 7 7 4 4 4 4 4 4 最大ゲート

リーク電流 A/cm2 2.2E+02 4.5E+02 5.2E+02 6.0E+02 9.3E+02 1.1E+03 1.2E+03 2.4E+03 1.0E+04 2.4E+04

サブスレショルド リーク電流 nA/um 30 50 50 50 70 70 70 100 300 500 サブスレショルド 特性調節係数 1 1 1 1 1 0.8 0.7 0.5 0.5 0.5 移動度増大係数 1 1.3 1.3 1.4 2 2 2 2 2 2 飽和速度増大係数 1 1 1 1 1 1 1 1.1 1.3 1.3 相対性能 1.00 1.26 1.39 1.60 1.86 2.20 2.49 4.05 6.80 10.77

戦略転換

T. Kuroda (5/70)

マルチコア

Montecito (90nm) Intel ISSCC’05 [16.2, 16.7] Dual Cores CELL (90nm SOI) IBM & SONY & 東芝

ISSCC’05 [7.4, 10.2, 20.3, 26.7]と Rumbus[28.9]

SPE (Synergistic Processing Element) :信号処理向け32ビット 8wayのSIMD型

Pessimistic opinions have been proven wrong time & time again! But, …

限界説

0.01 0.1 1 10 100 1970 1980 1990 2000 Year of prediction Minimum channel length (um) Prediction Real Life 2010

Carver Mead & Lynn Conway, “Introduction to VLSI Systems” (1980)

Section 9.8: Quantum mechanical lower limit (tunneling effect will dominate device operation) “Thickness such as gate oxide and depletion layer should be larger than several nano-meters.”

Mead

Momose (IEDM 1994)

“Gate leakage at Tox=1.5nm is accepted under high Ids at L=0.1um”

T. Kuroda (7/70)

Source: IEDM ‘96-’03 & Symp. on VLSI Tech. ‘00-’03

加熱する競争

1) Competition increases due to ITRS 2) Researchers investigate scaling limit

2000 2005 2010 2015 0 20 40 60 80 100 IEDM 2001, Toshiba L=35nm IEDM 2002, Toshiba L=14nm

2004 Symp. on VLSI Tech., Toshiba

L=10nm

2004 Symp. on VLSI Tech., TSMC

L=5nm

Year of production

MPU Physical Gate Length (nm)

ゲート支配力の低下

D S G C_B C_G C_D

„ When Tr is too small, it

becomes a resistor, since C_D

becomes comparable to C_G.

„ Drain Induced Barrier Lowering

(DIBL)

„ Tr does not turn

off, nor saturate.

Short L S D Increase Drain voltage Long L Increase Drain voltage S D Barrier height „ When Tr is not

too small, it turns off and saturates.

T. Kuroda (9/70)

トンネルリークの増大

Leakage ! Tradeoff: ON / Off (V_TH) 1 10 100 1000 10000 30 50 70 90 110 130 Temp (C) Ioff (na/u) 0.25u 45nm 1 10 100 1000 10000 30 50 70 90 110 130 Temp (C) Ioff (na/u) 0.25u 45nm _{tunnel leakage}

subthreshold leak

新材料

high-k (+metal) Strained-Si 1) material Leakage ! Tradeoff: ON / Off (V_TH)

T. Kuroda (11/70)

High-k絶縁膜とメタルゲートによるゲートリーク低減

Gate Leakage Solutions:

High-k + Metal Gate

50nm

Silicon substrate 1.2 nm SiO₂

Gate

~0.3nm: depleted

Source: Spectrum IEEE, Pat Gelsinger, Intel

90nm MOS Transistor

4 layer of SiO₂

molecule

issues: mobility, reliability

„ Gate oxide thickness is reduced

by 2~4A/generation

(1.2nm@90nm, 1.0nm@65nm, 0.8nm@45nm)

„ 3A equivalent oxide reduction by

using metal gate to eliminate poly-gate depletion layer

ひずみシリコンによるオン電流増大

D G S PMOS S D G NMOS

„Process-Induced Strained Silicon

„10-25% higher ON current, 84-97% leakage current reduction

or 15% active power reduction.

„Substrate-Strained Silicon

T. Kuroda (13/70)

新構造

Double Gate Surrounding Gate

high-k (+metal) Strained-Si 1) material 2) structure Leakage ! Tradeoff: ON / Off (V_TH)

Ultra Thin Body

Beyond Conventional CMOS

Substrate G T_Fin ~ (2/3) L_g D S FinFET Ultra Thin Body

T_SOI ~ (1/3) L_g S D G Substrate IEDM 2002 (IBM) Source Source Drain Drain Gate Gate Source Source Drain Drain Gate Gate Lateral CD control by oxidation (not lithography)

T. Kuroda (15/70)

9.1. 東芝：Symp. on VLSI Tech. 2004

Bulk，SiON, 0.9V，metal-gate, elevated S/D (ITRS: SOI, high-k, 0.5V，metal-gate)

T. Kuroda (17/70) 19.1. TSMC : Symp. on VLSI Tech. 2004

テクノロジ・ブースタ

Non-Planer Structure

ultra thin body double gate

triple gate

surrounding gate

Mobility Scaling

strained Si

anisotropic surface mobility

Ge (thin film on Si wafer)

compound semiconductor carbon nanotubes Performance Year Material high-k metal gate Clas sical Scali ng

T. Kuroda (19/70)

進化から革新へ

3D integration

革新的ナノテク

Spintronics Single-electron logic (SET, Toshiba)

Molecular devices

Single-electron memory (SESO, Hitachi)

超薄膜チャネル (∼2nm) ソース ドレイン ゲート 酸化膜 基板 DNA computing

T. Kuroda (21/70)

Challenges and Opportunities

„ Device Level (Physics)

Leakage problem shall be solved.

„ Integrated Circuit Level (Electronics)

Powerwall (power vs. speed) Variations 130nm 30% 5X 0.9 1.0 1.1 1.2 1.3 1.4 1 2 3 4 5

Normalized Leakage (Isb)

Norma lized Fre q ue ncy 130nm 30% 5X 0.9 1.0 1.1 1.2 1.3 1.4 1 2 3 4 5

Normalized Leakage (Isb)

Norma

lized Fre

q

ue

ncy

PLEASE TURN OFF

AT THE MAIN

When Not In Use

Main Cock

MTCMOS

T. Kuroda (23/70)

PLEASE ADUST

PERFORMNACE

V

_TH

VTCMOS

トランジスタ毎にV

_TH

を制御

T. Kuroda (25/70)

EDAが重要

低電力設計のための１０の秘訣

Tip 1: Optimize and control V_DD and V_TH.

Tip 2: Total power is minimum when P_leakage/P_active = 30/70. Tip 3: If you don’t need to hustle, relax and save power. Tip 4: Utilize surplus timing with multiple V_DD’s and V_TH’s.

Tip 5: Total power is minimum when V_DDL/V_DDH =0.7.

Tip 6: Two types are sufficient.

Tip 7: Adapt to the change with variable V_DD and V_TH. Tip 8: Two levels are sufficient.

Tip 9: Cooperate across various levels of design hierarchy. Tip 10: Right circuit for the right job.

T. Kuroda (27/70)

秘訣１: V

_DD

とV

_TH

を最適に制御

0 0.5 1 0 0.5 1 Normalized power V_DD [V] P_DYNAMIC 1 2 3 4 5 0 Normalized delay Delay P_{SUBTHRESHOLD LEAK} P_{GATE LEAK} Drain Induced Barrier Lowering (DIBL) Long L Increase Drain voltage S D Barrier height Short L S D Increase Drain voltage Courtesy: S. Narendra

秘訣２: P

_leakage

/P

_active

= 30/70のときに電力最小

0.3 0.5 0.7 0.9 1.1 1.3 1. 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 VTH (V) DD (V) V Equi-power (solid-lines) 0.05 0.1 0.2 0.3 0.4 0.5 0.7 κ_P =1.0 _1.2 1.3 1.4 P_leakage P_total =30% κS =1 .0 0.9 0.8 0.7 0.6 0.5 1.1 1.2 1.3 Eq ui-s pee d (b rok_en line_s) P S V_DD P P_active∝ V_DD2 30% 70% P_total P_leakage∝ 10 V_DD -V_TH s V_DD P P_active∝ V_DD2 30% 70% P_total P_leakage∝ 10 V_DD -V_TH s P_leakage∝ 10 V_DD -V_TH s -V_TH s

T. Kuroda (29/70)

P

_leakage

/P

_active

= 30/70

„ IBM Power5 „ Intel Pentium4

P_leak

仕事は時間一杯かけてゆっくり仕上げるのが省エネ

Active Active Sleep E=CV_H2 E=CV_L2 Cycle

T. Kuroda (31/70)

秘訣４: 多V

_DD

多V

_TH

で余った時間を電力削減に利用

1.0

0.5

Supply Voltage Ratio

1.0

0.4

0.5 1.0 1.5

V₁ (V)

Power Dissipation Ratio

V₂/V₁ P₂/P₁ { V₁, V₂ } V₂/V₁ V₃/V₁ { V₁, V₂, V₃ } 0.5 1.0 1.5 V₁ (V) P₃/P₁ V₂/V₁ V₃/V₁ V₄/V₁ 0.5 1.0 1.5 V₁ (V) P₄/P₁ { V₁, V₂, V₃, V₄ } „

秘訣5: V

_DDL

/V

_DDH

=0.7のときに電力最小

„

秘訣6: ２種類あれば十分

秘訣７: 可変 V

_DD

、V

_TH

で負荷の変動に対応

Montecito (90nm) 1.5-2X performance 0.8X power of Madison-9M (130nm) IIR DAC ADC ADC Calc -+ P_limit P_calc R_package V_die V_connector IIR DAC ADC ADC Calc -+ P_limit P_calc R_package V_die V_connector Power -> V_DD Temp. -> V_DD V_DD -> f

T. Kuroda (33/70)

Challenges and Opportunities

„ Device Level (Physics)

Leakage Problem

„ Integrated Circuit Level (Electronics)

Powerwall (power vs. speed) Variations

„ Business Level (Economics)

Post PC Applications SoC vs. SiP

1950 1960 1970 1980 1990 2000 2010 年 大型 中型 EWS PC モバイル ENIAC 1万円 1億円 コンピュータの価格 真空管 トランジスタ IC (Bip.) LSI (NMOS) VLSI (CMOS) システムLSI 軍事 科学 科学 工学 OA 民生

ダウンサイジング

T. Kuroda (35/70)

今後のダウンサイジング

„ コンピュータ：

PC -> Portable -> Wearable -> Implantable -> Paintable

（20万円）（2万円）（2千円） （200円） （20円）

OA -> Personal (Quality of Life、人間中心)

データ 人が入力 -> 環境からセンシング

„ 通信：

Office LAN -> Home LAN -> PAN -> Body -> Proximity

配線 -> 短距離ワイヤレス

„ ユビキタス情報化社会

LSIから見たユビキタス情報化社会

考えるモノ、話すモノ 人間や環境とコンピュータ との快適なインタフェース ウエアラブルコンピュータ インプランタブルコンピュータ インターネット （ブロードバンド） コンピュータを 見えなくする* （ワイヤレス） （超低電力） 高性能 サーバ （超高速） （認識） （低コスト）

* “The most profound technologies are those that

disappear. They weave themselves into the fabric of everyday life until they are indistinguishable from it.” Mark Weiser, “The Computer for the 21st Century,” Scientific American, 265 (3), pp.94-104, 1991.

T. Kuroda (37/70)

コンピュータが人を認識する

„

カメラが人物を見つける: AF、AE、AZ、防犯 …

遺伝的アルゴリズム（ソフト）と専用LSI（ハード）で実現

Y. Hori and T. Kuroda et al., Symp. On VLSI Circuits 2006

人数カウント（駅）

T. Kuroda (39/70)

人数カウント（イベント会場）

さまざまな応用

z

顔を自動検出してデジカメ・ビデオの自動焦点や自動露光を可

能にし、きれいな写真やビデオを誰でも撮れるようにする。

z

顔を自動認識してデジカメ・ビデオで撮った写真・ビデオに誰が

写っているかをタグ（Exif）に自動記録して検索を可能にする。

z

顔を自動認識して例えば運動会で走っている子供を自動追尾し

ズームアップして写真・ビデオ撮影する。

z

人物を自動認識して往来する人数を数えてマーケティング情報

に活用したりセキュリティに応用する。

z

指などのサインでデジカメ・ビデオなどのリモコン代わりにする。

z

手話翻訳をする。

T. Kuroda (41/70)

ユビキタスエレクトロニクス

Processor count per person

1950 1960 1970 1980 1990 2000 2020 Year Large scale Office / middle WS PC historical Vac. tube Transistor IC LSI VLSI 0.001 0.01 0.1 1 10 100 Embedded Ubiquitous Computing System LSI 1000 SiP Electronics is part of environments enhancing convenience and security of daily life. People use electronics consciously. Ambient Electronics Ubiquitous devices 2010 Everybody Everywhere Unaware

センサーネットワーク

MIT Media Lab

Responsive Environment (Joseph Paradiso) Ambient Intelligence Group (Pattie Maes) Human Dynamics (Sandy Pentland)

Affective Computing (Rosalind Picard)

T. Kuroda (43/70)

センサネット

ライフ顕微鏡

出典：矢野和男 「センサとは何か」ウェブを越えるそのインパクト

Computing Paradigm：細粒分散処理へ

Shift toward fine-grained, distributed interfaces • Ubiquitous Computing (PARC/Weiser)

• Things That Think (MIT)

• Disappearing Computer (EU) • Invisible Computing (Microsoft) • Pervasive Computing (IBM)

• Paintable Computing (MIT) • Pushpin Computing (MIT)

T. Kuroda (45/70)

香りを用いた分散情報処理

50m Cs Cn₁ ② 30m 60m ① ③ ④ Cn₂

S. Miura, T. Kuroda et al., "Evaluation of Parking Search using Sensor Network,"

IEEE International Symposium on Wireless Pervasive Computing, Jan. 2006.

8 0 _{60 120 180 240 300 360 420 480 540} 6 4 2 10 Cars Sea rch Time (min) 8 With Aroma 0 _{60 120 180 240 300 360 420 480 540} 6 4 2 10 Random Search Cars Sea rch Time (min)

短距離ワイヤレス （数10cm ~数10µm）

Intelligent Tires Wireless Assembly

T. Kuroda (47/70) Memory Bus

チップ内演算性能とチップ間通信性能

Chip Performance Year 70 80 90 00 10 4004 8086 286 Intel386 Intel486 Pentium Pentium4 X1.7 0 / y ear 100 MIPS [instruction/s] 0.01 0.1 1 10 1000 10000 100000 1000000

Pin Bandwidth Data Rate [MB/s]

1 10 100 1000 10000 Bus on Board ATA (HDD) Ethernet ISA PCI PCI-EX Serial ATA X1.4 4 / y ear Fast Ethernet

幾何学的差違（面積vs.周辺）が 性能ギャップを生む

TRANSISTOR Scaling Per year

Gate length [x] 0.87 Voltage [V] 0.87 Capacitance [c]~[x2_{/x] 0.87} Current [i]~[v2_{/x] 0.87} Speed [i/cv] 1.15 WIRE Wire pitch [x] 0.87 Chip size [s] 1.06 Tracks [t]~[s/x] 1.22 Grids [g]~[t2_{] 1.49} „Rent’s rule:

Bandwidth demand from a module with capacity C (grids*speed) grows as C0.7_.

Required pin bandwidth: x1.45/year

„Pin bandwidth

1.15 (Speed) x 1.11 (Pin #) = x1.28/year

Periphery

„Chip performance

1.15 (Speed) x 1.49 (Grids) = x1.71/year

Area „Moore’s Law Chip per form ance : 1. 71/y ear Pin ba ndwi dth : 1 .45/ye ar Scaling:1.28/year circuit innovation Year Data Rate

T. Kuroda (49/70)

従来のチップ間通信は限界

’96 ’98 ’00 ’02 ’04 ’06 100G 1T Data Ra te [b/s] Year ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ 1G 10G Speed-wall Stanford (1ch) Stanford (1ch) NEC (1ch) Power/Area-wall Toshiba (4ch,4W) Rambus (26ch) NTT (16ch,8W) Hotrail (32ch) NEC (4ch,5W) NEC (21ch,3W) NEC (20ch,8W) TI (20ch,6W) Intel (32ch,15W) IBM,Sony, Toshiba (48ch,6W) Hitachi (1024ch,12W)

SoCでI/Oを減らせば電力削減

Separate chips 891mW 240mW DRAM Logic & memory Embedded DRAM Power

16Mbit

DRAM

Speech codec Multiplexer MPEG-4 Video Codec Host I/F DRAM I/F PLL Cam I/F Display I/F Pre-filter VT VT VT VT MPEG4 codec DRAM - logic interface „ 70% power reduction by

DRAM embedding technology

T. Kuroda (51/70) DR AM PC Board Package PCB DR AM SRAM Analog CPU Connection DR AM PC Board Package PCB DR AM SRAM Analog CPU Connection _DRA M SRAM Analog CPU DR AM SRAM Analog CPU

SoCからSiPへ

System-on-a-Board CPU SRAM _DRA M Analog CPU SRAM _DRA M Analog Lower Cost, QT_AT Low pow

er, High s_peed

System-in-a-Package (SiP) System-on-a-Chip (SoC) Mask Set Cost [ M $] 0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n 0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n 0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n Generation [µm] Source: Intel A S I C A S S P 0 2000 4000 6000 8000 10000 12000 14000 2000 2001 2002 Year De si gn s tarts A S I C A S S P 0 2000 4000 6000 8000 10000 12000 14000 2000 2001 2002 Year De si gn s tarts

Number of design starts is declining from 1997.

CANDE の2010年予想

CANDE 5-Year predictions from 2005 (to be reviewed in 2010) were:

1) IC-Package CAD will be a part of standard design flow

2) India and China will have more EDA startups than U.S. 3) Analog Designers will still resist high-level models and

languages

4) A complete Open Source RTL-GDS tool flow will exist

5) Nearly all EDA tools will take advantage of multi-processors

6) Fewer than 200 commercial chips released in 45 nm technology

7) No practical nanotech computing products

8) SPICE-type simulators will still be the workhorse of analog designs

9) Moore's law will be dead

10) System in Package will boom

The CANDE （Computer-Aided Network DEsign）Committee is a technical activity of the IEEE

Circuits and Systems Society and IEEE Council on Electronic Design Automation which acts as a working group for electronic computer-aided design. The first CANDE Workshop was held in

T. Kuroda (53/70)

CANDE 予測の実績

CANDE PREDICTIONS – as rated at the 2001 CANDE Workshop

Results: 19 came true, 4 partially, 15 did not

Key: Blue – Correct (not necessarily in 5 years) Green – Did occur partially Red – Did not occur

1986 (6 came true, 1 partially, 3 did not)

○ 1. UNIX will be the dominant operating system

× 2. General Purpose Parallel machines will replace today’s computers; they will be designed for high performance on major CAD algorithms (e.g. SPICE, Logic Synthesis, Fault Simulation, Simulated Annealing, Device Simulation)

△ 3. The big problem for CAD will become the validation of specifications

× 4. The major developments in CAE/CAD will be in the environments for users

○ 5. The test problem will still be considered NP-hard, boring, and unsolved ○ 6. Many CAD tools will finally use hierarchy effectively

× 7. General silicon compiler not developed yet but targeted silicon compiler for DSP and other specific applications will be in general use

○ 8. SPICE will still be the standard circuit simulator

○ 9. CAD Tools will increasingly take into account statistical fluctuations in the manufacturing process

○ 10. Full hand-crafted custom will still be an important part of design

1979 (4 came true, 1 partially, 3 did not)

× 1. Design System will be a Network Formed With Dedicated Processors For Specific Functions

× 2. Heavy Emphasis on Testability and Test Generation During the Design Phase

○ 3. Integrated Verification Tools for Checking at Each Step in the Design Cycle ○ 4. Much Greater Use of Canonical Circuit Forms (PLA, ROM) Via Design Aids ○ 5. The Design Station is Highly Interactive for all Phases and Includes Graphics

△ 6. Sets of Compatible Software will be Used for Design and Verification

△ 7. Circuit and Process Simulation Programs are Closely Linked to an Ongoing Process Data Storage System

× 8. Layout will be Manipulated in Symbolic Form

1996 (4 came true, 1 partially, 5 did not)

× 1. Windows NT will be the only OS for commercially viable CAD applications × 2. X86 machines will ship as more than 50% of EDA platforms

× 3. More than 80% of the CAD effort will be directed toward software and “FPGA”-based programmable hardware

○ 4. EDA companies will distribute all their products (tools, libraries, etc,) on the Internet

△ 5. The hardware/software co-design problem will have become the driving system-level problem

× 6. “Pay per use” EDA tools will be in widespread use

○ 7. Tool suites for mainstream designers will be a significant fraction of total EDA ○ 8. Portable voltage will be 1.8 – 1.2 V, driving significant new circuit design and EDA

challenges

× 9. The IP crisis will be solved by an open IP industry and a mix-and-match standard

○ 10. Software will have become 60 to 80 % of the overall cost of an embedded system

1991 (5 came true, 1 partially, 4 did not)

○ 1. Hardware/software co-design will be one of the most important design problems ○ 2. Support will still be the biggest hidden cost for both CAD vendors and customers

× 3. MCM CAD becomes a reality

×4.MCM will enable new CAD and semiconductor businesses

△ 5. Internal CAD will make a come-back

○ 6. There will be tools for validation of specifications

× 7. Partitioning will emerge as a commercial product

○ 8. The telecommunications industry will provide the most challenging problems in CAD ○ 9. SPICE algorithms still dominate circuit simulation

× 10. Frameworks will be provided by computer vendors

従来のSiPチップ間通信：ワイヤボンディング

T. Kuroda (55/70)

周辺から面へ

MPU Memories

Sensor / RF / Analog

„

Bonding (Conv.)

„

Through Si Via (Future)

(+) area contact：

large # of connections（~10000） short distance（~0.1mm）

(-) expensive process / reliability issue (-) low yield due to Known Good Die

issue : difficult to test in fine pitch (-) scaling limit due to mechanical

contacts （~10µm pitch）

(+) low cost, practical (-) peripheral contact：

small # of connections （~100）

機械式から電子式へ

„

TSV

„

Wireless Interface

„ Proposal

wireless transceiver arrays

(-) process (-) KGD

(-) scaling limit

(+) no addition in process, no reliability issue (+) KGD solvable : easy to attach and remove

(+) high density channels (below 10µm pitch)

(+) 3D scaling scenario (thinning a chip) (+) channels through active devices

T. Kuroda (57/70)

３次元集積化のための面インタフェース

Capacitive Coupling [3] Wired Wireless 2 Chips (Face-to-Face)

Over 3 Chips (Faced up/dn)

[1] ISSCC’04, Sony [2] ISSCC’01, MIT [3] ISSCC’03, Univ. Tokyo, Keio Univ. [4] ISSCC’04, Keio Univ.

Inductive Coupling [4]

Micro-Bump [1]

Inductive結合リンク

ISSCC 2006 (1Tb/s) VR Vbias + -Rxdata Rxclk Rxdatab Dl Dlb Txdata IT Tx/Rx VR Vbias + -Rxdata Rxclk Rxdatab Dl Dlb Txdata IT Tx/Rx

Digital CMOS Circuits Multi-layer Wires

ISSCC 2005 (200Gb/s) ISSCC 2004 (1Gb/s)

[4] ISSCC’04, Keio Univ. [9] ISSCC’05, Keio Univ.

[11] ISSCC’05, Hiroshima Univ.

T. Kuroda (59/70)

世界最高速 (1Tb/s) 、最小エネルギー (2.4pJ/b)

100G 1T Data Rate [b/s] 1G 10G Stanford (1ch) Stanford (1ch) NEC (1ch) Toshiba (4ch,4W) Rambus (26ch) NTT (16ch,8W) Hotrail (32ch) NEC (4ch,5W) NEC (21ch,3W) NEC (20ch,8W) TI (20ch,6W) Intel (32ch,15W) IBM,Sony, Toshiba (48ch,6W) Hitachi (1024ch,12W) NEC (21ch,3W) TI (20ch,6W) Speed-wall Power/Area-wall NEC (21ch,3W) ’96 ’98 ’00 ’02 ’04 ’06 Year TI (20ch,6W) Keio (1024ch,3W) Keio (195ch,1.2W) Keio (1ch,45mW) (1024ch) (195ch) (1ch) Keio Keio Keio Sony (1300 µ-bamp 1 10 100 1000 Year ’96 ’98 ’00 ’02 ’04 ’06 Toshiba NTT Hitachi NEC NEC Intel TI NEC TeraChip IBM,Sony, Toshiba ’’ ’’ ’ ’ ’ ’’

Power / Data Rate [mW/Gb/s]

= Energy / bit [pJ/bit]

世界最小 (1mm

2

_/Tb/s)

100 1k 10k 100k 10 1

Layout Area / Data Rate

[mm 2 /Tb/s] Year ’96 ’98 ’00 ’02 ’04 ’06 Sony µ-bump TI NEC Intel NEC NEC Hotrail Hitachi NTT Toshiba IBM,Sony, Toshiba Keio (1024ch) Keio (195ch) Keio (1ch) ■L-coupling

30µm pitch (incl. transceiver circuits) Thinner packaging (no solder bump)

■Micro-bump

60µm pitch

■TSV

50µm pitch (excl. transceiver circuits) Need additional area for circuits

Tx Rx Circuits TSV Si Subs_trate Inductor Circuits TSV Si Subs_trate Circuits TSV Si Subs_trate Circuits TSV Circuits TSV Si Subs_trate Inductor

T. Kuroda (61/70)

有線通信と同レベルの高信頼性通信 (BER<10

-13

₎

10-13 10-7 10-4 10-3 ∆T [ps]

Bit Error Rate

300 350 250 400 1Gb/s φ φ Data Tx Data Rx Rxdata Txdata 223_{-1 PRBS} Generator Txclk Clk Tx Clk Rx Error Counter ∆T Rxclk 1GHz Clock Timing Margin=150ps 10-11 10-5 10-6 10-8 10-9 10-10 10-12 ・Easy to synchronize

コストダウン効果

・ Circuit solution in standard CMOS:

no need for new process development no additional cost in manufacturing

・ Reduce chip size:

no peripheral circuits needed no ESD protection needed

T. Kuroda (63/70)

AC結合のメリット

・No need for level shifters under different V_DD’s

・No need for additional V_DD’s nor thick gate oxide transistors

・V_DD’s can change: in burn-in, dynamic voltage scaling

Rx Tx 1V 2V Txdata Rxdata Txdata 1V 2V 2V 2V Rxdata Chip2, V_DD=2V Chip1, V_DD=1V

最近の研究成果：最小エネルギー (0.14pJ/b)

Inductive µ-bump w/ interposer Wire Bonding 2mW 20mW 200mW HDTV H.264/AVC (23.1Gb/s) 1 10 100 1000 Energy Dissipation [pJ/b] Year ’96 ’98 ’00 ’02 ’04 ’06 Toshiba (350nm) NTT (250nm) Hitachi (250nm) NEC (250nm) NEC (130nm)Intel (180nm) TI (180nm) NEC (130nm) Keio (350nm) Keio (250nm) [2]_Keio (180nm) TeraChip (130nm) Rambus (90nm) Sun (350nm) [1]_SFT (180nm) Fujitsu (90nm) 0.1 This Work (180nm) This Work (90nm) ’07 ’05 ’03 ’01 ’99 ’97 „電力低減：2.8pJ/b -> 0.14pJ/b （1/20）

ISSCC 2007 Technology Directionsセッション採択

“A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping”

T. Kuroda (65/70)

最近の研究成果：パッケージ越しにデバッグ

Probe IC on FCB Inductors in FCB PCB glue Inductors in FCB Target LSI on PCB CLK TX RX PCB Target LSI (in SSOP pkg) Probe IC (transceiver) Flexible-Circuit-Board (FCB) To/From in-Circuit-Emulator On-chip inductors

[18] ISSCC’07, Keio Univ.

„通信距離増大：30mm -> 1.2mm （デバッグなど応用拡大の波及効果）

ISSCC 2007 Technology Directionsセッション採択

“An Attachable Wireless Chip Access Interface for Arbitrary Data Rate by Using Pulse-Based Inductive-Coupling through LSI Package”

Diameter: 1/α Chip Thickness: 1/α Turn: α0.8 Voltage: 1/α Transistor size: 1/α Constant Magnetic Field Constant Electric Field 1/α Diameter: 1/α Chip Thickness: 1/α Turn: α0.8 Voltage: 1/α Transistor size: 1/α Constant Magnetic Field Constant Electric Field 1/α 1/α

３次元のスケーリングシナリオ

Inductive Coupling Link (Communication)

Field Effect Transistor (Computation) [I] [x] [T] [V] [n] [t]~[CV/I] 1/α 1/α 1/α α0.5 1/α 1/α 1 Coil Diameter [D]~[1/x] 1/α [k] 1 [vRS/vRN] 1 [1/t] α [ItV] 1/α3 D1.6_{(I/t)] 1} [1/tD2_] α3 [1/D2_] α2 Current [I] Transistor Size [x] Chip Thickness [T]

Power Supply Voltage [V]

Coil Turn Number (Layer #) [n]

Circuit Delay Time [t]~[CV/I]

Self Inductance 1/α 1/α 1/α α0.8 1/α 1/α 1 [D]~[1/x] 1/α

Magnetic Coupling Coefficient [k] 1

Crosstalk [vRS/vRN] 1

Data Rate / Channel [1/t] α

Energy / Bit [ItV] 1/α3

Receive Signal [v[vRR]~[kn]~[kn22 t)] 1

Aggregated Data Rate / Area[1/tD2_] α3

Channel Number / Area [1/D2_] α2 1.6 [L]~[n2_{D ]} [L]~[n2_D [I] [x] [T] [V] [n] [t]~[CV/I] 1/α 1/α 1/α α0.5 1/α 1/α 1 Coil Diameter [D]~[1/x] 1/α [k] 1 [vRS/vRN] 1 [1/t] α [ItV] 1/α3 D1.6_{(I/t)] 1} [1/tD2_] α3 [1/D2_] α2 Current [I] Transistor Size [x] Chip Thickness [T]

Power Supply Voltage [V]

Coil Turn Number (Layer #) [n]

Circuit Delay Time [t]~[CV/I]

Self Inductance 1/α 1/α 1/α α0.8 1/α 1/α 1 [D]~[1/x] 1/α

Magnetic Coupling Coefficient [k] 1

Crosstalk [vRS/vRN] 1

Data Rate / Channel [1/t] α

Energy / Bit [ItV] 1/α3

Receive Signal [v[v[v[vRRRR]~[kn]~[kn]~[kn]~[kn2222 t)] 1

Aggregated Data Rate / Area[1/tD2_] α3

Channel Number / Area [1/D2_] α2 1.6 [L]~[n2_{D ]} [L]~[n2_D1.6 [L]~[n2_{D ]} [L]~[n2_D T. Kuroda, ESSCIRC’06 „３次元スケーリングシナリオ提唱（新しい指導原理） 電界一定のスケーリング（MOSFET：演算） 磁界一定のスケーリング（磁界チャネル：通信）

T. Kuroda (67/70)

LSIの無限の可能性

„ 集積度は３年で４倍 †2003年に3億トランジスタ （>日本人の人口） †2007年に76億トランジスタ（>世界の人口60億人） †2010年に300億トランジスタ （>人間の脳のニューロン140億本） „ LSIは想像を越えた進化を遂げ、未来社会、未来文明を創造していく。 LSIの持つ潜在を引き出し、未来文明の夢を形にしていくのがシステム LSIの研究の楽しさ。 „ 産業の米と称されながらも半導体産業の市場規模はまだGWPの 0.5% （自動車産業で3%） 。エレクトロニクス機器に対する半導体市場 の割合は20%弱である。半導体はR. NoyceやG. Mooreらがフェアチ ャイルド・セミコンダクターを作って50年足らずの新しい技術であり、市 場が十分に消化していない。たとえCMOSのスケーリングが減速しても 、半導体産業は今後も十分な経済的発展の余地がある。

“Optimism is an essential ingredient for innovation. How else can the individual welcome change over

security, adventure over staying in safe place?”

Robert Noyce

“The best way to predict the future is to invent it.”

Alan Kay

T. Kuroda (69/70)

新しい時代の要請

„ Know How -> Know What -> Know Who

z’80年代（Japan as No1.）：いかに作るかを知っている （職人）

z’90年代：何を作るべきかを知っている （ビジョナリ）

z今後：誰と協働すべきかを知っている （プロデューサ）

人脈回路を活かすことが大切

„ Device -> Circuit / System -> Business

zシステム設計力 (総合デザイン力)

zビジネス力 (商品企画提案力)

„ 大学の役割

システムLSIの課題と展望：まとめ

„ 課題と展望をデバイス、集積回路、応用とビジネスの視点から議論した。 „ 電力（リーク）の増大でCMOSのスケーリングが難しくなってきた。 „ 低電力設計のための１０の秘訣を紹介した。 „ コンピュータとコミュニケーションは更にダウンサイジングを続けて融合し コンシューマ用途（人間中心）に展開される。 „ 次はセンサネットなどユビキタスエレクトロニクスの時代である。 „ 低電力、短距離ワイヤレス、認識が重要な技術になる。 „ チップ間無線通信はSi貫通ビアと同等の性能を低コストに実現できる。 „ 課題の解決には、ビジネスから設計、デバイス技術までを含めた総合的 なイノベーションが必要であり、広範囲な学問と知識が求められる。 Know How（職人）やKnow What（ビジョナリ）と同様にKnow Who （プロデューサ）が今後は重要になる。