FPGA の自己動的再構成を利用したシステムの設計と開発

全文

(1)2007-SL DM-128 (20). IPSJ SIG Technical Reports. 2007/1/18. 1-1-1. T 356-8502 #3E»-fc C 3* Tf: *«( 2-1-15 E-mail: f {hori.y,hirofumi.sakane,k-toda} @aist.go.jp, [email protected]. Design and Implementation of Self Run-time Partial Reconfiguration System Yohei HORIf, Hiroyuki YOKOYAMAtt, Hirofumi SAKANEt, and Kenji TODA* f National Institute of Advanced Industrial Science and Technology Tsukuba Central 2,1-1-1 Umezono, Tsukuba-shi, Ibaraki 305-8568, Japan. ft KDDI R& D Laboratories, Inc.. 2-1-15 Ohara, Fujimino-shi, Saitama 356-8502, Japan. E-mail: f{hori.y,hirorumi.sakane,k-toda} @aist.go.jp, [email protected] Abstract. We describe a design approach and its application of an FPGA-based system that utilizes self run-time partial re. configuration. Some FPGAs can be reconfigured in a portion of their circuits while the other parts are working. However, the design flow of a partially reconfigurable circuit is quite complicated and misleading, and thus only few examples have been actually developed so far. This paper clarifies the detail design approach of self run-time partial reconfiguration system and. demonstrates its sample implementation of Digital Rights Management (DRM) mechanisms on a Xilinx FPGA. Key words. FPGA, Reconfigurable Computing, Run-time Partial Reconfiguration, Content Protection, Digital Rights Man. agement (DRM). (±1* to IField-Programmable Gate. V\. rfttt,. Array (FPGA) It,. 5¥, DPRIUS§. SifiWgP^Hflliig (Dynamic Partial Reconfiguration: DPR) <D. ff<£> CAD ^-. -115-.

(2) EA PR Lounge 3&. 5. EA. 2.1. PR Lounge â-. fpga cox. r. t Sr,. ial Reconfig. uration: PR) * v>5.. £. DPRtef&fd, Active Partial Reconfiguration ^ Run-time. 3.2. Partial Reconfiguration b t>$£\1£tl£. iztz,. . S&. ISE8.1i+spl. ftffif& (Self Reconfiguration) £ B^. 7*4 ^©Sirflli, ^ .5.. Z,. E. ISE8.2i+spl. h y#3. , ^-—f it ngdbuild, MAP, PAR, bitgen #<Da-e^K. mft. DPR W«H*#-f-5 FPGA Kit. f^^ Spartan f y-Xfc Virtex i/y-. 5.. r , ea. 2.2. . PianAhead^, 7vT77>, IBgEH,. y h PianAhead tt. EA PR Lounge fr 3.3. y y^^(D Spartan > V —Xb Virtex i^y-XT'fo 6.. I&3.1. x ^ y -X-^ Spartan. SelfDPR. , Virtex-4 *T*<0 Virtex. -Xb, Spartan ^y-X^*>5. Virtex-5(i, ifiÊAPR . Virtex-II/-IIPro/-IIProX/-4T*(t, PianAhead 3.1. Early Access PR . Spartan-. , PianAhead ^rfljfflLfc7. y -. K[6]^j&s. V\ Virtex/-E^Spartan/-II/-IIE"C(t, PianAhead ^^Jffli"6. Virtex ^y-X^. DPR HfS^frff tf>t&tr#lite, Early Access Partial Reconfig . Virtex */ V -XT'It,. uration (EA PR) design flow b mttlX^. (& I) : E-mail HJ: 5 Xilinx i: ©It©. 2006 ¥ 12 £ 13-15 0.. -116-.

(3) « All = floorplan, constrain, export, map, PAR, assemble.. Clock Region Boui. PRM\. '. Reconfig., Frame. Virtex-II Pro. Virtex-4. Hi. tzib<D Dynamic Reconfigurable Port (DRP). ~ h ris. DPR *fc Spartan is V -. Z.y ]) 3.5. DPRTii,. 3.4. ft 5. ^<Db%, to&nm&<Dn*bt£Z*i?*-A>* Partially Reconfigurable Module (PRM) t WXf, ^W^vâ-^. (TBUF). Partially Reconfigurable Re. , Virtex-II Pro VMb. Virtex-4 &&<&?'<<< XT*&tZ6. IBIStf^Wlf \t, Spartan i/ V —Xb Virtex-II Pro $.X*(D Virtex is V — Xfc&tf 5 PRR <D. Look-up Table (LUT)^. EA PR T*(ir (DMfaltft 9 fafrtlXXS 0 ,. fe Virtex-4. it). Virtex-4 "Ctt, *, narrow/wide <D [HCSUtf5 & <5. Narrow '*. ). $.tz, Virtex-4 [Z.. *■?? o<Dlffljgi\Z 2CLB, wide it 4CLB Xfo6 (HI 2). Wide. ^. /j:*3 Virtex-4 <D Digital Clock Manager (DCM) b Multi Gigabit Transceiver (MGT) (-It,. , PRR. -117-.

(4) m2. ICAP t Select MAP #- h (Dftfo ICAP. PRM. •. KEEPJHIERARCHY it?*y a V$: "yes" A^ "soft". •. AREA GROUP flflJ^J&iS^L, t^. ti. EAPRT*. 3.6. Internal Configuration Access Port. Spartan-3 7 7 ^ y &<fctf Virtex *> y —X(D FPGA Mte, 1*1 Internal Configuration Access Port (ICAP). , SelectMAP*—Kfc. AREA. 8bit SfctS 32bit ^^^1"^ r PRM. C^L, AREA GROUP Wte^tf 5. (I). AREA GROUP RANGE Um*m. (2) (3). L. AREA GROUP MODE ^J^T*. (4) (5). "RECONHG". -zw^ PRM(D-r—. 4.3. 4.1. . static.used fc.. (I/O,. /l', PRM, ^<^. y ?tf v V t, 1 4.4. fe static.used. •. , arcs.exclude <tV>. KEEP-HIERARCHY ^/v' a >& "yes" 75^ "soft" £. -118-.

(5) 5.1. î/XxAT*(t, PRM. (Content-. Specific Circuit: CSC),. minal Built-in Circuit: TBC) b PftS. if Self DPR Sr CSC Configuration. Controller. . CSCi:. |. | Screen Conlro^T I. DVI Formatter. I. (1) (2). (3). 5.2.2. H 4 (-v. (4). block size, 128-bit key) \Z.. 5.2. ^^^fBFf^tffa (Digital Rights Management: DRM) fcj&ffl t /c^J^î". [Hl^(- «t 6 i!5 ,. 5.2.1. FPGA (D Self DPR. i. -|i(tt2) (7) REX2 (REconfigurable Experimental equipment 2). REX2 tt, Virtex-n Pro XC2VP70 & 1. c FPGA. fc»«) PCI-X sj?- K (REX2 PCI-X),. -K. (REX2 DVI) fr. http://www.rexeon.com/. -119-. . AES (CBC mode, 128-bit.

(6) m [1] [2]. tf)|$fg,"{f^&$8CPSY2004-114) pp.55-60, 2004. H. Yokoyama, and K. Toda, "FPGA-based content protection system. for embedded consumer electronics " RTCSA, pp.502-7, 2005. [3]. Y. Hori, H. Yokoyama, and K. Toda, "Secure content distributing system based on run-time partial reconfiguration," FPL, pp.637-640, 2006.. fcayfy^ j%M i/^T^<D fcfa," ft ^t£# RECONF2006-34, 2006.. [5]. Xilinx, 'Two flows for partial reconfiguration: Module based or dif ference based," , Sept. 9, 2004 2004.. [6]. Xilinx, Development System Reference Guide,, for ISE8. li edition, 2005.. [7] [8]. Xilinx, PlanAhead User Guide, Release 8.2,, 2006. N. Dorairaj. E. Shiflet, and M. Goosman, "PlanAhead Software as a platform for partial reconfiguration " Xcell Journal, vol.55, pp.68-71, 2005.. 1. PlanAhead. d r.T?tt, PlanAhead ^fflV^fc. fob.. , DCM,. , EA PR. ISE8.1i+spl t PlanAhead 8.2.4. -1 <D<fc 5 l -1, PRM.2. 3 Q Export. I ;£$ PlanAhead. SSi £3 exportJ & £j export^ 8 irt PlanAhead. & %3 project.? 9 ici PRM P^PRMJ. , if -T y > * * FPGA O g &W}&}Wffl& (Self Dy. ^ PRM.2. namic Partial Reconfiguration:. ^ Static. H A-. 1.1. (1). Sffc^nsJ^hSrflsdH-*.. ::tft ^n^x. h <nWtffi& PR_example/PlanAhead «b L, £fft& project_l t. PR.example/Top/top.ngc Srlt^t-5. Self DPR £. ( 2). Netlist ^ y — *. Tools * = »-,. -120-.

(7) tSrtSw^^^^^^^ top.ngc. "V—7-/^ (Static, PRM/PRM_1)^]. I»« AM ■«■ 0 (MM OOUT.WRANfR). racentJIRfCONrjO Tux. mA-2. EXTORT.OS.CIOWREQCM. Sosbai. MOK. En». V«U. C.. iREOONFn. 3. MODE = RECONFIG. "New Pblock". "AG-static" t "f 6. Physical Hierarchy ^ II — \z., AG-static fc. BA-5. H AREA GROUP JRte#W!££*Lfc. PRM ©-=e— K. *.—frh "RECONHG" %WLfet%> (0A-5). r. , AREA GROUP MODE ftJ^Jf RECONFIG #K£ $ ( 5). Netlist y V —<D Primitives Workspace ±T?. (6). Ifcli,. ,, PR. ;*^-tf) *Tools-> Run Tel Script". -h,. ^(DRC),. (7) YTyf. ( 3). PR. "Tools->RunDRC"£»?-t-<5.. li, US 0 Q 0 -© O ■© "@ ■ 0 ••■© 0 © ^ "@ -© -O O O. NeUisty y-T. â—j5^ "Draw Pblock" ^rUtTt, Workspace _bT* PRM (D®S. HSritfc-t-5 (HI A- 4). Workspace ±"C^^ yy^L, "Select-^ Clock Region" hirZt, tvyfV — i? a s 5we,. . Physical Hierarchy ^ JJ — IZ. AG-PRM-l. , AREA GROPU RANGE ffl#toMS£$*i*.. Partial Reconfig ^l PRNM : Bus macro between static and PRM \& PRBD : Bus macro direction. ^ M ;YJ m ifl i«5 lid y y :^ I M y ^ 1. PRBO : Bus macro orientation inside PR block PRBN: Bus macro connectivity PRPN : Prohibited net through bus macro PRBL : Bus macro LOC PROP : Bus macro placement PRTP : TPSYNC for asynchronous bus macro PROL: Overlap with other PRM PRBG: BRAM grid for PRM PRUR: Uniform range PRCC : Global clock inside PR block PRGL : Glitching logic LOC above and below PRIL:IOLOCs PRGB : Glitching logic block above and below. PRSG : Static group check PRCL : Clock object LOC. HA-6. (8). "Files-. ExportFloorplan". /i-^li, r. r Tii PR^xample/Export/export.l i:i"5. Export mode X' "Partial Reconfig" #3g& ZtlXV ^-5 r. t &ffilfSL, Next. $r ft3i". Summary HI® (HI A- 7) T*. export floorplan mode -^tti. *7*^y*SjELVîSrffllBL"C Finish Sr^Pi". ( 9) ( 4). Physical Hierarchy yy-"C AG.PRM-1 «r 51^ L ,. Pblock Properties $M V K £ 0> Attribute ^:/ T?Jltt$r^^f. 5. "Define new attribute" T-T =*>-£#LT "MODE". -121-. tti^^fe^^/U^ export-1 i:, export. 1/static y^r^V<D PlanAhead (D/^—.

(8) Fborpim ffborpiio. * i rwe,iM94dô tMfcinsid.i.). • Sxpai fberplm mods b Partial Rocanf «. vl f%t to be nrer»i»J. M'-St ii:. [flR£COKF.H«h. ■■» <AIISUticlocicMadtilt*>. I3A-9. ( 3). 1.2. (1). "Tools— Run Partial Reconfig" trMfti~6 t, PR 7. i). ii). -9). r. Budgeting (h. (4). Static Logic Implementation (St^â-yKD PAR). iii). PR Block Implementation (PRM <O PAR). iv). Assemble (\?y\>7T -iVKZ>toJt). Physical Hierarchy y y -•? PRM <£> Pblock. PblockProperties ^^f^K. <Tools-^RunDRC"^lltT-f'5. ai^-^ttJfcfe, IS. PRM.1 ^>#î: Pttic, 31^ ^^- NUT "Build All" Sr , flow step <r>MM<r> 2 o»i PRM.1 irl^C. '{f&tlZ. PR Block Implementation fcii^L, PRM. V * MuWtTV^jOHMBf * (H A-8).. flow step (PB Block Implementation) fr. (5). exporLl 7*>V?\ZhZ>,. h y7°*i?zi.-/\s(D NGD. 10) %, PR.sxample/Export/export-2 \z =» fc°—1"-5.. glA-8. ( 2). PRflow^wif-K. Next ^ 3 0J¥ t, "Flip-flops or latches may be packed. into" t V^ 9 Jg@ t? "None" ^r^^y î"5. ^.^l(i, PRM <£>. (6). "Files— ExportFloorplan" fcUff-f 6. )fttl%<r>7*. !V?\&,. ( 3). Back -C flow step if®J-M5. £*-r yy^ 1 ofo r^fcT?**^,. ::ttt "Build All" if-aiix^. ZZX'U PR-example/Export/export-2 t i" 6. Export. mode -C "Partial Reconfig" #W*3*l/O *5 r. t $:i^L, Next. SrJPL, ( 7). (HI A- 8). Next £J¥irt Summary U®^^^, Finish ^r. $^(- Finish SrJfi". *Tools— Run Partial Reconfig" £ HfT-f -5. Flow step. t? "PR Block Implementation" £j!^L , PRM ÎEL < U ^ h (4). ,. export.l/merge. ( 8). Next ^r }f L, "Flip-flops or latches may be packed into". t V^ p^SST* "None" ^f oi^y ^ LT Finish &J¥L, PRM cOgB. static Jull.bit (PRM-1. ag.prm_l_cv_routed_partial.bit (PRM <D fy). ( 9). ag4)rm.l.blank.bit C/7V^â — A-) ( 1). Flow step T* "Assemble". mary @j®^?f|^Lr Finish «r}f L. \f y. 1.3. ft 5.. "File-> Save Project As" S: Hf? L ,. •. static Jull.bit (PRM-2 & $tt \B\&±fc<D7* - 9). "File-+ Update Netlist" % Mff't %>. "Replace a specific. •. ag-prm_2-cv_routed-partial.bit (PRM <O2h). module" #i§JR£tlT^5:: h£$mLX Next^r^fL, PRM_2. •. ag_prm_2_blank.bit tfjl/tî/x. —}V). PR_example/Project <t L, ^tif^r project_2 ( 2). -122-. . Sum.

(9)