SWITCHING FREQUENCY (Hz)

Analysis and Design of Quasi-

Square Wave Resonant Converters

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

What is Quasi-Square Wave Resonance ?

‰ MOSFET turns on when V

(t) reaches its minimum value.

¾ Minimize switching losses

¾ Improves the EMI signature

valley

Quasi-Resonant Operation

‰ In DCM, V_DS must drop from (V_IN + V_reflect) to V_IN

‰ Because of L_p-C_lump network Æ oscillations appear

‰ Oscillation half period:

V_IN + V_reflect

V_IN V_DS

Lp

Vin

SW Clump

Rload Cout

1 : N Vout

VDS Vin

x p lump

t = π L C

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

A Need to Limit the Switching Frequency

‰ In a self-oscillating QR, F

increases as the load decreases

‰ 2 methods to limit F

:

– Frequency clamp with frequency foldback – Changing valley with valley lockout

Higher losses at light load if F

is not limited

Frequency Foldback in QR Converters

‰ In light load, frequency increases and hits clamp

¾ Multiple valley jumps

¾

Second valley First valley QR mode

Changing Valley

‰ As the load decreases, the controller changes valley (1^st to 4^th valley in NCP1380)

‰ The controller stays locked in a valley until the output power changes significantly.

¾ No valley jumping noise

¾ Natural switching frequency limitation

0 10000 20000 30000 40000 50000 60000 70000 80000

0 10 20 30 40 50 60

OUTPUT POWER (W)

SWITCHING FREQUENCY (Hz)

1^st 2^nd

3^rd 4^th

VCO mode

QR operation

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

Calculating the QR Inductor

‰ Calculation steps:

1. Primary to secondary turns ratio

2. Primary and secondary peak current 3. Inductance value

4. Primary and secondary rms current

Turns Ratio Calculation

ds max, dss D

V = BV k

‰ Derate maximum MOSFET BV_dss:

‰ For a maximum bulk voltage, select the clamping voltage:

‰ Deduce turns ratio:

, ,

clamp ds max in max os

V = V − V − V

( )

c out f

s ps

p clamp

k V V N N

N V

= = +

BV_dss V_ds,max

V_clamp

V_bulk,max

15% derating V_os

V_reflect V_os: diode overshoot

k_D: derating factor

How to Choose k

‰ Choose k_c to equilibrate MOS conduction losses and clamping resistor losses.

1.2 1.5 1.8 2.1 2.4 2.7 3

0 1 2 3

600 V MOSFET

P_Rclamp

P_MOS,on@ V_in,min

P_SW,on@ V_in,max

Ploss(W)

k_c

1

out c

Rclamp leak

c

P k

P k

η k

= −

1.2 1.5 1.8 2.1 2.4 2.7 3

0 1 2 3

800 V MOSFET

P_Rclamp P_MOS,on@ V_in,min

P_SW,on @ V_in,max

Ploss(W)

k_c

2 ,

, , ,

1 2

dss D in max os

sw on in max OSS sw max

c

BV k V V

P V C F

k

− −

⎛ ⎞

= ⎜ + ⎟

⎝ ⎠

2

, 2

, , ,

4 1

3

out c

MOS on dson

in min in min dss D in max os

P k

P R

V V BV k V V

η

⎛ ⎞

= ⎜⎜⎝ + − − ⎟⎟⎠

P_tot ≈ 3.8 W

P_tot≈ 2.8 W

Primary Peak Current and Inductance

, ,

,

pri peak pri pri peak pri ps

sw pri lump

in min out f

I L I L N

T L C

V V V

π

= + +

‰

‰ ¹

out

2

P = L I F η

1 N

2 P C

F

P ^{⎛ ⎞} π

= + + 2 P

L =

t_on t_off

t_v I_pri,peak

t_on t_off

t_v 0

DCM

C_oss contribution alone.

RMS Current

‰ Calculate maximum duty-cycle at maximum P_out and minimum V_in:

‰ Deduce primary and secondary RMS current value:

, ,

3

max pri rms pri peak

I = I d

, ,

1 3

pri peak max

sec rms

ps

I d

I N

= −

,

, ,

pri peak pri

max sw min

in min

I L

d F

= V

I_pri,rms and I_sec,rms Losses calculation

Design Example

‰ Power supply specification:

– V_out = 19 V – P_out = 60 W

– F_sw,min = 45 kHz – 600 V MOSFET

– V_in = 85 ~ 265 Vrms

T1

. .

Vout

Gnd Vbulk

Design Example

, , ,

3.32 0.43 1.26

3 3

max

pri rms pri peak pri rms

I = I d = ⇒ I = A

,

, ,

1 3.32 1 0.43 3 0.25 3 5.8

pri peak max

sec rms sec rms

ps

I d

I I A

N

− −

= = ⇒ =

,

, ,

3.32 285

45 0.43

100

pri peak pri

max sw min max

in min

I L µ

d F k d

V

= = × ⇒ =

,

( ) 1.5 (19 0.8)

600 0.85 375 20 0.25

c out f

ps ps

Vdss D in max os

k V V

N N

B k V V

+ × +

= = ⇒ ≈

− − × − −

,

,

2 1 2

2 60 1 0.25 2 60 250 45 0.85 100 19.8 0.85 3.32

ps out lump sw

out pri peak

in,min out f

pri peak

N P C F

I P

V V V

p k

I A

η π η

π

⎛ ⎞

= ⎜⎜⎝ + + ⎟⎟⎠+

× ⎛ ⎞ × × ×

= ⎜⎝ + ⎟⎠+ ⇒ =

2 2

,

2 2 60

3.32 45 0.85 285

out

pri pri

pri peak sw

L P L µH

I F η k

= = × ⇒ =

× ×

‰ Based on equations from slides 11 to 14:

¾ Turns ratio:

¾ Peak current:

¾ Inductance:

¾ Max. duty-cycle:

¾ Primary rms current:

¾ Secondary rms current:

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

MOSFET

‰ TO220 package: R_θJA= 62 °C / W

‰ Ambient temperature: T_A = 50 °C, MOS junction temperature: T_J = 110 °C

R W T P T

JA A J

220

TO₋

= − ≈ 1

θ

2 2

,

1 0.6 1.3

TO 220 DSon120

pri RMS

R P

I

=

= = Ω

15 A, 600 V MOSFET

Power dissipated by TO-220 without heatsink:

MOS R_DS(on) @ T_J = 110 °C:

Assume we do not want a heatsink

!

MOS Heatsink

‰ We choose a 7 A, 600 V MOS: R_DS(on)120 = 1.2 Ω, R_DS(on)25 = 0.6 Ω

2 2

( ) ,

1.2 1.26 1.9

cond DS on 120 pri rms

P = R I = × = W

Thermal resistance of the heatsink:

110 50

2.5 1.6 27 / 1.9

J A

SA JC CS

cond

T T

R R R C W

θ

P

− −

= − − = − − = °

MOS conduction losses: ^Tj

Output Diode

‰ TO-220 package Æ power dissipation: 1 W

‰ MBR20200: V_T0 = 0.60 V, R_d = 20 mΩ

2 diode T 0 out d sec rms,

P = V I + R I

V_T0 R_d

V I

0.60 3.2 0.02 5.8

2.60

diode

P = × + × = W

110 50

2.0 1.6 2.6

J A

SA JC CS

cond

T T

R R R

θ

P

− −

= − − = − −

Diode conduction losses:

Heatsink:

19 /

R

≈ ° C W

Output Capacitor Selection

‰ Maximum output voltage ripple: V_ripple = 2%V_out =0.38 V

,

0.38 30 m 13.2

ripple Cout

sec peak

R V

≤ I = ≈ Ω

RMS current circulating in C_out:

2 2 2 2

, , 5.8 3.2 4.83 A

Cout RMS sec rms out

I = I − I = − ≈

Maximum ESR of output capacitor:

Two 1200-µF capacitors (3.2 Arms, 13 mΩ / capacitor) Losses in C_out:

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

Origin of Losses

. .

OUT

GND

Conduction and switching losses in MOSFET

Conduction losses in ESR of capacitor, diodes, clamp resistor, sense resistor

Switching Losses at Turn-On

3 2

, ,

2 3

out f

sw on in min DO O sw

ps

V V

P V C V F

N

⎛ + ⎞

= ⎜⎜⎝ − ⎟⎟⎠

2

, ,

1 2

out f

sw on OSS in min sw

ps

V V

P C V F

N

⎛ + ⎞

= ⎜⎜⎝ − ⎟⎟⎠

‰ Use the variablevariable capacitor for losses calculation:

2 19 0.8

100 200 25 45 3.6 mW

3 ⎛ 0.25 + ⎞ p k

= ⎜ − ⎟ =

⎝ ⎠

C_OSS

V_O C_DO

( )

1

OSS DS DO

DS O

C V C

V V

= +

‰ Traditional approach:

1 19 0.8 2

200 100 45 2 mW

2 p⎛ 0.25+ ⎞ k

= ⎜⎝ − ⎟⎠ =

Losses are negligible!

Bulk Capacitor Losses

arcsin

1 3

4

min peak c

line line

V

t V ms

F 2 Fπ

⎛ ⎞

⎜ ⎟

⎜ ⎟

⎝ ⎠

= − =

, ,

2 1

bulk rms in mean

3

line c

I I

= F t −

V_peak= 120 V

V_min= 70 V

Conduction time of diode bridge

0.70 2 1 1.3

I = − = A

‰ Power losses caused by ac current in the bulk capacitor ESR (350 mΩ)

2 bulk bulk bulk rms,

P = R I

C_bulk

Flyback I_in,mean I_bulk,rms

I_in,rms

I_in,ac

=

( )

, 2 2

2 , 2 0.7 0.35 70 1.04 640

2

in mean

diodes T 0 d d rms

P ⎛V I R I ⎞ m mW

= ⎜ + ⎟ = × × + × =

⎝ ⎠

Diode Bridge Losses

‰ KBU4K

‰ From datasheet curves: V_T0 = 0.70 V , R_d = 70 mΩ

‰ There are two diodes conducting at the same time.

‰ Two diodes always conduct during half a cycle:

‰ As two diodes always conduct, over a cycle, the bridge power is:

, ,

0.70 1.04

3 3 50 3

in mean d rms

line c

I I A

F t m

= = =

× ×

2 1.28

KBU 4K diodes

P = P = W

V_T0 R_d

V I

RCD Clamp Losses

‰ Power losses in clamping resistor:

‰ R_clamp can be calculated with:

clamp clamp Rclamp

R P V

2

=

V_clamp

V_bulk,max

V_os

2

2 _{clamp clamp} ^{out f}

ps clamp

sw leak peak

V V

V V

R N

F L I

⎛ + ⎞

⎜ − ⎟

⎜ ⎟

⎝ ⎠

=

2

19 0.8 2 120 120

0.25 7 7.3

45 2.8 3.32

clamp clamp

R k R k

k µ

⎛ + ⎞

× ⎜⎝ − ⎟⎠

= = Ω ⇒ = Ω

× ×

Inductor Losses

2 , ,

2 ,

,dc in mean pri ac pri ac

pri

Rpri R I R I

P = +

Core losses:

Determined from data provided by the manufacturer

2 2

, , ,

Rsec sec dc out sec ac sec ac

P = R I + R I

.

L_m .

L_leak1 L_leak2

R_c

R_pri R_sec

R_ac R_dc

Losses Summary for the 19 V / 60 W Adapter

11.14 Ploss = W

. .

OUT

GND

1.9 W

0.33 W 2.6 W

0.15 W 2 W

0.59 W 1.28 W

2.32 W

‰ Total losses:

Comparison with Real Adapter

‰ Efficiency measured after the EMI filter at 85 Vrms (120 Vdc)

η = 84.4%

P_in = 71.14 W P_out = 60 W

Calculated

η = 84.8%

P_in = 70.9 W P_out = 60.1 W

Measured

Vdrain

C5 1n C6

22p

C1 10n

C8

220p C11

4.7u

D5 1N4937

X5 TL431_G

C10 47n C9

220nF L1

X2 C18 100nF

C14

100u T1

. .

.

M1

R16

10 D3

1N4148

R3 47k

D2 MBR20200

C5a 1.2mF

L3 Vout 2.2u

C7 100uF

35V 25V

C5b 1.2mF

35V

C15 Gnd 2.2nF Type = Y1

R5 27k

R7 39k

R8 10k R9

1k

R15 1k R18

10k

SPP07N60

Gnd

Gnd

+ -

IN

X18 KBU4K

R26 0.47

R27 0.47

C20 100n R29

1k

Nps = 1 : 0.25 Npaux = 1 : 0.18 Lp=290 µH T1:

18 mH 2 A

Rx 10

R4 12k

R11 18k

1 2 3

4 5

8

6

7 D7

1N4148

Q1 BC857

C13 100u D1

1N4937

NCP1380

R1 1.3MEG

C3 100n

D4 1N967

X6 NTC R2

1k R6 340k

D6 1N4148

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

Synchronous Rectification

‰ High rms currents in secondary side Æ increased losses in the output diode.

‰ Replace the diode with a MOSFET featuring a very low R_DS(on).

Degraded standby power Increased efficiency

- +

. .

Vout

Gnd C_out

Q_sync

Synchronous Rectification Basics

‰ During (t

-t

), current flows into the body diode

‰ Minimize (t

-t

) duration to reduce body diode conduction.

. .

Vout

Gnd

R_load C_out

Q_sync

‰ Body diode conducts before the MOSFET is turned-on.

Losses in the Sync. Rect. Switch

2

( ) ,

ON DS on 120 sec rms

P = R I

Qsync ON Qdiode

P = P + P

Qdiode f out sw delay

P = V I F t

‰ Losses in the Sync. Rect. switch are mainly conduction losses.

Low if t_delay small

200 300

0 0.2 0.4 0.6 0.8 1

P_ON

P_Qdiode

V_in (V) P loss(W)

‰ MOSFET conduction losses

‰ Body diode conduction losses Body diode and MOS conduction losses for the 19 V/65 W adapter

Choosing the Sync. Rect. MOSFET

‰ Target around 1 W conduction losses in Sync. Rect. switch to avoid using an heatsink.

2 ,

1

DSon120

sec RMS

R W

= I

Universal mains

2 4

6 MBR20200

R_DSon120 = 30 mΩ R_DSon120 = 50 mΩ R_DSon120 = 70 mΩ

P loss(W)

60 W QR Sync. Rect. Calculations

2 2

( ) ,

30 5.8

1

ON DS on 120 sec rms ON

P R I m

P W

= = ×

=

0.7 3.2 45000 70 7

Qdiode f out sw delay Qdiode

P V I F t n

P mW

= = × × ×

=

1 0.007 1

Qsync

P = + ≈ W

Power loss saving: 1.6 W

‰ Total Sync. Rect switch losses:

‰ Losses into the MBR20200 diode: 2.6 W

‰ MOSFET losses:

‰ Body diode losses:

Using NCP4302

NCP4302

1

2

3 4 5

8

6 7

Sync DRV

Vcc

Trig

Dlyadj Gnd

Adjust:

- minimum on-time of the Sync. MOSFET - the minimum off-time of the Sync. MOSFET

Trigger input for CCM.

Connect it to Gnd if not used.

CS input connected to the drain of the MOSFET

TL431 Cathode TL431 V_REF input

Measured Efficiency with Sync. Rect.

‰ Efficiency measured after the EMI filter at 85 Vrms

η = 86.3%

P_in = 69.54 W P_out = 60 W

Calculated

η = 86.8%

P_in = 69.25 W P_out = 60.1 W

Measured

T1

. .

C3 47n C5ax

1.2mF

L7 Vout

2.2u

C19 100uF

35V 25V

C5bx 1.2mF

35V

Gnd

R17 27k

R19 39k

R20 10k R24

1k

R25 1k

Gnd

M2

R10 75

R31 10

R30 R33 110k

15k IRFS4320 D²PAK

1

2

3 4 5

8

6 7

Sync

DRV Vcc

Trig

Dlyadj X8 DIP4302 D8

1N4148

Gnd

Measured efficiency with Diode and Sync. Rect.

Standby power Sync. Rect. ^{Pin = 140 mW} P_in = 110 mW Diode

230 Vrms

Efficiency vs Output Power (60 W to 6 W)

80 81 82 83 84 85 86 87 88 89 90

5 15 25 35 45 55 65

Pout (W)

Efficiency (%)

Sync.Rect. 230 V Diode 230 V Sync.Rect 110 V Diode 110 V

Efficiency vs Output Power ( 1 W to 0.5 W)

56 58 60 62 64 66 68 70

0 0.2 0.4 0.6 0.8 1 1.2

Pout (W)

Efficiency (%)

Sync.Rect. 230 V Diode 230 V Sync.Rect 110 V Diode 110 V

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

Power Stage

‰ Borderline Conduction Mode Approximation.

‰ Neglect the high frequency Right Half Plane Zero (RHPZ)

( ) ¹

( ) ( )

( ) 1

2 2

( )

out IN load ESR out

FB sense out ps IN eq ESR out

V R R C s

v s

H s R V N V R R C s

v s

η α

⎛ + ⎞

= = + ⎜ ⎜ ⎝ + + ⎟ ⎟ ⎠

$

$

V_out

Gnd Controller

QR

R_ESR

R_load C_out

V_in

L_p

N_ps

2

out ps IN

eq load

out ps IN

V N V

R R

V N V

= +

+ Open loop transfer function of power stage

α: internal dividing ratio

The Optocoupler Pole

‰ Parasitic capacitance of optocoupler Î opto pole

‰ If f_optoclose to f_c (R_pullup high) Î phase margin degradation

Include the optocoupler pole in the power stage to calculate the phase shift at the crossover frequency.

1

opto 1

pullup opto

s = sR C +

( ) ( ⁽ )(

⁾ )

( ) 2 2 ( ) 1 1

ESR out IN load

sense out ps IN eq ESR out pullup opto

R C s H s V R

R V N V R R C s R C s

η α

= +

+ + + +

a

k c

e

R_pullup R_LED

C_opto

V_out V_dd

Optocoupler

characterization reveals a pole at 5 kHz

Compensating the QR with TL431

V_out

Gnd V_FB

R_LED

R_upper

R_lower V_dd

R_pullup

C_zero

C_pole

TL431

( ) 1 1

( ) CTR

( ) 1

pullup upper zero

FB R sR C

V s

G s V s R sR C sR C

⎛ + ⎞⎛ ⎞

= = − ⎜⎜⎝ ⎟⎜⎟⎜⎠⎝ + ⎟⎟⎠

Low frequency zero

Compensating the QR Converter

‰ Calculate f_c according to specified V_out undershoot for an output step load.

‰ Calculate R_LED to boost the gain at crossover.

2

c out

out out

f I

V C π

≈ Δ Δ

20 ) (

10

fc

H pullup LED

CTR R

R =

1 10 100 1 10× ³ 1 10× ⁴ 1 10× ⁵

−60

−30 0 30 60

)

f

|H(f)| (dB)

frequency (Hz)

f_c

K Factor Method

‰ Needed phase boost:

⎟ ⎠

⎜ ⎞

⎝

⎛ +

= 45

tan Boost 2 k

‰ Place the zero at frequency: f_c/k 1 2

zero

c upper

C f

R k

π

=

Boost PM PS = − − 90

1 10 100 1 10× ³ 1 10× ⁴ 1 10× ⁵

−180

−150

−120

−90

−60

−30 0

PS -101°

Arg[H(f)] (°)

frequency (Hz) Selected phase

margin

Power stage phase shift

Selected cross over frequency

Loop Compensation Example

1 1

38 47

2 66 800

2 12.5

zero zero

upper c

C nF C nF

f k

R k π

= π = = ⇒ =

× ×

tan 81 45 12.5 k = ⎛⎜⎝ 2 + ⎞⎟⎠

‰ Needed Phase Boost:

1 1

0.8 1

2 2 18 12.5 800

pole pole

pullup c

C nF C nF

R kf k

π π

= = = ⇒ =

× × ×

( ) 22

20 20

0.6 18 1 10

10

c

pullup

LED H f

R k

R =CTR ₋ = ≈ kΩ

‰ Calculated mid-band gain: 18.6 dB

90 70 ( 101) 90 81 Boost PM PS= − − = − − − = °

( ) ( ) G f H f

‰ Specification: Δ^V_out= 230 mV for Δ^I_out ^{= 2.8 A}

2.8 800

2 230 2.4 2

out

c c

out out

f I f Hz

V C π m m π

≈ Δ = ⇒ =

Δ × ×

10 100 1 10× ³ 1 10× ⁴ 1 10× ⁵

−60

−48

−36

−24

−12 0 12 24 36 48 60

−200

−160

−120

−80

−40 0 40 80 120 160 200

) a

Gain (dB) Phase (°)

PM

Frequency (Hz)

Measurement versus Calculation

‰ Power stage gain and phase

-- Measured gain -- Measured phase -- Calculated gain -- Calculated phase

Measurement versus Calculation

‰ Loop gain and phase

-- Measured gain -- Measured phase -- Calculated gain -- Calculated phase PM

Agenda

1. Quasi-Resonant (QR) Generalities 2. Limiting the free-running frequency 3. Calculating the QR inductor

4. Choosing the Power Components

5. Predicting the Losses of a QR Power Supply 6. Synchronous Rectification

7. Loop Compensation

8. NCP1380, our future QR controller

‰ Operating modes:

– QR current-mode with valley lockout for noise immunity – VCO mode in light load for improved efficiency

‰ Protections

– Over power protection – Soft-start

– Short circuit protection – Over voltage protection

– Over temperature protection – Brown-Out

NCP1380 Features

HV-bulk

Dovp ZCD / OPP

1 2 3

4 5

8

6 7

NCP1380 C/D

FB CS Rzcd1

GND

Rzcd2 Czcd Rstart

Ct

Cvcc Ct

DRV Vcc OVP/BO

Rbol Rbou

‰ Sampling date: end of January 09

‰ Mass production: end of Feb. 09

Control Topology Comparison

Smaller Normal BCM/DCM Best

Best Variable (min P_out at min F_sw) QR-FOT (NCP1380)

CCM/DCM BCM (Borderline)

CCM/DCM Operating mode

Normal Smaller

Normal EMI

Normal Larger

Normal Transformer size

Normal Best

Normal Full load

efficiencies

Valley jumping Best problem (noise) Max F_sw at min P_out Normal

(with skip mode or freq foldback) Light load

efficiencies

Variable (max power at max F_sw) Variable

(max power at min F_sw) Fixed

Frequency

Fixed On Time (FOT)(NCP1351) Quasi Resonant

Fixed F_sw

QR Mode with Valley Lockout

‰ As the load decreases, the controller changes valley (1^st to 4^th valley)

‰ The controller stays locked in a valley until the output power changes significantly.

¾ No valley jumping noise

¾ Natural switching frequency limitation

0 10000 20000 30000 40000 50000 60000 70000 80000

0 10 20 30 40 50 60

OUTPUT POWER (W)

SWITCHING FREQUENCY (Hz)

1^st 2^nd

3^rd 4^th

VCO mode

QR operation

VCO Mode

‰ Occurs when V_FB < 0.8 V (P_out decreasing) or V_FB < 1.6 V (P_out increasing)

‰ Fixed peak current (17.5% of I_pk,max), variable frequency set by the FB loop.

Constant peak current (17.5% of I_pk max) I_pk max

OPP: How does it Work?

‰ L_aux with flyback polarity swings to –NV_IN during the on time.

‰ Adjust amount of OPP voltage with R_opu // R_opl.

‰ V_CS,max = 0.8 V + V_OPP

100%

60%

370 Peak current

set point

V_IN(V)

ZCD/OPP

ESD protection Aux

Ropu

Ropl

1

CS

+ - Vth

DRV Tblank

leakage blanking

Demag

OPP

V_ILIMIT

IpFlag

Non dissipative OPP !

NCP1380 Versions

‰ 4 versions of NCP1380: A, B, C and D

X X

NCP1380 / X D

X X

NCP1380 / X C

X X

NCP1380 / X B

X X

NCP1380 / X A

Latched

Over current protection

Auto-Recovery

Over current protection

BO OVP

OTP

Short-Circuit Protection

‰ Internal 80-ms timer for short-circuit validation.

‰ Additional CS comparator with reduced LEB to detect winding short-circuit.

‰ V_CS(stop) = 1.5 * V_ILIMIT

ZCD/OPP

Laux CS

Rsense

LEB1 +

-

grand reset IpFlag

PWMreset

Up Down

TIMER

Reset FB/4

OPP

V_ILIMIT

+ - LEB2

V_CS(stop)

CsStop

DRV S

R Q Q

Stop controller

S

R Q Q

CS after LEB1 +

-

S Q

Vcc aux

management

latch

Vdd

fault

grand reset DRV

IpFlag +

-

PWMreset

Up Down

TIMER

Reset

VCCstop

FB/4

V_ILIMIT V_OPP+

VCC

CSstop

Short-Circuit Protection (A and C Versions)

‰ A and C versions: the fault is latched.

¾ V_CC is pulled down to 5 V and waits for ac removal.

SCR delatches when

I_CC< ICC_LATCH