保存型一括並列処理による高速なHMM出力確率計算・最尤推定回路の構成法
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(2) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report extracted from speech signal, etc. Feature vectors (stored in RAM). HMMs, where Ot = (ot1 , ot2 , ..., otP ), 1 ≤ t ≤ T . T is the number of input feature. words, etc.. vectors, and P is the dimension of the input feature vector. For an Ot , the output. HMM parameters (stored in ROM). probability of N -state left-to-right continuous HMM at the j-th state is given by log bj (Ot ) = ωj +. Register arrays. ...... Viterbi scorer. 1 ≤ j ≤ N, 1 ≤ t ≤ T,. (1). where ωj , σjp , and μjp are the factors of the Gaussian probability density function. The output probability computation circuit (Fig. 1) computes log bj (Ot ) based on. PEs. Eq. (1), where all HMM parameters ωj , σjp , and μjp are stored in ROM, and the input. Output probability of HMMs. Register arrays. σjp (otp − μjp )2 ,. p=1. Input Bus Output probability computation circuit. P . feature vectors are stored in RAM. The values of T, N, P , and the number of HMMs. PEs. V differ for each recognition system. For a recent isolated word recognition system1),2) , Score. T, N, P , and V are 86, 32, 38, and 800, respectively, and for another word recognition. Fig. 1 Basic structure of HMM-based recognition hardware.. system3) , T, N, P , and V are 89, 12, 16 and 100. For output probabilities log bj (Ot ), 1 ≤ j ≤ N, 1 ≤ t ≤ T , log-likelihood score log P ∗. 2.. HMM-based Recognition Systems. 2.1. HMM-based Recognition Hardware. is is given by log δ1 (j) = log πj + log bj (O1 ). (2). log δt (j) = min[log δt−1 (j − 1) + log aj−1,j , log δt−1 (j) + log aj,j ] + log bj (Ot ) (3). Figure 1 shows the basic structure of HMM-based recognition hardware1)–7) . The out-. log P ∗ = min [log δT (j)]. put probability computation circuit and Viterbi scorer work together as a recognition. (4). 1≤j≤N. engine. The inputs to the output probability computation circuit are feature vectors of. using Viterbi algorithm in HMM-based recognition hardware.1)–4) . A flowchart of out-. several dimensions and model parameters of HMMs. These values are stored in RAM. put probability computation and likelifood score computations is also shown in Fig. 2.. and ROM respectively. The RAM, ROM, output probability computation circuit and. Likelifood scores are obtained by N · T · V times the partial computation of log δt (j). Viterbi scorer interconnect via a single bus, and memory accesses are exclusive. The. calls. Partial computation of log bj (Ot ) performs 4 arithmetic operations, an addition,. output probability computation circuit outputs the results of the output probability. a subtraction and two multiplications for Eq. (1) and computes log bj (Ot ). Partial. computation of HMMs. The Viterbi scorer outputs likelihood score using the Viterbi. computation of log δt (j) performs 3 arithmetic operations, three additions for Eq. (2),. algorithm. In HMM-based recognition systems, the most time-consuming task is output. (3), (4), and computes log δT (j).. probability computations and likelihood score computations, and the output probability. 3.. computation circuit and the Viterbi scorer accelerate these computations. The output probability computation circuit and the Viterbi scorer have several register arrays and processing elements (P Es) for efficient high-speed parallel processing. 2.2. 3.1. Fast VLSI Architecture of Output Probability Computations and Viterbi Scorer with Fast Store-Based Block Parallel Processing VLSI Architecture of Viterbi Scorer for StoreBPP. Block parallel processing (BPP) for output probability computations and Viterbi. Output Probability Computation of HMMs and Likelihood Score. scorer was proposed as an efficient parallel processing method for word HMM-based. Computation with Viterbi Algorithm. speech recognition by Yoshizawa et al.1)–3) . In this method, the set of input feature. Let O1 , O2 , ..., and OT be a sequence of P -dimensional input feature vectors to. 2. c 2010 Information Processing Society of Japan .
(3) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report v=0 v=v+1 t=0 t=t+1 j=0 j=j+1 p=0 p=p+1. v=0 v=v+1. Loop D Loop C. Load μ j, p and σ j, p of HMM v to Regμ and Regσ (j=1, 2, ..., N, p=1, 2, ..., P, N .P cycles). Loop B. Load π j to Regδ (j=1, 2, ..., N, N/2 cycles). Loop A. Load a j,j to Reg a j, j (j=1, 2, ..., N, N/2 cycles). Partial computation of logb j (Ot ) p >P. Load a j-1,j to Reg a j-1, j (j=2, 3, ..., N, N/2 cycles). NO. YES. Load ωj to Regω (j=1, 2, ..., N, N/2 cycles) Loop C t=0 t=t+1 p=0 Loop A p=p+1. Partial computation of logδ t ( j) j >N YES. t >T YES. v >V. Loop D. NO NO. PE11 , j=1. NO. Load ot, p. YES. logb1 (Ot ). PE12 , j=2. logb2 (Ot ). Fig. 2 Flowchart of output probability computation and likelihood score computation.. p >P. vectors is called a block, and HMM parameters are effectively shared between differ-. YES PE2 2, j=2. PE2 1, j=1. ent input feature vectors in the computation. N -parallel computation is performed. logδt (1). logδt (2). by their BPP, and in recent years, two types of BPP are classified according to int >T. put data flow: stream-based block parallel processing (StreamBPP) and store-based. ... ... ... ... PE1N , j=N N-parallel logbN (O ) t computation. NO. ... ... ... ... PE2 N , j=N N-parallel logδj (N) computation NO. YES. block parallel processing (StoreBPP) by Nakamura et al.5) . A block can be seen as. v >W. NO. YES. a set of M (≤ T ) input feature vectors, whose elements are Ot ’s, 1 ≤ t ≤ M . M. Fig. 3 Flowchart of output probability computation and Viterbi scorer using StreamBPP.. vectors in T input feature vectors are processed in block. StoreBPP performs arith-. which computes log P ∗ by three additions for Eq. (2), (3) and (4). Loop B (Fig. 2) is. metic operations to locally stored input feature vectors, which are O1 , O2 , ..., and. expanded as shown in Fig. 3, and log b1 (Ot ), log b2 (Ot ), ..., and log bN (Ot ) are com-. OM . On the other hand, a block can also be seen as a M × P matrix whose elements. puted simultaneously with N P E1s. In addition to the N -state parallel computation,. . are ot p , 1 ≤ t ≤ M, 1 ≤ p ≤ P . StreamBPP performs arithmetic operations to an. the same HMM parameters μjp ’s, σjp ’s, and ωj ’s, 1 ≤ j ≤ N, 1 ≤ p ≤ P , are used. input stream, which is o11 , ..., o1P , o21 ..., o2P , ..., oM 1 ..., oM P .. repeatedly during Loop C in Fig. 3.. The BPP proposed. by Yoshizawa et al.1)–3) is classified as a StreamBPP for output probability compu5). tations and Viterbi scorer. The BPP proposed by by Nakamura et al.. A flowchart of the output probability computation with StoreBPP5) is shown in Fig. 4. The P E1s and P E2s in Figs. 4 and 3 are identical.. is classified. Loop C in Fig. 2 is partially ex-. as a StoreBPP for output probability computations. M/2-parallel computations are. panded in Fig. 4, and log bj (Ot +1 ), log bj (Ot +2 ), ..., and log bj (Ot +M/2 ) are computed. performed by the StoreBPP.. simultaneously with M/2 P E1s in Loop C1. In addition to the M/2-parallel computa-. A flowchart of the output probability computations and Viterbi scorer with the. tions, log bj (Ot +M/2+1 ), ..., and log bj (Ot +M ) are also computed with the same M/2. StreamBPP1)–3) is shown in Fig. 3. P E1j represents the j-th processing element, which. P E1s. In this double M/2-parallel computation, the same HMM parameters μjp and. computes log bj (Ot ) based on Eq. (1). P E2j represents the j-th processing element,. σjp are used twice, because the parameters are independent of t. In addition to the. 3. c 2010 Information Processing Society of Japan .
(4) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report v’max = 0 Loop D2 v’max = v’max + L t’max = 0 Loop C1 t’ = t’max , t’max = t’max + M , v’ = v’max _ L v = v’ + 1, j = 1, p = 1 Load Ot to RegO (t=t’+1,t’+2, ..., t’+M, M. P cycles) Load μ 1,1 , σ1,1 to Regμ, Regσ, respectively (2 cycles) v’ = v’ + 1 j = 0, v = v’ j=j+1 Load ω j to Regω (1 cycle) p=0 p=p+1 PE11 t=t’+1. v’max = 0 Loop D2 v’max = v’max + L t’max = 0 Loop C1 t’ = t’max , t’max = t’max + M , v’ = v’max _ L v = v’ + 1, j = 1, p = 1 Load Ot to RegO (t=t’+1,t’+2, ..., t’+M, M. P cycles) Load μ 1,1 , σ1,1 to Regμ, Regσ, respectively (2 cycles). Loop D1 Loop B. Load π j to Regδ j (1 cycle), when t’ == 1 Load a j,j to Reg a j, j (1 cycle). ... ... ... ... logb j (O t’+M/2) 2 times PE1M/2 , t=t’+M PE11 t=t’+M/2+1 PE12 t=t’+M/2+2 Load σ j, p+1 to Regσ logb j (O t’+M/2+1) logb j (O t’+M/2+2) M/2-parallel logb j (O t’+M ) computation Load μ j, p+1 to Regμ. logb j (O t’+1). logb j (O t’+2). p >P. Load a j-1,j to Reg a j-1, j (1 cycle), when j = 1 p=0 Loop A p=p+1. NO. PE1 M/2 t=t’+1. YES Copy Regω to Regδ. j >N. NO. p >P. NO. t’’1 max =t’+ M/P t’’ 1 = t’ Loop A’ t’’ 1 = t’’ 1 + 1 PE2 1. NO. t’’M/P max=t’+M t’’M/P = t’+M _ M/P Loop A’ t’’M/P = t’’ + 1 PE2 M/P. logδ t’’1( j _1) t’’>t’’ 1 max 1. .... _ . . . logδ t’’M/P ( j 1) NO. t’’ M/P >t’’ M/P. YES M/P -parallel computation. YES Copy Regω to Regδ. YES. v’max >V. logb j (O t’+1). PE1 M/2 t=t’+M/2+1. YES. t’max >T. PE1M/2 , t=t’+M/2. ... ... ... ... logb j (O t’+M/2) 2 times PE1M/2 , t=t’+M M/2-parallel Load σ j, p+1 to Regσ logb j (O t’+M/2+1) logb j (O t’+M ) computation Load μ j, p+1 to Regμ. NO. YES. v’ >v’max. Loop B. Load ω j to Regω (1 cycle) Loop A. PE1 M/2 , t=t’+M/2. PE12 t=t’+2. Loop D1. v’ = v’ + 1 j = 0, v = v’ j=j+1. max. NO. YES. .... NO. YES. j >N. Fig. 4 Flowchart of output probability computations using StoreBPP.. NO. YES. M/2-parallel computations, Loop D (Fig. 2) is divided into Loops D1 and D2 (Fig. 4).. v’ >v’max. The same feature vectors Ot +1 , ..., and Ot +M are used repeatedly during Loop D1.. t’max >T. For j-th HMM state, M output probabilities log bj (Ot ), t = t + 1, · · · , t + M , are. v’max >V. NO. YES NO. YES NO. YES. simultaneously obtained by Loop A. Different block parallel processing methods re-. Fig. 5 Flowchart of output probability computations and Viterbi scorer using StoreBPP.. quire different architectures of Viterbi scorer. Viterbi scorer which is suitable for the StoreBPP architecture is required for the development of well-optimized future HMM-. HMM state, log δt (j − 1) is computed with log δt −1 (j − 2) and log δt −1 (j − 1) dur-. based recognition systems.. ing in Loop A’. The intermediate result score log δt (j − 1) has to be computed during M/2-parallel computation of Loop A.. We present a pipelined VLSI architecture of Viterbi scorer for the StoreBPP. A flowchart of the output probability computation and Viterbi scorer with the StoreBPP is shown in Fig. 5. The P E1s and P E2s in Figs. 5, 4 and 3 are identical. Loop A. 3.2 Fast Store-based Block Parallel Processing (FastStoreBPP) and a. in Figs. 4 and Figs. 3 are also identical. Likelihood scores are computed by M/P Loop A’ with pipelined M/P P E2s based on Eq. (2), (3) and (4).. VLSI Architecture that Supports It. For (j − 1)-th. We demonstrate fast store-based block parallel processing (FastStoreBPP) for output. 4. c 2010 Information Processing Society of Japan .
(5) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report. v’max = 0 Loop D2 v’max = v’max + L t’max = 0 Loop C1 t’ = t’max , t’max = t’max + M , v’ = v’max _ L v = v’ + 1, j = 1, p = 1 Load Ot to RegO (t=t’+1,t’+2, ..., t’+M, M .P / 2cycles) Load μ 1,1 , σ1,1 to Regμ, Regσ, respectively (1 cycle). probability computations of HMMs and Viterbi scorer, and present a VLSI architecture that supports it. A flowchart of the output probability computation and Viterbi scorer with FastStoreBPP is shown in Fig. 6. Output probabilities are computed by Loop A with M P E1s. Likelihood scores are computed by M/P Loop A’ with pipelined M/P P E2s based on Eq. (2), (3) and (4). . In the StoreBPP(Fig. 5), the M cal-. v’ = v’ + 1 j = 0, v = v’ j=j+1. . culations of log bj (Ot ), t + 1 ≤ t ≤ t + M, were performed with 2 cycles, because it. Loop D1 Loop B. requires 1 cycle to read parameters which will be needed for the next calculation. In. Load ω j to Regω (1 cycle). Loop A(Fig. 5), the M calculations ware proceeded with M/2 P E1s, where M/2 was. Load π j to Regδ j (1 cycle), when t’ ==1. adequate number for the calcuations. The objective of the FastStoreBPP is efficient. Load a j,j to Reg a j, j (1 cycle). high-speed parallel processing of StoreBPP by a little extention of the bit length of the. Load a j-1,j to Reg a j-1, j (1 cycle), when j = 1. input bus(Fig. 2). By extending the input bus, it can read two parameters at once,. p=0 p=p+1. therefore M calculations of log bj (Ot ), t + 1 ≤ t ≤ t + M, were performed with 1. Loop A. t’’1 max =t’+ M/P t’’ 1 = t’ Loop A’ 1 = t’’ 1 + 1 t’’. cycles, and the M calculations are proceeded with M P E1s. where M is adequate . . . . . . . . . . . . PE1 M , t=t’+M Load μ j, p+1 to Regμ PE11 t=t’+1 logb j (O t’+1) M-parallel logb j (O t’+M ) Load σ j, p+1 to Regσ (1 cycle) computation. number for the calcuations. Our FastStoreBPP VLSI architecture for output probability computations and. PE2 1. Viterbi scorer is shown in Fig. 7, where the number of P E1s M ≤ P . The architecture. p >P. has two register arrays, two registers and M P E1s for output probability computations.. YES Copy Regω to Regδ. The architecture has four register arrays, two registers and one P E2s for likelihood. max. NO. YES. NO. YES. v’ >v’max. respectively. Regω stores HMM parameter ωj and intermediate results. Regδ stores. t’max >T. computed output probabilities for a Viterbi scorer. Regδl stores intermediate results. v’max >V. NO. YES NO. YES NO. YES. Regδj and Regδj−1 store intermediate results. Fig. 6 Flowchart of output probability computations and Viterbi scorer using FastStoreBPP architecture.. log δt (j) and log δt (j − 1), t + 1 ≤ t ≤ t + M, of v-th HMM. Regaj,j and Regaj−1,j store HMM parameters log aj,j and log aj−1,j of an HMM, respectively.. t’’ M/P >t’’ M/P .... Ot +1 , Ot +2 , ..., and Ot +M . Regμ and Regσ store HMM parameters −μjp , and σjp ,. log δt +M (j), 1 ≤ j ≤ N, of L HMMs.. NO. M/P -parallel computation. j >N. score computations based on Eq. (2), (3) and (4). RegO stores M input feature vectors. _ . . . logδ t’’M/P ( j 1). YES. NO. t’’M/P max=t’+M t’’M/P = t’+M _ M/P Loop A’ t’’M/P = t’’ + 1 PE2 M/P. logδ t’’1( j _1) t’’>t’’ 1 1 max. .... Each P E1. M P E1s, where the HMM parameters are shared by all P E1s. At the same time, an. consists of two adders and two multipliers, which are used for computing Eq. (1). The. HMM parameter μjp+1 and σjp+1 of v-th HMM are read from ROM and stored in Regμ. computation starts by reading M input feature vectors from RAM and storing them. and Regσ. In this M -parallel computation, the stored HMM parameters μ11 and σ11. The HMM parameters of v-th HMM are read from. are used once. In the next M -parallel computation, the stored HMM parameters μjp+1. to RegO in Loop C1 (Fig. 6).. ROM and stored in Regμ, Regσ, Regω, Regδj and Regaj,j , which are μ11 , σ11 , ω1 ,. and σjp+1 are used. M output probabilities log bj (Ot +1 ), ..., and log bj (Ot +M ) of v-th. π1 and a11 .. For the M stored input feature vectors Ot +1 , Ot +2 , ..., and Ot +M ,. HMM are obtained by Loop A (Fig. 6). The obtained results are copied from Regω to. M intermediate results are simultaneously computed with the stored μ11 and σ11 by. Regδ for starting the next computation, log bj+1 (Ot +1 ), ..., and log bj+1 (Ot +M ). The. 5. c 2010 Information Processing Society of Japan .
(6) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report. Viterbi scorer. ROM RAM μ, σ, ω O. Reg a j, j. Reg a j-1, j. 1. SEL. +. CMP t’==1. +. + +. ... .... .... Reg δ. ... .... +. N. M/ M/P. +. M ... .... .... SEL. .... .... SEL. L. Reg δ 1. M/P. ... .... N. M/P. M/ M/P. Reg δ l. .... +. ... .... .... CMP <. PE2 1. .... CMP t’==1. .... M. ... .... .... CMP < SEL. L .... +. SEL. ... .... .... .... M-parallel computation. ... .... PE M. +. M/ M/P. +. +. PE2 M/P. .... .... SEL. M. .... .... +. .... .... .... CMP <. PE2 1. .... .... .... CMP t’==1. .... ... .... .... Reg δ j. M. PE M-1 ... .... .... ... .... .... +. +. .... .... +. PE 2. Reg δ j-1. M. Reg ω. +. +. Reg δ j M/P. M/ M/P. Reg σ. PE 1. M. .... P. .... Reg μ. Reg a j-1, j. .... Reg a j, j. ... .... M/P. Reg δ j-1 M/P. M/ M/P. Reg δ j 1. M/ M/P. Output probability computation circuit. ot’,p. Reg a j-1, j. M/P. .... Reg δ j-1 1. M/ M/P. Viterbi scorer. Reg O. Reg a j, j. 1. Reg δ l. Reg δ M/P. PEs. Fig. 8 Pipelined Viterbi scorer for FastStoreBPP architecture (M/P ≥ 2).. Fig. 7 FastStoreBPP VLSI architecture (M/P = 1).. (Fig. 10) VLSI architecture1)–3) .. StoreBPP VLSI architecture for output probabil-. ity computations and Viterbi scorer is shown in Fig. 9, where the number of P E1s. results are fed to the Viterbi scorer. The M · N output probabilities of v-th HMM are obtained by Loop B (Fig. 6). M · N · L output probabilities of HMM v , v + 1, ...,and. M/2 ≤ P . The architecture has three register arrays, one register and M/2 P E1s for. v + L − 1 are obtained by Loop D1 (Fig. 6) with the same M input feature vectors. output probability computations, and has four register arrays, two registers, and one. Ot +1 , ..., and Ot +M .. P E2 for likelihood score computations based on Eq. (2), (3) and (4).. L is the number of HMMs whose output probabilities are. RegO stores. computed with the same input feature vectors during Loop D1. The M · N · L · T /M . M input feature vectors Ot +1 , ..., and Ot +M . Regμ and Regσ store HMM param-. output probabilities of HMM v , ..., and v + L − 1 are obtained by Loop C1, and. eters −μjp , and σjp , respectively. Regμ has space for storing −μjp and for prestoring. finally the M · N · L · T /M · V /L output probabilities of all HMMs are obtained by. −μj p+1 before the computation with μj p+1 during the computation using μjp . Regμ is. Loop D2 (Fig. 6). The intermediate score log δt +M (j − 1) has to be computed during. two times larger than Regσ. Regω stores HMM parameter ωj and intermediate results.. one M -parellel computation of Loop A. Consequently, we introduce pipelined Viterbi. Regδ stores computed output probabilities for a Viterbi scorer. Each P E1 consists of. scorer for the FastStoreBPP and StoreBPP. Our pipelined Viterbi scorer for the Fast-. two adders and two multipliers, which are used for computing Eq. (1). The architecture. StoreBPP (M > P ) and StoreBPP (M/2 > P ) is shown in Fig. 8. This viterbi scorer. works as shown in the flowchart Fig. 5.. consists of M/P -set of P E2s and register arrays for pipelined computation.. 4.. The StreamBPP (Fig. 10) architecture has two register arrays and N P E1s for output probability computations. The architecture has four register arrays and N P E2s for. Evaluation. likelihood score computations based on Eq. (2), (3) and (4), where P E21 is optimized for Eq. (2). The P E1s in Figs. 10, 9 and 7 are identical. The P E2s in Figs. 10, 9, 8 and. We compared the proposed FastStoreBPP, StoreBPP (Fig. 9) and StreamBPP. 6. c 2010 Information Processing Society of Japan .
(7) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report. 7 are identical. The StreamBPP architecture works as shown in the flowchart Fig. 3. Regμ and Regσ store HMM parameters −μjp and σjp , respectively, and Regω stores The computation starts by reading all. 2 · N · P + 4 · N HMM parameters of v-th HMM from ROM and storing them to Regμ,. Viterbi scorer. Regσ, Regω, Regδ, Regaj,j and Regaj−1,j in Loop D (Fig. 10). For stream input otp ,. Output probability computation circuit Reg a j, j. + .... .... CMP t’==1. +. M/2. +. .... +. .... M/2. PE2 1. ... .... +. CMP < SEL. +. +. Reg δ. block, respectively.. L. Reg δ l. Fig. 9 StoreBPP VLSI architecture (M/P = 2).. Table 2 shows the processing time for computing output probabilities of V HMMs and likelihood scores with the FastStoreBPP, StoreBPP and StreamBPP architectures,. ROM RAM μ, σ, ω O. where T and L are the number of input feature vectors and the number of HMMs whose output probabilities are computed with the same input feature vectors during Loop D1. Output probability computation circuit. PE1 1. registers and requires less processing time.. PE1 N. Compared with the FastStoreBPP (M = 29), the FastStoreBPP (M = 44) requires. +. +. +. ....... +. + .... pared with the StreamBPP and StoreBPP architectures, the FastStoreBPP has fewer. + ....... N-parallel computation PE1 N-1. used in the FastStoreBPP, StoreBPP and StreamBPP architectures are identical. Com-. +. Reg ω. ... SEL. +. CMP < SEL. + +. N-parallel computation. PE2 N-1 SEL. N. +. SEL. PE2 1. PE1 2. ....... ot,p. PE2’1. + +. ....... where L = 5 for the FastStoreBPP and StoreBPP architectures. The P E1s and P E2s. CMP t==1. + ....... FastStoreBPP, the other FastStoreBPP and one StoreBPP architectures, respectively,. N-1 Reg a j-1, j. Reg a j, j. CMP < SEL. N. ... .... .... ... ... .... We also assume that M = 44, M = 29 and M = 44 for one. .... without Viterbi scorer .. P. ... ... .... P. in a recent circuit design for isolated word recognition1),2) and StoreBPP architecture. N. N. .... ... .... T = 86, xμ = 8, xσ = 8, xf = 24, xo = 8,xa = 8, and V = 800—the same values used 5). Reg σ. N. ... .... Reg μ. ... .... Table 3 shows the register size, the processing time, and the number of P Es for computing output probabilities of 800 HMMs, where we assume that N = 32, P = 38,. Viterbi scorer. ... .... of Figs. 5 and 6, respectively.. Reg δ. N. + +. Fig. 10 StreamBPP VLSI architecture.. 7. N. +. M. PE1 M/2. the dimension of input feature vector, and the number of input feature vectors in a. SEL. ... .... .... .... M/2-parallel computation. PE1 M/2-1. ... .... ... .... N , P , and M are the number of HMM states,. .... chitectures, where xμ , xσ , xo , xa , and xf represent the bit length of μjp , σjp , otp , ajj ,. M/2. +. .... ot’,p. Reg δ j. M. PE1 2. +. Table 1 shows the register size of the FastStoreBPP, StoreBPP and StreamBPP arand the output of P E1, respectively.. ... .... N · T · V output probabilities of all HMMs are obtained by Loop D (Fig. 10).. +. M/2. .... ... .... of v-th HMM are obtained by Loop C (Fig. 10) with the same HMM parameters. The. Reg δ j-1. M. Reg ω. PE1 1. .... P. .... Reg O. .... output probabilities log b1 (Ot ), ..., log bN (Ot ) of the HMM are obtained by Loop A (Fig. 10). The obtained results are fed to a Viterbi scorer. N · T output probabilities. Reg a j-1, j. Reg σ .... Reg μ. ... .... the intermediate results are computed with stored HMM parameters by N P E1s. N. ... .... HMM parameter ωj and intermediate results.. ROM RAM μ, σ, ω O. c 2010 Information Processing Society of Japan .
(8) Vol.2010-SLDM-144 No.8 Vol.2010-EMB-16 No.8 Vol.2010-MBL-53 No.8 Vol.2010-UBI-25 No.8 2010/3/26. 情報処理学会研究報告 IPSJ SIG Technical Report 表1. FastStoreBPP (ours) StoreBPP (ours) StreamBPP. Register size.. data path delay.. Register size (bit) (P · M · xo + xμ + xσ + M · xf ) +(N · L + 2 · M + (M · (M/P + 1))/2) · xf + 2 · xa (P · M · xo + 2 · xμ + xσ + M · xf ) +(N · L + 2 · M + (M · (M/P + 1))/2) · xf + 2 · xa (N · P · xμ + N · P · xσ ) +(3 · N − 1) · xa + N · xf. 5.. Conclusions. We presented FastStoreBPP for output probability computations and Viterbi scorer and presented a new VLSI architecture. A reconfigurable architecture for both the StreamBPP and FastStoreBPP architectures are our future work.. 表 2 Processing times.. Acknowledgment. Processing time (cycles) FastStoreBPP (ours) StoreBPP (ours) StreamBPP. The authors would like to thank to Assistant Professor Shingo Yoshizawa of Hokkaido. V /L · {P · M/2 + (2 + P ) · L · N } · T /M V /L · {P · M + (4 + 2 · P ) · L · N } · T /M V · (N · P + 2 · N + P · T ). University.. 参. 考. 文. 献. 表 3 Evaluation of the FastStoreBPP, StoreBPP and StreamBPP performance.. FastStoreBPP (ours) FastStoreBPP (ours) StoreBPP (ours) StreamBPP. Register size (bit). Processing time (cycles). #P E1s. #P E2s. 22,000 15,808 22,008 21,288. 2,315,520 3,345,600 4,631,040 3,638,400. 44 (M=44) 29 (M=29) 22 (M=44) 32. 2 1 1 32. 1) S.Yoshizawa, N.Wada, N.Hayakawa and Y.Miyanaga : Scalable Architecture for Word HMM-based Speech Recognition and VLSI Implementation in CompleteSystem, IEEE TRANS. ON CIRCUITS AND SYST., Vol.53, No.1, pp.70–77 (2006). 2) S.Yoshizawa, N.Wada, N.Hayasaka and Y Miyanaga : Scalable Architecture for Word HMM-Based Speech Recognition, Proc. of ISCAS’04, pp.417-420 (2004). 3) S.Yoshizawa, Y.Miyanaga and N.Yoshida, : On a High-Speed HMM VLSI Module with Block Parallel Processing, IEICE TRANS. Fundamentals, Vol.J85-A, No.12, pp.1440-1450 (2002). 4) Y. Kim and H. Jeong : A Systoric FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition, IEICE TRANS.INF & SYST., Vol.E90-D, No.2, pp.562–568 (2007). 5) K.Nakamura, M.Yamamoto, K.Takagi and N.Takagi : A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with StoreBased Block Parallel Processing, IEICE TRANS.INF & SYST., Vol.E93-D, No.2, pp.300–305 (2010). 6) B. Mathew, A. Davis and Z. Fang, A Low-Power Accelerator for the SPHINX 3 Speech Recognition System, Proc. of Int’l Conf. on Compilers, Architecture and Synthesis for Embedded Systems, pp.210-219, 2003. 7) B.Mathew, A.Davis and A.Ibrahim, Perception Coprocessors for Embedded Systems, Proc. of ESTIMedia, pp.109-116, 2003. 8) X. Huang, F. Alleva, H. W. Hon, M. Y. Hwang, K. f. Lee and R. Rosenfeld, The SPHINX-II speech recognition system: an overview, Computer Speech and Language, vol.7(2), pp.137-148, 1992.. less processing time. Compared with the FastStoreBPP (M = 44), the FastStoreBPP (M = 29) has fewer registers and P Es. Compared with StreamBPP (Fig. 3) which requires N P E2s, the proposed architecture requires fewer P E2s because the value of M/P is at most 2 when using StoreBPP5) . From a VLSI architectural viewpoint, the evaluation results show that full performance of the StoreBPP architecture has been exploited by a little extention of the bit length of the bus in the FastStoreBPP. From a logic design viewpoint, the register arrays of the FastStoreBPP, StoreBPP and StreamBPP architectures are designed with Flip-Flops or on-chip multi-port memories of different sizes. Data paths are designed with identical P Es, but in a different number. The control paths of these architectures are designed, as shown in the flowcharts Figs. 3, 5 and 6. The data path delay is the same for the FastStoreBPP, StoreBPP and StreamBPP designs—equal to the delay time of one P E1. The delay times of control paths differ between the three, but the control path delay is small compared with the. 8. c 2010 Information Processing Society of Japan .
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