JAIST Repository: 金属/絶縁体トンネル接合を用いた超微細トランジスタに関する研究
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(2) Nano-Scale Metal Transistor Controlling Fowler-Nordheim Tunneling Currents through 16 nm Insulating Channel. Kouji Fujimaru School of Materials Science, Japan Advanced Institute of Science and Technology. (Supervised by Prof. Hideki Matsumura) Keywords:. The metal/insulator tunnel transistor (MITT), Fowler-Nordheim (F-N) tunneling currents, Photolithography, Anodic oxidation. A nano-scale transistor, the metal/insulator tunnel transistor (MITT) with a channel length of only 16 nm, is fabricated by conventional photolithography, and its operation is experimentally studied. The MITT consists of two metal electrodes, the insulating channel inserted laterally between these two electrodes and the third metal gate-electrode formed upon the gate insulator over the insulating channel. The Fowler-Nordheim (F-N) tunneling currents owing from one metal electrode to the other through the insulating channel are controlled by applying a voltage to the gate electrode. It is found that the MITT can be operated similarly to the semiconductor transistor, and the feasibility of a nano-scale metal transistor is demonstrated.. 1. Introduction. The conventional metal/oxide/semiconductor
(3) eld-e ect transistor (MOSFET) has physical and technological limits for sub-micron fabrication.[1] Thus, a nanometer scale transistor operating by a new principle is strongly desired to realize even higher package density of ultra large scale integrated circuits (ULSI). As one of the alternative candidates of MOSFET, the metal/insulator tunnel transistor (MITT), consisting of the metal and insulator without the semiconductor, has been proposed by our group in 1996.[2] The structure of MITT is brie y illustrated in Fig. 1. A nanometer-scale insulating region, named the tunnel insulator is formed between the metal source and drain electrodes. Just above the tunnel insulator, the gate electrode is formed upon the gate insulator. In the MITT, the Fowler-Nordheim (F-N) tunneling currents[3] owing through the tunnel insulator can be controlled by the gate voltage, just as in a conventional MOSFET, since the potential pro
(4) le near the interface between the metal source electrode and the tunnel insulator is distorted by the electric
(5) eld from the gate electrode. This is illustrated in Fig. 2, and a detailed explanation appears in reference.[2] The notation B and EF refer to the barrier height and the Fermi energy, respectively. When the gate electrode is positively biased toward the source electrode, the potential pro
(6) le at the source-insulator interface is distorted to make the pro
(7) le even sharper. It is known that F-N tunneling currents are strongly a ected by the barrier width through which electrons have to pass. Thus, the F-N tunneling currents can be increased by applying a positive gate bias. 1.
(8) The advantages of MITT are as follows: 1) Since the channel length can be reduced to around 15 nm by using F-N tunneling currents and also since the metal electrodes are directly connected to metal-signal lines, the MITT requires only a nano-scale area for transistor action. 2) An -ray soft error and radiation damage do not occur at all, since the MITT is made of metal and the insulator without semiconductor. 3) The MITT can be fabricated by a much simpler fabrication process than that of semiconductor devices because the formation of the p-n region is not necessary. 4) High speed operation of the order of pico-seconds is realized, since all signal lines and the electrodes are made of metal, and the drain currents also ow by tunneling phenomena. 5) The insulating channel of MITT is about ten times more tolerable in applying the electric
(9) eld than the semiconductor channel of MOSFET, since the insulator has about ten times larger dielectric strength than the semiconductor. This is useful for nano-scale devices. 6) In the MITT, it is easy to fabricate three-dimensional circuits by stacking the two-dimensional ones, since the MITT does not require to use crystalline materials in the fabrication process. Recently, a new technology using the tip of scanning tunnel microscopy has been reported to fabricate nanometer devices.[4,5] E. S. Snow et al.[6] succeeded in fabricating the MITT by using this technology based on our previous suggestion.[2] Their work is useful in checking the fundamental physics in device operation. However, the technology does not appear to be industrially acceptable. Thus, the fabrication of MITT by using conventional technology such as photolithography is strongly required. The purpose of this paper is to demonstrate the validity of our proposal regarding the MITT through its fabrication using industrially acceptable technology. The MITT with a channel length of 16 nm is fabricated by using only conventional photolithography and its operation is veri
(10) ed. The results clearly demonstrate that the size of transistor can be drastically minimized to the ten nanometer scale by using the MITT instead of semiconductor transistors. Moreover, the MITT can be fabricated by a simple method because the formation of a p-n region is not necessary.. 2 1. Experimental Procedure Fabrication Process. Figure 3 shows the present fabrication process of the MITT using conventional photolithography. The MITT is fabricated as follows[7,8]: 1) The gate insulator and a
(11) eld insulator are formed by thermal oxidation on an n-type silicon substrate as a gate electrode. 2) A Ti
(12) lm is evaporated on the gate insulator and the edge of the photoresist is aligned over the gate insulator by using photolithography. 3) The sidewall of Ti under the photoresist is steeply cut by the reactive ion etching (RIE) using chlorine (Cl2 ) and boron trichloride (BCl3 ) mixture. 4) The sidewall of Ti is anodized in ethyleneglycol dissolved ammonium-tetraborate. 5) A Ti
(13) lm is evaporated again, upon both the photoresist and the anodized TiOx. 6) A Ti
(14) lm above the photoresist is removed by lift-o technology, and
(15) nally the fabrication of MITT is completed. 2.
(16) The detailed conditions for fabrication of MITT is summarized in Table I. This fabrication process indicates the possibility of fabricating nano-scale MITT by using only conventional photolithography.. 3. Transistor Characteristics. The experimentally obtained transfer characteristics are demonstrated in Fig. 4 at 90 K because the drain currents due to the Poole-Frenkel currents are negligible. The structure of the transistor is described in the inset. In this particular case, the length of the tunnel insulator is 16 nm and the thickness of the gate insulator is 10 nm. This graph shows that the source-drain currents (Ids ) are controlled from 10012 A to 1007 A by the gate voltage (Vg ) changing from -4 V to +4 V. When Vg is smaller than -2.0 V, the F-N tunneling currents due to applying the drain voltage (Vds ) of 3 V are suppressed by the negative gate bias as described in Fig. 4. Of course, it is con
(17) rmed that the gate-leakage currents of the order of picoamperes have nothing to a ect on the change of Ids . Ids are clearly increased by changing the gate voltage in the scale of 105 enough to transfer the signal in the logic circuits. Figure 5 shows the I-V characteristics of MITT. It is found from this graph that Ids with some uctuations are slightly saturated by applying the gate voltage of 4.0 V. It is expected that these uctuations are caused by owing large Ids through the tunnel insulator. It is also found that the threshold voltage is around -1.0 V. It is surely con
(18) rmed from these results that the operation of MITT is similar to that of conventional MOSFET.. 4. Conclusion. It is concluded that the operation of the MITT is similar to that of conventional MOSFET. The MITT fabricated by the conventional photolithography is the promising candidate for the future switching transistor in ULSI.. Acknowledgments The author is grateful to Mr. T. Ono, Mr. R. Nagai, Mr. R. Sasajima, Mr. S. Hashioka and Mr. K. Fukushima for their useful experimental support and input.. 3.
(19) Table I: The condition of fabrication process. RIE condition Power of RIE 17.5 mW/cm2 Flow rate of Cl2 9.0 sccm Flow rate of BCl3 1.0 sccm Gas pressure 1.0 Pa Anodic oxidation Temperature 25 C pH 6.9. Width direction. Gate insulator. Gate 1 μm 5 nm. 21 nm. 2 nm. Metal line Source. Drain. Substrate. 15 nm. Tunnel insulator Figure 1.. Schematic view of structure of metal/insulator tunnel transistor (MITT).. EF. Positive gate vias. φB. EF. Source Shifted Effective potential thickness. Insulator. Figure 2.. φB. EF Drain. Energy band diagram of source/tunnel insulator/drain in the MITT.. 4.
(20) Field insulator. Resist. RIE etching. Ti. gate insulator. n-Si(100) Formation of gate insulator. Ti evaporation and photolithography. (a). Dry etching of half part of Ti. (b). TiOx. (c) Tunnel insulator Source Drain. Ti. Gate Lateral anodic oxidation of Ti (d). Figure 3.. Ti evaporation. Lift-off process. (e). (f). Fabrication process of MITT.. Vds = 3 V. 10–6. 90 K Ids (A). 10–8 L = 16 nm dg = 10 nm. 10–10. Source. 16 nm Drain. 30 nm. 10 nm 1 μm Gate. 10–12 –4. 0 Vg (V). 2. 4. Experimentally obtained transfer characteristics of MITT at 90 K.. [x10–7] 6 Ids (A). Figure 4.. –2. Vg = –1.0 V Vg = 2.0 V Vg = 4.0 V. 4. 2. 0 0. Figure 5.. 1. 2 Vds (V). 3. I-V characteristics of MITT.. 5.
(21) References [1] S. M. Sze: Semiconductor New York, 1985), 213.. Devices Physics and Technology, (John Wiley and Sons,. [2] K. Fujimaru and H. Matsumura: Jpn. J. Appl. Phys., 35 (1996) 2090. [3] R. H. Fowler and L. Nordheim: Proc. R. Soc. London, (1928) 173. [4] K. Matsumoto, M. Ishii, K. Segawa, Y. Oka, B. Vartanian and J. Harris: Ext. Abstr. Solid State Device and Materials, (1995) 192. [5] H. Sugimura, T. Uchida, N. Kitamura and H. Masuhara: J. Phys. Chem., 98 (1994) 4352. [6] E. S. Snow, P. M. Campbell, R. W. Rendell, et.al: Appl. Phys. Lett., 3071.. 72. (1998). [7] K. Yamanouchi, T. Meguro and K. Matsumoto: IEEE Trans. Ultrason., Ferroelectr. and Freq. Control, 39 (1992) 447. [8] K. Fujimaru, T. Ono, R. Nagai and H. Matsumura: Jpn. J. Appl. Phys., 36 (1997) 7786.. Publication list [1] K. Fujimaru, and H. Matsumura: Jpn. J. Appl. Phys.. ,2090 (1996).. 35. [2] K. Fujimaru, R. Nagai, T. Ono and H. Matsumura, Microprocesses and Nanotechnology '97, 9C-5-24. [3] K Fujimaru, T. Ono, R. Nagai and H. Matsumura: Jpn. J. Appl. Phys. (1997).. , 7786. 36. [4] K. Fujimaru, R. Sasajima and H. Matsumura, 56th Annual Device Research Conf. Dig., (1998) 44. [5] K. Fujimaru, R. Sasajima and H. Matsumura: J. Appl. Phys. (submitted). [6] R. Sasajima, K. Fujimaru and H. Matsumura: Appl. Phys. Lett. (submitted). Note: the thesis is written in Japanese. February 20, 1998. Copyright c 1999 by Kouji Fujimaru. 6.
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