⸘ߐࠇࠆߎߣ߇ᄙߊߥߞߡ߈ߡ޿ࠆ㧚 FPGA ߪ DSP ߦᲧ ߴ⋥ធࡂ࡯࠼࠙ࠚࠕࠍ᭴ᚑߔࠆߩߢ㧘㜞ㅦߥ࠺ࠖࠫ࠲࡞

(1)

1. はじめに

ޓ㜞ᐲᖱႎൻߩ൓޿ߪ㧘㓸Ⓧ࿁〝ߩᓸ⚦ൻ㧘㜞ㅦൻ㧘㜞 ᯏ⢻ൻ㧘ૐࠦࠬ࠻ൻࠍዉ߈㧘੹߹ߢࠕ࠽ࡠࠣ࿁〝ߢ⵾૞

ߒߡ޿ߚ࿁〝߇ DSP 㧔 Digital Signal Processor 㧕߿ FPGA 㧔 Field Programmable Gate Array 㧕╬ߢ⟎߈឵߃ࠄࠇߡ⸳

⸘ߐࠇࠆߎߣ߇ᄙߊߥߞߡ߈ߡ޿ࠆ㧚 FPGA ߪ DSP ߦᲧ ߴ⋥ធࡂ࡯࠼࠙ࠚࠕࠍ᭴ᚑߔࠆߩߢ㧘㜞ㅦߥ࠺ࠖࠫ࠲࡞

ା ภ ಣ ℂ ߇ น ⢻ ߣ ߥ ࠅ㧘 ߹ ߚ VHDL 㧔 Very high speed integrated circuit Hardware Description Language 㧕╬ߩ⸒

⺆ߦࠃࠅ ASIC㧔Application Specific Integrated Circuit㧕㐿

⊒߳ߩ㆏ࠍ㐿ߊ㧚ߘߩ৻ᣇߢⶄ㔀ߥᢙ୯Ṷ▚ࠍⴕ߁႐ว ߩࡊࡠࠣ࡜ࡓߦࠃࠆ⸳⸘ߩᨵエᕈߪ DSPߩ߶߁߇ఝࠇߡ

޿ࠆ߇㧘ㄭᐕ FPGA ߦࡊࡠ࠮࠶ࠨࠍ⚵ߺㄟߺಣℂߔࠆᣇ ᴺ߽㐿⊒ߐࠇߡ߈ߡ߅ࠅ㧘ߎߩ໧㗴߽⸃᳿ߒ߿ߔߊߥߞ ߡ߈ߡߪ޿ࠆ㧚ߐࠄߦ㧘 ASIC 㧘 FPGA 㧘 PROM ߣ AD ᄌ឵

ེ߿ DA ᄌ឵ེ╬ߩⶄᢙߩ࠴࠶ࡊࠍ 1 ࡄ࠶ࠤ࡯ࠫߦߒߚ SiP 㧔 System in Package 㧕ߩ㐿⊒߽น⢻ߣߥࠆ㧚๟ᵄᢙ೙

ᓮⵝ⟎ߩ࠺ࠖࠫ࠲࡞ൻߩ೑ὐߦߟ޿ߡߪߔߢߦ↥✚⎇⸘

㊂ᮡḰႎ๔ߩਛߢ⸥ߒߚ

¹⁾

㧚߹ߚ㧘ၮḰశ๟ᵄᢙ߇વࠊࠆ శ ࡈ ࠔ ࠗ ࡃ ࡯ ߩ 㐳 ߐ ೙ ᓮ ߩ ታ 㛎 ߢ ߪ㧘PSD㧔Phase Sensitive Detector㧕ࠍᄙbit ൻߒߚPFD㧔Phase Frequency Discriminator㧕ࠍ↪޿ࠆߎߣߦࠃࠅ㧘น೙ᓮ▸࿐߇ᐢ߇ࠅ㧘

Abstract

A Phase Frequency Discriminator (PFD) has been developed for atomic frequency standards and other frequency control systems using the state of the art digital technology. The PFD has been implemeted successfully in an exciter system for Sr+

microwave frequency standard.

ࠦࡅ࡯࡟ࡦ࠻㐳એ਄ߩశ〝Ꮕࠍߟߌߚ႐วߢ߽㧘శ〝㐳

೙ᓮࠍⴕ߁ߎߣ߇ߢ߈㧘߹ߚ 1 ᵄ㐳એਅߩ♖ᐲߢశ〝㐳 ࠍ቟ቯൻߢ߈ࠆ⢻ജ߇޽ࠆߎߣ߽⏕⹺ߐࠇߡ޿ࠆ

²⁾

㧚ߎߩ ࠃ߁ߥ⢛᥊߆ࠄ㧘㜞ㅦ࠺ࠖࠫ࠲࡞ାภಣℂߩశࡈࠔࠗࡃ

࡯ߩ㐳ߐ೙ᓮ㧘ේሶᤨ⸘ߩࠛࠠࠨࠗ࠲࡯ߩ૏⋧๟ᵄᢙᲧ セེ㧘ࠝࡈ࠮࠶࠻ࡠ࠶ࠢ࡟࡯ࠩࠪࠬ࠹ࡓ㧘శࠦࡓߩ࠺ࠖ

ࠫ࠲࡞ࠨ࡯ࡏ╬߳ߩㆡ↪ࠍ⋡ᜰߒ㧘 PFD ߩ㐿⊒ࠍⴕߞߚ㧚

߹ߚታ㓙ߦࡑࠗࠢࡠᵄߩࠛࠠࠨࠗ࠲࡯߳ PFD ߩㆡ↪ࠍ⹜

ߺߚߩߢႎ๔ߔࠆ㧚 2. 位相周波数比較器

ޓ৻⥸⊛ߦ⸒ࠊࠇߡ޿ࠆ૏⋧Ყセེߪ 2 ߟߩࠢࡠ࠶ࠢା

ภ㑆ߩ૏⋧Ꮕߦᔕߓߚᤨ㑆ߩ㑆㧘㔚࿶ࠍ಴ജߔࠆ㧚ାภ 㑆ߩ૏⋧Ꮕ߇৻๟ᦼએ਄ߕࠇߡߒ߹ߞߚ႐วߪ㧘ߘߩߕ ࠇࠍᬌ಴ߢ߈ߕ㧘৻๟ᦼࠬ࡝࠶ࡊߒߚାภࠍ಴ജߔࠆ㧚

૏⋧๟ᵄᢙᲧセེ PFD 㧔 Phase Frequency Discriminator 㧕ߪ㧘 2 ߟߩାภߩ૏⋧Ꮕ߇৻๟ᦼએ਄ߕࠇߡ߽㧘ߘߩߕࠇࠍᖱ ႎߣߒߡ⫾߃ࠆߩߢ㧘ାภߩ૏⋧ᬌ಴▸࿐ࠍᐢߍࠆߎߣ ߇ߢ߈ࠆ㧚૏⋧๟ᵄᢙᲧセᦼࠍ๟ᵄᢙ೙ᓮߦ↪޿ࠆߦߪ㧘

૏⋧ߩᲧセㇱಽߩઁߦ㧘౉ജᱜᒏᵄࠍ⍱ᒻᵄߦᄌ឵ߔࠆ

ࠦࡦࡄ࡟࡯࠲ㇱ㧘ߐࠄߦ૏⋧ߩ㆑޿ࠍ㔚࿶ߦᄌ឵ߔࠆ DA ᄌ឵ེࠍട߃ࠆߣଢ೑ߢ޽ࠆ㧚੹࿁㧘⵾૞ߒߚ࠺ࠖࠫ࠲

࡞ PFD ⵝ⟎ࠍ࿑1 ߦ㧘߹ߚࡏ࡯࠼ߩ࿁〝࿑ࠍઃ㍳ߦ␜ߔ㧚 FPGA ߣ㜞ㅦ DA ࠦࡦࡃ࡯࠲ߩធ⛯㧘 FPGA ߣ PC ߩࠗࡦ࠲

࡯ ࡈ ࠚ ࠗ ࠬ㧘 PROM ߣ FPGA ߩ ធ ⛯㧘 ࠦ ࡦ ࡄ ࡟ ࡯ ࠲ ߣ

૏⋧๟ᵄᢙᲧセེ⵾૞ߩᛛⴚ⾗ᢱ

ᐔ㊁ޓ⢒ *㧘⪤ᧄޓᙗ 㧘ᩉ↸ ᥙሶ 㧘ฎ⾐ ଻༑ **

㧔ᐔᚑ 20 ᐕ 8 ᦬ 4 ᣣฃℂ㧕

Technical Note for Phase Frequency Discriminator.

Iku HIRANO, Ken HAGIMOTO, Akiko YANAGIMACHI, Yasuki KOGA

* ⸘᷹ᮡḰ⎇ⓥㇱ㐷ޓᤨ㑆๟ᵄᢙ⑼ޓᵄ㐳ᮡḰ⎇ⓥቶ

** ⸘᷹ᮡḰ⎇ⓥㇱ㐷ޓᤨ㑆๟ᵄᢙ⑼ޓᤨ㑆ᮡḰ⎇ⓥቶ

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ߎߢ㧘ㄭᐕ᥉෸߇⋡ⷡߒ޿ FPGAߦ⺰ℂ࿁〝ࠍᦠ߈ㄟߺ㧘 Ṷ▚࿁〝ࠍ᭴ᚑߔࠆߎߣߦߒߚ㧚VHDL ߪࡂ࡯࠼࠙ࠚࠕ ࠍ⸥ㅀߔࠆ⸒⺆ߢ㧘⵾૞ߒߚ VHDL ࠦ࡯࠼ࠍ⺰ℂวᚑ࠷

࡯࡞ߦࠃߞߡ⺰ℂ࿁〝ߩ࠺࡯࠲ࠍ૞ࠅ㧘ߘࠇࠍ FPGA ߹ ߚߪ PROM ߦᦠ߈ㄟߺ FPGA ౝㇱߦ⺰ℂ࿁〝ࠍ᭴ᚑߔࠆ㧚

⵾૞ߒߚ VHDL ߩ࠰࡯ࠬࠦ࡯࠼ࠍઃ㍳ߦ␜ߔ㧚 FPGA ߩ 76 ⇟ pin ߣ 77 ⇟ pin ߆ࠄߘࠇߙࠇ౉ജߐࠇߚㅪ⛯⍱ᒻᵄࠍ clk1 ߣ clk2 ߣߒߡࡊࡠࠣ࡜ࡓߩಣℂߦ߈ߞ߆ߌߣߥࠆࠃ ߁ߦ process ᢥߩਛߦ process(clk1) ߣ⸥ㅀߔࠆ㧚ᰴߦ if ᢥ ߢclk1 ߩ୯߇ 1 ߢ޽ࠇ߫ᄌᢙQ1߇޽ࠆቯᢙ୯ߕߟჇടߔ ࠆࠃ߁ߦߔࠆ㧚clk2 ߦߟ޿ߡ߽ห᭽ߣߔࠆ㧚ߘߒߡ㧘74

⇟pin ߩ1 MHzߩ᳓᥏ࠢࡠ࠶ࠢ㧘߽ߒߊߪ 72⇟pin ߩᄖㇱ ߩࠢࡠ࠶ࠢ߆ࠄߩାภࠍclk3 ߣߒߡprocess ᢥߩਛߦ⸥ㅀ ߒߡ㧘ࠢࡠ࠶ࠢߏߣߦ Q1 ߣ Q2 ߩᏅࠍߣࠅ㧘 DA ᄌ឵ེ߳

ㅍࠆ㧚ߘߩߐ޿ Q1 ߣ Q2 ߩᏅ߇ 0 ߢ޽ࠆᤨߦ㧘 DA ᄌ឵ེ

ߩ಴ജ߇ 0 ߦߥࠆࠃ߁ㆡᒰߥᢙ୯ࠍട߃ߡࠝࡈ࠮࠶࠻⺞

▵ࠍߔࠆ㧚೙ᓮࡄ࡜ࡔ࡯࠲ߣߒߡ㧘ᄌᢙ Q1,Q2 ߩჇടಽ ߩ⺞▵㧘 Q1 ߣ Q2 ߩᏅߩାภࠍ಴ജߔࠆᤨ㑆㑆㓒ߩ⺞▵㧘

╬߇⠨߃ࠄࠇࠆ㧚 4. 性能試験

ޓFPGA ߣ ߒ ߡ SPARTAN3 ࠍ ૶ ↪ ߒ ߚ㧚SPARTAN3 ߪ

Xilinx ␠ߦࠃࠅ᳃↢ᯏེߥߤߩ㊂↥ຠ↪ߦࠦࠬ࠻ࠍ㊀ⷞߒ

ߡ㐿⊒ߐࠇߚ FPGA ߢ޽ࠅ㧘↥ᬺ⇇ߢߪᐢߊ૶ࠊࠇߡ޿ࠆ㧚 ߎߩߚ߼㧘㐿⊒ߔࠆߚ߼ߩᖱႎ߇Ყセ⊛౉ᚻߒ߿ߔ޿㧚 SPARTAN3 ߩ 72 ⇟ pin ߆ࠄ 2 MHz ⍱ᒻᵄ 0-3.3 V ߩࠢࡠ࠶

ࠢାภࠍ౉ജߒߡ㧘 76 ⇟ pin ߆ࠄ 14.5 MHz 77 ⇟ pin ߦߪ

15.0 MHz ߩ⍱ᒻᵄ߇౉ജߒߚᤨߩ಴ജାภࠍ࿑ 2 ߦ␜ߔ㧚

VHDL ࠦ࡯࠼ߩ Q1,Q2 ߩჇಽߪ 1 ߦ⸳ቯߔࠆ㧚㧔ߎߩᤨⵝ

⟎ߩ౉ജ┵ሶߦශടߐࠇߚᱜᒏᵄߩᝄ᏷ߪ 1.2Vp-p ߢ޽

ࠆ㧚㧕๟ᵄᢙᏅ߇ 500 kHz ࠃࠅ12 bit ߩDAࠦࡦࡃ࡯࠲ࠍ૶

↪ߒߡ޿ࠆߩߢ (1/500 kHz) 4096 = 8.192 msec ๟ᦼߩ ฝ਄߇ࠅߩᢳ✢߇ࠝࠪࡠߩ↹㕙ߦ⴫␜ߐࠇࠆ㧚ⵝ⟎ߩ౉

FPGAߩធ⛯╬ߩ࿁〝࿑㧘 VHDLߦࠃࠆࡊࡠࠣ࡜ࡓ㐿⊒ߪ㧘

ᄙߊߩᢥ₂ߣ૶߁࠺ࡃࠗࠬߩࠗࡦ࠲࡯ࡀ࠶࠻ᬌ⚝ߦࠃࠆ

⾗ᢱߩ࠳࠙ࡦࡠ࡯࠼ߐࠄߦ࠺ࡃࠗࠬࡔ࡯ࠞ߳ߩ໧޿วࠊ ߖ╬ߦࠃࠅ⸳⸘ࠍⴕߞߚ

²⁾

¹⁹⁾

㧚 PFD ߪ౉ജߩࠦࡦࡄ࡟࡯

࠲ TA8504F ߢ ౉ ജ ᵄ ᒻ ߇ Ꮕ േ ECL 㧔 Emitter-coupled logic 㧕಴ജߣߥࠅ -1.2 V ࠍਛᔃߦr 0.4 V ߩ⍱ᒻᵄߦᄌ឵

ߐࠇࠆ㧚 ECL ߩᦨᄢߩ․ᓽߪ㧘࠻࡜ࡦࠫࠬ࠲ࠍ㘻๺ߐߖ ߕߦ೑↪ߔࠆߚ߼㧘⁁ᘒᄌൻ߇㕖Ᏹߦ㜞ㅦߦⴕ߃ࠆὐߢ

޽ࠆ㧚ᓥߞߡ㧘ECL ߢ᭴ᚑߐࠇߚ࿁〝ߪ㕖Ᏹߦ㜞ㅦߦേ

૞ߔࠆ

²⁰⁾

㧚৻⥸ߦ಴࿁ߞߡ޿ࠆ ECL ࿁〝ߪ⽶ߩ㔚Ḯ㔚࿶

㧔-5.2V㧕ࠍଏ⛎ߐࠇ㧘⺰ℂ࡟ࡌ࡞߽ઁߩ⺰ℂ⚛ሶߣߪ⇣

ߥࠆ㧚ᓥߞߡ㧘ઁߩ TTL 㧔 Transistor-transistor-logic 㧕ߥ ߤߣ ECL ࠍ⚿วߔࠆߦߪ㧘ࠗࡦ࠲࡯ࡈࠚࠗࠬ࿁〝߇ᔅⷐ ߣߥࠅ㧘ߎߩߚ߼ߩᄌ឵⚛ሶߣߒߡ MC10H125 ࠍ૶↪ߒ ߚ㧚 MC10H12 ߪ ON Semiconductor ␠ߩࠛࡒ࠶࠲⚿วࡠࠫ

࠶ࠢߢ࠻࡜ࡦࠫࠬ࠲ߩ⫾Ⓧᤨ㑆ࠍߥߊߒ㜞ㅦേ૞ࠍน⢻

ߦߔࠆ㕖㘻๺ဳ࠺ࠖࠫ࠲࡞࡮ࡠࠫ࠶ࠢߢ޽ࠆ

¹²⁾

㧚 TTL ࡟ ࡌ࡞ߦᄌ឵ߐࠇߚାภߪ FPGA ߳౉ജߐࠇ㧘ࠢࡠ࠶ࠢା

ภߣߒߡ೑↪ߐࠇࠆ㧚VHDL ߦࠃࠅࠢࡠ࠶ࠢߏߣߦࠞ࠙

ࡦ࠻ߔࠆ࡟ࠫࠬ࠲ࠍ↪ᗧߒߡߎߩࠢࡠ࠶ࠢࠍᢙ߃ߡ޿ߊ㧚

ࠦࡦࡄ࡟࡯࠲ߣECL-TTL ᄌ឵⚛ሶࠍ 2 ୘↪ᗧߔࠆߎߣߦ ࠃࠅ 2 ߟߩ౉ജ๟ᵄᢙߩࠞ࠙ࡦ࠻ᢙ߆ࠄߘߩᏅࠍ᳞߼㧘 FPGA ߦ૶↪ߔࠆࠢࡠ࠶ࠢାภࠍၮḰߣߒߚ޽ࠆ৻ቯ๟

ᦼߏߣߦ FPGA 㧔 XC3S400PQBF 㧕߆ࠄ 12 bit ߩࡄ࡜࡟࡞

ାภߣߒߡ಴ജߐߖߡ㧘ߘߩାภࠍ DA ᄌ឵ེߢࠕ࠽ࡠࠣ

ାภߦᄌ឵ߐߖࠆߎߣߦࠃࠅ PFD ࠍ᭴ᚑߔࠆߎߣ߇ߢ߈ ࠆ㧚

3. VHDL プログラム

ޓ⺰ℂ࿁〝ࠍ᭴ᚑߔࠆߦߪࡠࠫ࠶ࠢIC ࠍ⚿✢ߒߡ޿ߊᣇ ᴺ߽޽ࠆ߇㧘 IC 㑆ߩ㈩✢߇ⶄ㔀ߦߥߞߚࠅ㧘ାภߩㆃࠇ㧔ࠬ

ࠠࡘ࡯㧕㧘ࠨࠗ࠭߇ᄢ߈ߊߥࠆߣ޿ߞߚ໧㗴߇↢ߓࠆ㧚ߘ

図 2ޓࠝࠪࡠࠬࠦ࡯ࡊߦ⴫␜ߐࠇߚ಴ജାภ

0.5 V/divޓޓޓޓޓޓޓ5 msec/div

図 1ޓPFD ࡏ࡯࠼

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ේሶߣࡑࠗࠢࡠᵄߩ⋧੕૞↪߆ࠄᬌ಴ߒߡ޿ࠆାภᒝᐲ ߇ࠊߕ߆ߦᄌൻߔࠆ㧚ߎߩᄌൻࠍࠨ࡯ࡏᯏ᭴ߦࠃࠅ10 MHz ╬ߩ᳓᥏⊒ᝄེ߳Ꮻㆶߔࠆߎߣߦࠃࠅ㧘ࡑࠗࠢࡠᵄ

ේሶ๟ᵄᢙᮡḰߪߟߊࠄࠇࠆ

²¹⁾

㧚࿑ 4 ߦ PFD 㧔࠺ࠖࠫ࠲

࡞૏⋧๟ᵄᢙᲧセེ㧕ࠍࡑࠗࠢࡠᵄࠛࠠࠨࠗ࠲࡯߳ㆡ↪

ߒߚ଀ࠍ␜ߔ㧚ߎߩࡑࠗࠢࡠᵄࠛࠠࠨࠗ࠲࡯ߪ㧘 Sr

⁺

ࠗࠝ

ࡦ࠻࡜࠶ࡊࠍ೑↪ߔࠆࡑࠗࠢࡠᵄ๟ᵄᢙᮡḰ᭴▽ߩߚ߼

ߦ⵾૞ߒߚ߽ߩߢ޽ࠆ㧚ၮḰ๟ᵄᢙߩ 10 MHz ߪࡈࠚ࡯࠭

ࡠ࠶ࠢ⺃㔚૕⊒ᝄེ (PLO) ߢ 499 ㅛ୚ߐࠇ 4990 MHz ߣߥ ࠆ㧚 ৻ ᣇ㧘⺃㔚 ૕ ⊒ ᝄ ེ DRO㧔Dielectric Resonant Oscillator㧕ߪ 5002 MHzㄭறߢ⊒ᝄߔࠆࠃ߁ߦ⸳ቯߔࠆ㧚 ߎߩ๟ᵄᢙߣ 4990 MHzߩ๟ᵄᢙߪ࠳ࡉ࡞ࡃ࡜ࡦࠬ࠼ࡒࠠ

ࠨߦ౉ജߐࠇ㧘ߘߩᏅߩ 12 MHz߇࠺ࠖࠫ࠲࡞૏⋧๟ᵄᢙ Ყセེ߳౉ജߐࠇࠆ㧚৻ᣇ㧘๟ᵄᢙࠪࡦ࠮ࠨࠗࠩ࡯߆ࠄ

ߪ 12 MHz ㄭறߩ๟ᵄᢙ߇หߓߊ࠺ࠖࠫ࠲࡞૏⋧๟ᵄᢙᲧ

セེ߳౉ജߐࠇࠆ㧚ߎࠇࠄ 2 ߟߩ๟ᵄᢙߩᏅߦ⋧ᒰߒߚ

ାภ߇⫾Ⓧߐࠇ࠺ࠖࠫ࠲࡞૏⋧๟ᵄᢙᲧセེ߆ࠄ಴ജߐ ࠇ㧘೙ᓮାภߣߒߡ⺃㔚૕⊒ାེ߳౉ജߐࠇࠆ㧚๟ᵄᢙ

ࠪࡦ࠮ࠨࠗࠩ࡯ߩ๟ᵄᢙࠍ 12.1 MHz ߦ⸳ቯߔࠆߣ DRO ߩ಴ജ๟ᵄᢙߪ 5002.1 MHzߣߥࠅ㧘࠳ࡉ࡞ࡃ࡜ࡦࠬ࠼ࡒ

ࠠࠨ߆ࠄߩ಴ജାภ߽ 12.1 MHzߣߥࠆ㧚PFD ߆ࠄߩ಴ജ

ାภࠍ DRO߳ශടߔࠆ㔚ሶ࿁〝ࠍઃ㍳ߦ␜ߔ㧚

ޓࠛࠠࠨࠗ࠲࡯ߩ 1 ⑽ᐔဋߩ๟ᵄᢙ቟ቯᐲߪ㧘ࠞ࠙ࡦ࠲

࡯ߢ⋥ធ 5002 MHz ߩ๟ᵄᢙࠍ⸘᷹ߔࠆߣ࿑ 5 ߦ␜ߔࠃ߁

ߦ 1 ⑽ᐔဋߢ 4 10

¹²

୯ࠍᓧߚ㧚ߎߩ୯ߪ㧘หߓߊࠞ࠙ࡦ

࠲࡯ߢ⋥ធ⸘᷹ߒߚ PLO න૕ߩ๟ᵄᢙ቟ቯᐲߣ߶߷หߓ ߢ޽ߞߚߎߣ߆ࠄ㧘ࠞ࠙ࡦ࠲࡯ߩ᷹ቯ㒢⇇ߢ޽ࠅ㧘߹ߚ

ࠪࡦ࠮ࠨࠗࠩ࡯ߩᄖㇱၮḰାภ 10 MHz ߽ࠞ࠙ࡦ࠲࡯ߩၮ

Ḱାภ 10 MHz ࠍ૶↪ߒߡ޿ࠆߚ߼㧘੹ᓟ PLO ߣ DRO ߩ

ࡆ࡯࠻࠳࠙ࡦߦࠃࠆ♖ኒ⸘᷹ߣ♖ኒߥᄖㇱၮḰାภࠍ૶

↪ߔࠆߎߣߦࠃࠅ㧘 PFD ߩᕈ⢻ߩㅊ᳞ࠍⴕߞߡ޿߈ߚ޿㧚

図 5ޓࠛࠠࠨࠗ࠲࡯ߩ๟ᵄᢙ቟ቯᐲ ജ┵ሶߩ౉ജ๟ᵄᢙࠍ౉ࠇᦧ߃ߚᤨߪฝਅ߇ࠅߩᢳ✢߇

⃻ࠇࠆ㧚หᦼࠍߣߞߚ2 บߩࡈࠔࡦ࡚ࠢࠪࡦࠫࠚࡀ࡟࡯

࠲HP33120㧘A2 บ߆ࠄ 10 MHz ߩାภࠍPFD ߦട߃ߚᤨ

ߩ಴ജߩ࠴ࡖ࡯࠻ࠍ࿑ 3ߦ␜ߔ㧚10 000 000 Hz ߣ10 000 010 Hzߩାภࠍട߃ߚᤨߦߪ಴ജାภ߇-1.0 V 㨪 0.9 V ߹ ߢᄌൻߒ㧘 410 ⑽๟ᦼߢᄌൻߔࠆ㧚 (1/10) 4096 = 409.6

⑽ޓࠃߞߡ࿑ 4 ߩ࠴ࡖ࡯࠻ߩ 1 ⑽㑆ߩ㔚࿶ߩᦨᄢᄌൻߪ 9 μ Vߢ޽ࠆߩߢ10Hz : 1.9 / 410 = x : 9 μ V / 1 ⑽ࠃࠅ4.3 10

⁶

Hz ߩ๟ᵄᢙߩਇ⏕߆ߐ߇⃻ࠇࠆߎߣߦߥࠆ㧚ࠃߞߡ

⏕ᐲߪ 4.3 10

¹³

ߣߥࠆ㧚ߒ߆ߒ㧘㔚࿶⸘ߩ⴫␜୯ߪ౉ജ ߇ߥ޿⁁ᘒߢ 1 ⑽㑆ߦ 2 㨪 20 μ V ⒟ᐲᄌേߒߡ޿ࠆߩߢ㧘 ⵝ⟎ߩ⏕ᐲߪ਄⸥▚಴୯ࠍ਄࿁ࠆ߽ߩߣ⠨߃ࠄࠇࠆ㧚 5. エキサイターへの適用

ޓࡑࠗࠢࡠᵄࠍ೑↪ߔࠆේሶ๟ᵄᢙᮡḰེߪ㧘ේሶߩၮ ᐩ⁁ᘒߩ⿥ᓸ⚦᭴ㅧ㑆ߩࡑࠗࠢࡠᵄߩ๟ᵄᢙࠍ೑↪ߔࠆ㧚

ࠛࠠࠨࠗ࠲࡯ߪ㧘߹ߕ 10 MHz ╬ߩ᳓᥏⊒ᝄེߩ๟ᵄᢙࠍ ၮḰߦߒߡ㧘ߘߩ๟ᵄᢙࠍᢙ⊖୚߆ࠄජ୚⒟ᐲㅛ୚ߒߚ ㅛ୚ࡑࠗࠢࡠᵄ๟ᵄᢙࠍ૞ࠆ㧚ߎߩ๟ᵄᢙߛߌߛߣၮḰ ߣߔࠆ⿥ᓸ⚦᭴ㅧ㑆ߩࡑࠗࠢࡠᵄߩ๟ᵄᢙߦᱜ⏕ߦߪว

⥌ߒߥ޿ߩߢ㧘ߐࠄߦߎߩ 10 MHz╬ࠍၮḰߣߒߡࠪࡦ࠮

ࠨࠗࠩ࡯ߦࠃࠅචᢙ MHz ߩ๟ᵄᢙࠍ⊒↢ߐߖ㧘ㅛ୚ࡑࠗ

ࠢࡠᵄ๟ᵄᢙߦട߃ࠆߎߣߦࠃࠅ㧘⿥ᓸ⚦᭴ㅧ㑆ߩࡑࠗ

ࠢࡠᵄߩ๟ᵄᢙࠍ૞ࠆⵝ⟎ߢ޽ࠆ㧚ࠪࡦ࠮ࠨࠗࠩ࡯ߩ๟

ᵄᢙࠍᢙ 10 mHz ᄌൻߐߖࠆߎߣߦࠃࠅ㧘ේሶߣ⋧੕૞↪

ߔࠆࡑࠗࠢࡠᵄߩ๟ᵄᢙ߽ᢙ 10 mHz ᄌൻߒ㧘ߘࠇߦࠃࠅ㧘

㪈㪅㪇㪜㪄㪈㪊㪈㪅㪇㪜㪄㪈㪉㪈㪅㪇㪜㪄㪈㪈㪈㪅㪇㪜㪄㪈㪇㪈㪅㪇㪜㪄㪇㪐㪈㪅㪇㪜㪄㪇㪏

㪇㪅㪇㪈㪇㪅㪈㪈㪈㪇

ᐔဋᤨ㑆㱠㩿㫊㪀

䉝䊤䊮 ᮡ Ḱ ஍ Ꮕ 㱟㫐㩿㱠㪀

図 4ޓPFD ߩࡑࠗࠢࡠᵄࠛࠠࠨࠗ࠲࡯߳ߩㆡ↪

図 3ޓPFD ߩ಴ജ㔚࿶ߩᤨ㑆ᄌൻ

(4)

5) http://direct.xilinx.com/bvdocs/userguides/ug332.pdf 6) http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/

fig26.htm

7) http://www.xilinx.com/support/sw_manuals/2_1i/

download/jtag.pdf

8) http://direct.xilinx.com/bvdocs/publications/j_ds099.pdf 9) ޟTD-BD-TS101 ೋ⚖✬࠹ࠠࠬ࠻ޠ㧘᧲੩ࠛ࡟ࠢ࠻ࡠࡦ

࠺ࡃࠗࠬᩣᑼળ␠㧘2004

10) h t t p : / / j a p a n . x i l i n x . c o m / s u p p o r t / c l e a r e x p r e s s / websupport.htm

11) http://www.tij.co.jp/jsc/docs/pic/pichome.htm

12) http://www.onsemi.com/pub/Collateral/MC10H125-D.

PDF

13) http://focus.tij.co.jp/jp/docs/prod/folders/print/dac902.

html

14) http://www.ortodoxism.ro/datasheets/toshiba/4106.pdf 15) http://direct.xilinx.com/bvdocs/publications/j-ds123.pdf 16) http://japan.xilinx.com/support/documentation/data_

sheets/j_ds123.pdf

17) http://focus.tij.co.jp/jp/lit/ds/symlink/opa690.pdf 18) http://japan.xilinx.com/support/answers/3418.htm 19) http://japan.xilinx.com/support/programr/files/0380507.

pdf

20) http://ja.wikipedia.org/wiki/%E3%82%A8%E3%83%9F

%E3%83%83%E3%82%BF%E7%B5%90%E5%90%88%

E8%AB%96%E7%90%86

21) Y. Koga, C. McNeilage, J. H. Searls, S. Ohshima,: ̌A Microwave Exciter for Cs Frequency Standards Based on a Sapphire-Loaded Cavity,̍ IEEE Trans. Ultrasonics, Ferroelectrics, Frequency Control., vol.48, no. 1, pp.1- 5,Jan,2001.

22) http://japan.xilinx.com/direct/ise7_tutorials/j_ise7tut.pdf 6. むすび

ޓ㜞ㅦ࠺ࠖࠫ࠲࡞ାภಣℂߩߚ߼ߩPFDߩ㐿⊒ࠍⴕߞߚ㧚

߹ߚታ㓙ߦࡑࠗࠢࡠᵄߩࠛࠠࠨࠗ࠲࡯߳ߩㆡ↪ࠍ⹜ߺߚ㧚

⃻࿷㧘᷹ቯⵝ⟎ߩ೙㒢߆ࠄ PFD ߩ๟ᵄᢙ቟ቯᐲߩ㒢⇇୯ ߣࠛࠠࠨࠗ࠲࡯ߩ๟ᵄᢙ቟ቯᐲߩ㒢⇇୯ࠍ▚಴ߢ߈ߥ޿

߇㧘੹ᓟ㧘 PLO ߣ DRO ߩࡆ࡯࠻࠳࠙ࡦߦࠃࠆ♖ኒ⸘᷹ߣ

♖ኒߥᄖㇱၮḰାภࠍ૶↪ߔࠆߎߣߦࠃࠅ㧘 PFD ߩᕈ⢻

ߩㅊ᳞ࠍⴕߞߡ޿߈ߚ޿㧚 7. 謝辞

ޓᧄ⎇ⓥࠍㅴ߼ࠆߦ޽ߚࠅ㧘㔚᳇ㅢାᄢቇ㧔⃻JAXA㧕ߩ

૒⮮ᵗᐔ᳁ߦߪ㔚ሶ࿁〝ߩࠦࡦࡄ࡟࡯࠲ㇱಽߣ PLD ߩ VHDL ࡊࡠࠣ࡜ࡓߦߟ޿ߡ⾆㊀ߥ⍮⼂ࠍᢎ߃ߡ㗂߈߹ߒ ߚ㧚⸘᷹ᮡḰ⎇ⓥㇱ㐷ߩᄢ⧣ᢕඳ჻㧔೨ᵄ㐳ᮡḰ⎇ⓥቶ㐳㧕 ߦߪ PFD ߩ㐿⊒ߦߟ޿ߡߩ⚫੺ࠍ㗂߈߹ߒߚ㧚⸘᷹ᮡḰ

⎇ⓥㇱ㐷ߩ੹ᳯℂੱᤨ㑆๟ᵄᢙ⑼㐳ߦߪ㧘ᧄႎ๔ᦠࠍ߹

ߣ߼ࠆߦ޽ߚࠅ㧘ᄙᄢߥࠆߏᜰዉࠍ⾦ࠅ߹ߒߚ㧚ߎߎߦ

ෘߊ߅␞↳ߒ਄ߍ߹ߔ㧚参考文献

1) ᐔ㊁ ⢒㧘⍹Ꮉ ⚐ : ޟ࠺ࠖࠫ࠲࡞ାภಣℂᛛⴚߦࠃࠆ

࡛࠙⚛቟ቯൻ He-Ne ࡟࡯ࠩߩ๟ᵄᢙ೙ᓮޠ㧘↥✚⎇⸘㊂

ᮡḰႎ๔㧘 6, 3, pp. 141-144 (2007-9)

2) ૒⮮ᵗᐔ : ޟశࡈࠔࠗࡃ࡯ࠍ↪޿ߚࡒ࡝ᵄၮḰାภ㈩

ାࠪࠬ࠹ࡓߩ㐿⊒ޠ㧘㔚᳇ㅢାᄢቇୃ჻⺰ᢥ (2007-3) 3) ↰ਛ⦟ᐔ : ޟ㜞ㅦࠕ࠽ࡠࠣ಴ജ࿁〝ޠ㧘࠺ࠩࠗࡦ࠙ࠚ

࡯ࡉࡑࠟࠫࡦ㧘AUG. 2005. pp. 50-51

4) ޟFPGA ࠻࡟࡯࠾ࡦࠣࠠ࠶࠻ TD-BD-TS101ޠ㧘᧲੩ࠛ

࡟ࠢ࠻ࡠࡦ࠺ࡃࠗࠬᩣᑼળ␠㧘2005

(5)

ઃ㍳

๟ ᵄ ᢙ ౉ ജ ㇱ ߣ ࠢ ࡠ ࠶ ࠢ ౉ ജ ㇱ ޕ ౉ ജ ߩ ࠦ ࡦ ࡄ ࡟ ࡯ ࠲

TA8504F

ߢ ౉ ജ ᵄ ᒻ ߇ Ꮕ േ

ECL( Emitter-coupled logic)಴ജߣߥࠅ -1.2V

ࠍਛᔃߦr0.4 V ߩ⍱ᒻᵄߦᄌ឵ߐࠇࠆޕ

ECL

߆ࠄTTL ߎߩߚ߼ߩᄌ឵⚛ሶߣߒߡ

MC10H125

ࠍ૶↪ߒߚޕTTL ࡟ࡌ࡞ߦᄌ឵ߐࠇߚାภߪ

FPGA

߳౉ജߐ ࠇޔࠢࡠ࠶ࠢାภߣߒߡ೑↪ߐࠇࠆޕ

FPGA

ߪ74 ⇟pin ߆ࠄ

1 MHz

ߩࠢࡠ࠶ࠢࠍขࠅ౉ࠇߡDA ࠦࡦ ࡃ࡯࠲ߦࠢࡠ࠶ࠢࠍㅍࠆ߇ޔ72⇟

߆ࠄᄖㇱߩࠢࡠ࠶ࠢߢ߽േ૞ߔࠆၮ᧼᭴ㅧߣߒߚޕ

0.1u

49.9 0.1u

0.1u 0.1u

-5.2 V TA8504F

1 GND1 2 IN+

IN- 3 4 VEE

NC 5 OUT 6 OUT 7 GND2 8

TA8504F 1 GND1

IN+

2 3 IN- 4 VEE

NC 5 OUT 6 OUT 7 GND2 8 49.9

5.0 V

-5.2 V -5 .2V BNC

1

2

0.1u 0.1u

0.1u

0.1u BNC

1

2

-1.67 V

5 V

XC3S400PQ208BF IO_L19P_7 7

IO_L31P_5/D5 72

IO_L31N_5/D4 74

IO_L32P_5/GCLK2 76

IO_L32N_5/GCLK3 77

MC10H125 VBB 1 2 Ain 3 Ain 4 Aout 5 Bout Bin 6 7 Bin 8 VEE

VCCCinCin 91011 Cout 12 DoutDinDin 131415 GND 16

1k

33k -2 V

-2 V

33k

-2 V 1k 49.9

49.9

49.9 49.9 0.1u

0.01u 0.1u

0.1u

SKPEAA 1 BNC

2

KCJXO5-1.000C51CS0

IN 1

OUT 3

GND2

DAᄌ឵ㇱޕ૶↪ߒߚDAC902

ߪ12 bit 165Msps ߩ㜞ㅦ

DA

ࠦࡦࡃ࡯࠲ߢ޽ࠆޕ㜞ㅦߩࠬࠗ࠶࠴ࡦࠣ

ߣᄌ឵ࠍታ⃻ߔࠆߚ߼㔚ᵹ೙ᓮࠍ↪޿ߡ߅ࠅޔ

22⇟pin

ߣ

21⇟pin߆ࠄᏅേߩ㔚ᵹାภ߇಴ജߐࠇࠆޕ FPGA

߆ࠄ಴ജߐࠇߚାภࠍCode ߣߔࠆߣ22⇟

߆ࠄ19.84(Code/4096) mAޔ

21

⇟pin ߆ࠄߪ

19.84((4095-Code)/4096) mA

ߩ㔚ᵹ߇಴ജߐࠇࠆޕߎߩᏅേାภࠍ⽶⩄ᛶ᛫ߦࠃࠅ㔚࿶ߦᄌ឵ߒߡ࡙

࠾࠹ࠖ࡮ࠥࠗࡦ቟ቯߩ㔚࿶ᏫㆶࠕࡦࡊOPA690 ߦࠃࠅ㔚࿶ାภߣߒߡขࠅ಴ߔޕ

IDTQS3VH245 B0 18 B1 17 B2 16 B3 15

0.1u 82 82

2.5 V

SW1 4.7k 4.7k

330 2.5V

XCF02SVO20 VCCJ VCCO VCCINT TDO NC NC NC CEO NC GND D0 NC CLK TDI TMS TCK CF OE/RESET NC CE

XC3S400PQ208BF 55 M0

54 M1 56 M2 159 TCK 160 TMS 208 TDI 158 TDO

PROG_B 207 103 DONE 104 CCLK

INIT_B 83

DIN/D0 92

3.3 V

0.1u 200

200

402

402 26.1

0.1u

IO_L19N_2 152 IO_L19P_2 150 IO_L20N_2 149 IO_L20P_2 148 IO_L21N_2 147 IO_L21P_2 146 IO_L22N_2 144 IO_L22P_2 143 IO_L23P_2 140 IO_L24N_2 139 IO_L24P_2 138 IO_L39N_2 137 IO_L39P_2 135 IO_L40N_2 133 XC3S400PQ208BFBank2

+10u 27 +VD

26 DGND 1 Bit1 2 Bit2 3 Bit3 4 Bit4 5 Bit5 6 Bit6 7 Bit7 8 Bit8 9 Bit9 Bit10 10

Bit11 11

Bit12 12 28 CLK 15 PD

REFin 17

+Va 24 AGND 20 Iout 22 Iout 21

BW 19 BY P 23

INT/EXT 16 18 FSA

+3.3 V

-3.3V 0.1u

+3.3V

+10u

0.1u 10p

0.1u

49.9

28.7

2k

0.01u

0.1u

3 + 4 -62+Vs-VsOutput 1

1

2

BNC DAC902

IC1

IC2

C1 C3

IC3

C4 C5

C6

C9 C10 C11

R3

R2 R1

R8 R4

R6 R5

R7

0.1u

C8

OPA690IDBV

R43 R44

C67 C66

IC1

R47 R46

R45

IC11 IC10

(6)

PCߣFPGAߩࠗࡦ࠲࡯ࡈࠚࠗࠬㇱPC߆ࠄFPGAߩࠕࠢ࠮ࠬߪ࿁〝ߩ⚛ሶࠍᢙ⃨❬߉ߦߒߡౝㇱ⁁

ᘒࠍ㗅⇟ߦ⺒ߺ಴ߔ

JTAG㧔ࠫࠚࠗ࠲ࠣJoint Test Action Group㧕ᣇᑼࠍ૶↪ߒߚޕXilinx␠ߩISE

ߣ

޿߁㐿⊒࠷࡯࡞

^㧞

ࠍ૶↪ߒߡޔVHDL ࠦ࡯࠼ߩ⵾૞ޔFPGA ߩ

㈩⟎ߩ⸳ቯޔࡃࠗ࠽࡝ᒻᑼߩ

bit

ࡈࠔ࡞ߩ⵾૞ࠍⴕߞߚޕߐࠄߦ

iMPACT

ࠍ૶↪ߒߡPROM ࠍ

BYPASS

ߩ⸳ቯߦߒߡࡄ࡜࡟࡞Υࠤ࡯

ࡉ࡞ࠍㅢߒߡ

bit

ࡈࠔࠗ࡞ࠍFPGA ߳ㅍߞߚޕJTAG ߩࡐ࡯࠻ߪFPGA ߩࡕ࡯࠼⸳ቯߩߚ߼ߩ55 ⇟

pinM0,54

⇟

pinM1,56

⇟

pinM2

ߩ⸳ቯߦ߆߆ࠊࠄߕᏱߦ೑↪ߔࠆߎߣ߇ߢ߈ࠆޕࠦࡀࠢ࠲

CON

ߩ

6

⇟

PROG

߇

High

ߩᤨ

TC7SH04F

ߩ಴ജߪ

Low

ߦߥࠅ

RN1101

ߪേ૞ߖߕޔITDQS3VH245 ߩ

2

⇟

ߩA0 ߆ࠄ಴ߡ߈ߚ

TDOߪ74HC125ࠍㅢࠅPC

ᚯࠆޕ

74HC125

ࠍേ૞ߐߖࠆߚ߼ߦߪޔ

CON

ߩ

5⇟pin

߆ࠄ಴ജߐࠇࠆCTRL ାภࠍLow ߦߔࠆޕߎࠇࠄߩାภߩേ߈ߪPC߆ࠄ

iMPACTߣ޿߁

࠰ࡈ࠻ߦࠃࠅಣℂߐࠇࠆޕߐࠄߦน៝ᕈߩะ਄ࠍ⋡ᜰߒၮ᧼਄ߩ

PROM( XCF02SVO20 )ߦࡈࠔࠗ࡞ࠍ

ㅍࠅޔPC ߆ࠄߩធ⛯ࠍಾࠅ㔌ߒߡޔၮ᧼ߛߌߢ߽േ૞ߔࠆࠃ߁ߦ⸳⸘ࠍ߅ߎߥߞߚޕPC ߆ࠄ

JTAG

ࠍㅢߒߡࡈࠔࠗ࡞ࠍ

PROM

ߦㅍࠆߩߦFPGA ߩ

BYPASS Registerࠍേ૞ߐߖࠆߎߣߦࠃࠅޔPC߆

ࠄ

FPGA

ࠍࡃࠗࡄࠬߐߖߡPROM ߦ

msc

ߣ޿߁ࡈࠔࠗ࡞ㅍࠆߎߣ߇ߢ߈ࠆޕ

FPGA

ߩM0,M1,M2 ࠍ ធ࿾ߔࠆߎߣߦࠃࠅޔFPGA ߪ

104

⇟

ߩ

CCLK

ࡇࡦࠍ㚟േߒޔߎࠇߦࠃࠅPROM ߇

3

⇟

ߩ

CLK

ߦࠃࠅ㚟േߐࠇࠆޕ࠲ࠢ࠻ࠬࠗ࠶࠴SW1 ࠍ᛼ߔߣFPGA ߩ207 ⇟

ߩPROG_B ߇Low ߦߥ ࠅޔ

FPGA

ߩࡔࡕ࡝߇ᶖ෰ߐࠇࠆޕ߹ߚޔ

103⇟pin

ߩDONE ߇Low ߦߥࠅ

PROMߩCE

߇Low ߦ ߥࠆޕ

FPGA

ߩࡔࡕ࡝ߩᶖ෰߇ቢੌߔࠆߣ83 ⇟pin ߩ

INIT_B

߇High ߦߥࠅߎࠇߦࠃࠅ

PROMߩ8

⇟

pin OE/RESET

߇High ߦߥࠆޕࠬࠗ࠶࠴ߩធὐ߇㔌ࠇPROG_B ߇

HighߦߥࠆߣPROM

ߩ7 ⇟

ߩCF ߽

High

ߦߥࠅޔPROM ߩ⸳ቯ࠺࡯࠲߇

PROM

ߩ

1⇟pin D0

߆ࠄ಴ജߐࠇFPGA ߩ

92

⇟

pin DIN/D0

ߦᦠ߈ㄟ߹ࠇࠆޕ

CON25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

74HC125 11OE

21A 1Y3

42OE

52A 2Y6

103OE 93A 4OE 13

4A 12

3Y8 4Y11 Vcc 14

GND 7

3.3 V

220p 0.1u 220p8

220p9

4.7k RN1101

47k

IDTQS3VH245 NC 1

A0 2

A1 3 4A2 5A3 6A4 7A5 8A6 9A7 10GND

Vcc 20 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 OE 19 TC7SH04F

NC 1

IN A 2

GND 3

OUT Y4 Vcc5

3.3 V

1k

3.3 V

2.5V

4.7k

47k 220p

MEM2012T10R0 CON

FPGA

߳ߩ㔚Ḯଏ⛎࿁〝

TPS75003 1OUT3

FB32 EN33 EN24 SS25 DGND6 SW27 IN28 IS29 FB210 FB111

IS112IN113SW114DGND15SS116EN117AGND18SS319

20 IN3

62k 100u 1u

1500p

0.1u 10u

Vin

0.01u

Vin

15k

390

33m

Vin

1500p 33m

MBRM120

Vishay SS32D2 15uH

Siliconix Si2323DS 5uH

Siliconix Si2323DS

100u

0.1u

10p 62k

100u

36k 510

DGND VCCAUX 2.5V, 300mA

VCCO 3.3V 2A +5 V

+5 V

VCCINT 1.2V 2A

(7)

FPGA

߳ߩ㔚Ḯଏ⛎⚿✢࿑

XC3S400PQ208BF VCCO_0 188 VCCO_0 201

VCCO_1 177

VCCO_1 164

VCCO_2 153

VCCO_2 136

VCCO_3 127

VCCO_3 110

VCCO_5 73

VCCO_5 60

VCCO_6 49

VCCO_6 32

VCCO_7 23

VCCO_7 6

VCCO_4 98

VCCO_4 84

VCCAUX 193

VCCAUX 173

VCCAUX 142

VCCAUX 121

VCCAUX 89

VCCAUX 69

VCCAUX 38

VCCAUX 17

VCCINT 192

VCCINT 174

VCCINT 88

VCCINT 70

GND 202 GND 195 GND 186 GND 179 GND 170 GND 163 GND 157 GND 151 GND 145 GND 134 GND 129 GND 118 GND 112 GND 105 GND 99 GND 91 GND 82 GND 75 GND 66 GND 59 GND 53 GND 47 GND 41 GND 30 GND 25 GND 14 GND 8 GND 1 VCC2.5V

VCC 3.3V

VCC1.2V

⍍㑆⊛ߥ㔚࿶ૐਅ㒐ᱛߩߚ߼ࡃࠗࡄࠬࠦࡦ࠺ࡦࠨࠍขࠅઃߌࠆޕ

VCC 1.2V

VCC 2.5V

VCC 3.3V

u

u 0.1u 0.1u

IC1

0.01u 0.01u

0.01u

0.01u 0.01u 0.01u 0.01u

0.01u 0.01u

0.01u

0.01u 0.01u

XC3S400PQ208BF XC3S400PQ208BF

XC3S400PQ208BF

0.01u

0.01

0.1u

0.1 0.1u

0.1u

0.1u 0.1u

0.1u

0.1u 0.1u

0.1u

0.1u 0.1u

0.1u

0.1u 0.1u 0.01u 0.01u 0.01u 0.01u

0.01u 0.01u 0.01u

DA

ᄌ឵ེ߳ߩ㔚Ḯଏ⛎࿁〝

MAXIM604 1 IN 2 GND 3 GND 4 OFF GNDGNDOUTSET 5678

+5V +3.3 V

10uF 10uF

(8)

ઃ㍳

PFD

߆ࠄߩ಴ജࠍDRO ߳ශടߔࠆ㔚ሶ࿁〝

0.1u

0.1 u

0.1u

0.1 u 0.1 u

R9 1 k

BNC

1

2 10u

10u 10 k

R3A 10 k

10 k

3.3 k

50 20 k

6.6k +15 V

-15 V

+15 V

MAX400C 2 -

3 + 1

OP37 2 -

3 + 1

SMA

1

2 10u

10u -15 V

+15 V

+

+ C

C

C C

C

LT1460ACN8- 6 6 4 2 banana

7

4 4 7

+ banana

5 +

ઃ㍳VHDL ࠦ࡯࠼

8*&. ߢ૶↪ߔࠆାภߦߟ޿ߡߩ⺑᣿

ENM ౉ജ࠺࡯࠲

ENM $#0- ߦធ⛯ߔࠆޕFCENMߦવࠊࠅ &# ᄌ឵ེࠍ㚟േߔࠆࠢࡠ࠶ࠢߣߥࠆޕ FCQWV 3 ߣ 3ߩ๺ߩ಴ജߣߒߡ &# ᄌ឵ེ߳಴ജߐࠇࠆޕ

RF$#0-ߦធ⛯ߐࠇߡ޿ࠆ &# ᄌ឵ེ &#%ࠍേ૞ߐߖࠆାภ TGUGV52#46#0:%523ࠍ࡝࠮࠶࠻ߐߖࠆାภ

3ENMߩጊߩᢙࠍᢙ߃ࠆᄌᢙ 3ENM ߩጊߩᢙࠍᢙ߃ࠆᄌᢙ

GPVKVK[ߣ 2QTVߩㇱಽߢᄖㇱߣߩࠗࡦ࠲࡯ࡈࠚࠗࠬࠍ⸥ㅀߔࠆޕ KPUVFANQIKE㧝ᧄߩ౉ജାภ✢ QWVUVFANQIKE㧝ᧄߩ಴ജାภ✢

QWVUVFANQIKEAXGEVQTFQYPVQᧄߩ಴ജାภ✢ߩ᧤

8*&. ࠦ࡯࠼

NKDTCT[+'''

WUG+'''56&A.1)+%A#..

WUG+'''56&A.1)+%A#4+6*#..

WUG+'''56&A.1)+%A705+)0'&#..

GPVKV[2(&KU

2QTVENMKPUVFANQIKE ENMKPUVFANQIKE ENMKPUVFANQIKE TGUGVKPUVFANQIKE

FCQWVQWVUVFANQIKEAXGEVQTFQYPVQ FCENMQWVUVFANQIKE

RFQWVUVFANQIKE GPF2(&

CTEJKVGEVWTG46.QH2(&KU

UKIPCN3UVFANQIKEAXGEVQTFQYPVQ UKIPCN3UVFANQIKEAXGEVQTFQYPVQ

(9)

UKIPCNFCUVFANQIKEAXGEVQTFQYPVQ DGIKP

RTQEGUUENM DGIKP

KHENM GXGPVCPFENM VJGP

33̍̍

GPFKH

GPFRTQEGUU

RTQEGUUENM DGIKP

33̍̍

GPFKH

GPFRTQEGUU

RTQEGUUENM DGIKP

FC33

FCQWVFC

GPFKH

GPFRTQEGUU

FCENMPQVENM RF GPF46.

⸘ߐࠇࠆߎߣ߇ᄙߊߥߞߡ߈ߡ޿ࠆ㧚 FPGA ߪ DSP ߦᲧ ߴ⋥ធࡂ࡯࠼࠙ࠚࠕࠍ᭴ᚑߔࠆߩߢ㧘㜞ㅦߥ࠺ࠖࠫ࠲࡞

1. はじめに

ޓ㜞ᐲᖱႎൻߩ൓޿ߪ㧘㓸Ⓧ࿁〝ߩᓸ⚦ൻ㧘㜞ㅦൻ㧘㜞 ᯏ⢻ൻ㧘ૐࠦࠬ࠻ൻࠍዉ߈㧘੹߹ߢࠕ࠽ࡠࠣ࿁〝ߢ⵾૞

ߒߡ޿ߚ࿁〝߇ DSP 㧔 Digital Signal Processor 㧕߿ FPGA 㧔 Field Programmable Gate Array 㧕╬ߢ⟎߈឵߃ࠄࠇߡ⸳

⸘ߐࠇࠆߎߣ߇ᄙߊߥߞߡ߈ߡ޿ࠆ㧚 FPGA ߪ DSP ߦᲧ ߴ⋥ធࡂ࡯࠼࠙ࠚࠕࠍ᭴ᚑߔࠆߩߢ㧘㜞ㅦߥ࠺ࠖࠫ࠲࡞

ା ภ ಣ ℂ ߇ น ⢻ ߣ ߥ ࠅ㧘 ߹ ߚ VHDL 㧔 Very high speed integrated circuit Hardware Description Language 㧕╬ߩ⸒

⺆ߦࠃࠅ ASIC㧔Application Specific Integrated Circuit㧕㐿

⊒߳ߩ㆏ࠍ㐿ߊ㧚ߘߩ৻ᣇߢⶄ㔀ߥᢙ୯Ṷ▚ࠍⴕ߁႐ว ߩࡊࡠࠣ࡜ࡓߦࠃࠆ⸳⸘ߩᨵエᕈߪ DSPߩ߶߁߇ఝࠇߡ

޿ࠆ߇㧘ㄭᐕ FPGA ߦࡊࡠ࠮࠶ࠨࠍ⚵ߺㄟߺಣℂߔࠆᣇ ᴺ߽㐿⊒ߐࠇߡ߈ߡ߅ࠅ㧘ߎߩ໧㗴߽⸃᳿ߒ߿ߔߊߥߞ ߡ߈ߡߪ޿ࠆ㧚ߐࠄߦ㧘 ASIC 㧘 FPGA 㧘 PROM ߣ AD ᄌ឵

ེ߿ DA ᄌ឵ེ╬ߩⶄᢙߩ࠴࠶ࡊࠍ 1 ࡄ࠶ࠤ࡯ࠫߦߒߚ SiP 㧔 System in Package 㧕ߩ㐿⊒߽น⢻ߣߥࠆ㧚๟ᵄᢙ೙

ᓮⵝ⟎ߩ࠺ࠖࠫ࠲࡞ൻߩ೑ὐߦߟ޿ߡߪߔߢߦ↥✚⎇⸘

㊂ᮡḰႎ๔ߩਛߢ⸥ߒߚ

㧚߹ߚ㧘ၮḰశ๟ᵄᢙ߇વࠊࠆ శ ࡈ ࠔ ࠗ ࡃ ࡯ ߩ 㐳 ߐ ೙ ᓮ ߩ ታ 㛎 ߢ ߪ㧘PSD㧔Phase Sensitive Detector㧕ࠍᄙbit ൻߒߚPFD㧔Phase Frequency Discriminator㧕ࠍ↪޿ࠆߎߣߦࠃࠅ㧘น೙ᓮ▸࿐߇ᐢ߇ࠅ㧘

Abstract

A Phase Frequency Discriminator (PFD) has been developed for atomic frequency standards and other frequency control systems using the state of the art digital technology. The PFD has been implemeted successfully in an exciter system for Sr+

microwave frequency standard.

ࠦࡅ࡯࡟ࡦ࠻㐳એ਄ߩశ〝Ꮕࠍߟߌߚ႐วߢ߽㧘శ〝㐳

೙ᓮࠍⴕ߁ߎߣ߇ߢ߈㧘߹ߚ 1 ᵄ㐳એਅߩ♖ᐲߢశ〝㐳 ࠍ቟ቯൻߢ߈ࠆ⢻ജ߇޽ࠆߎߣ߽⏕⹺ߐࠇߡ޿ࠆ

㧚ߎߩ ࠃ߁ߥ⢛᥊߆ࠄ㧘㜞ㅦ࠺ࠖࠫ࠲࡞ାภಣℂߩశࡈࠔࠗࡃ

࡯ߩ㐳ߐ೙ᓮ㧘ේሶᤨ⸘ߩࠛࠠࠨࠗ࠲࡯ߩ૏⋧๟ᵄᢙᲧ セེ㧘ࠝࡈ࠮࠶࠻ࡠ࠶ࠢ࡟࡯ࠩࠪࠬ࠹ࡓ㧘శࠦࡓߩ࠺ࠖ

ࠫ࠲࡞ࠨ࡯ࡏ╬߳ߩㆡ↪ࠍ⋡ᜰߒ㧘 PFD ߩ㐿⊒ࠍⴕߞߚ㧚

߹ߚታ㓙ߦࡑࠗࠢࡠᵄߩࠛࠠࠨࠗ࠲࡯߳ PFD ߩㆡ↪ࠍ⹜

ߺߚߩߢႎ๔ߔࠆ㧚 2. 位相周波数比較器

ޓ৻⥸⊛ߦ⸒ࠊࠇߡ޿ࠆ૏⋧Ყセེߪ 2 ߟߩࠢࡠ࠶ࠢା

ภ㑆ߩ૏⋧Ꮕߦᔕߓߚᤨ㑆ߩ㑆㧘㔚࿶ࠍ಴ജߔࠆ㧚ାภ 㑆ߩ૏⋧Ꮕ߇৻๟ᦼએ਄ߕࠇߡߒ߹ߞߚ႐วߪ㧘ߘߩߕ ࠇࠍᬌ಴ߢ߈ߕ㧘৻๟ᦼࠬ࡝࠶ࡊߒߚାภࠍ಴ജߔࠆ㧚

૏⋧๟ᵄᢙᲧセེ PFD 㧔 Phase Frequency Discriminator 㧕ߪ㧘 2 ߟߩାภߩ૏⋧Ꮕ߇৻๟ᦼએ਄ߕࠇߡ߽㧘ߘߩߕࠇࠍᖱ ႎߣߒߡ⫾߃ࠆߩߢ㧘ାภߩ૏⋧ᬌ಴▸࿐ࠍᐢߍࠆߎߣ ߇ߢ߈ࠆ㧚૏⋧๟ᵄᢙᲧセᦼࠍ๟ᵄᢙ೙ᓮߦ↪޿ࠆߦߪ㧘

૏⋧ߩᲧセㇱಽߩઁߦ㧘౉ജᱜᒏᵄࠍ⍱ᒻᵄߦᄌ឵ߔࠆ

ࠦࡦࡄ࡟࡯࠲ㇱ㧘ߐࠄߦ૏⋧ߩ㆑޿ࠍ㔚࿶ߦᄌ឵ߔࠆ DA ᄌ឵ེࠍട߃ࠆߣଢ೑ߢ޽ࠆ㧚੹࿁㧘⵾૞ߒߚ࠺ࠖࠫ࠲

࡞ PFD ⵝ⟎ࠍ࿑1 ߦ㧘߹ߚࡏ࡯࠼ߩ࿁〝࿑ࠍઃ㍳ߦ␜ߔ㧚 FPGA ߣ㜞ㅦ DA ࠦࡦࡃ࡯࠲ߩធ⛯㧘 FPGA ߣ PC ߩࠗࡦ࠲

࡯ ࡈ ࠚ ࠗ ࠬ㧘 PROM ߣ FPGA ߩ ធ ⛯㧘 ࠦ ࡦ ࡄ ࡟ ࡯ ࠲ ߣ

૏⋧๟ᵄᢙᲧセེ⵾૞ߩᛛⴚ⾗ᢱ

ᐔ㊁ޓ⢒ *㧘⪤ᧄޓᙗ **㧘ᩉ↸ ᥙሶ **㧘ฎ⾐ ଻༑ **

㧔ᐔᚑ 20 ᐕ 8 ᦬ 4 ᣣฃℂ㧕

Technical Note for Phase Frequency Discriminator.

Iku HIRANO, Ken HAGIMOTO, Akiko YANAGIMACHI, Yasuki KOGA

ߎߢ㧘ㄭᐕ᥉෸߇⋡ⷡߒ޿ FPGAߦ⺰ℂ࿁〝ࠍᦠ߈ㄟߺ㧘 Ṷ▚࿁〝ࠍ᭴ᚑߔࠆߎߣߦߒߚ㧚VHDL ߪࡂ࡯࠼࠙ࠚࠕ ࠍ⸥ㅀߔࠆ⸒⺆ߢ㧘⵾૞ߒߚ VHDL ࠦ࡯࠼ࠍ⺰ℂวᚑ࠷

࡯࡞ߦࠃߞߡ⺰ℂ࿁〝ߩ࠺࡯࠲ࠍ૞ࠅ㧘ߘࠇࠍ FPGA ߹ ߚߪ PROM ߦᦠ߈ㄟߺ FPGA ౝㇱߦ⺰ℂ࿁〝ࠍ᭴ᚑߔࠆ㧚

⇟pin ߩ1 MHzߩ᳓᥏ࠢࡠ࠶ࠢ㧘߽ߒߊߪ 72⇟pin ߩᄖㇱ ߩࠢࡠ࠶ࠢ߆ࠄߩାภࠍclk3 ߣߒߡprocess ᢥߩਛߦ⸥ㅀ ߒߡ㧘ࠢࡠ࠶ࠢߏߣߦ Q1 ߣ Q2 ߩᏅࠍߣࠅ㧘 DA ᄌ឵ེ߳

ㅍࠆ㧚ߘߩߐ޿ Q1 ߣ Q2 ߩᏅ߇ 0 ߢ޽ࠆᤨߦ㧘 DA ᄌ឵ེ

ߩ಴ജ߇ 0 ߦߥࠆࠃ߁ㆡᒰߥᢙ୯ࠍട߃ߡࠝࡈ࠮࠶࠻⺞

▵ࠍߔࠆ㧚೙ᓮࡄ࡜ࡔ࡯࠲ߣߒߡ㧘ᄌᢙ Q1,Q2 ߩჇടಽ ߩ⺞▵㧘 Q1 ߣ Q2 ߩᏅߩାภࠍ಴ജߔࠆᤨ㑆㑆㓒ߩ⺞▵㧘

╬߇⠨߃ࠄࠇࠆ㧚 4. 性能試験

ޓFPGA ߣ ߒ ߡ SPARTAN3 ࠍ ૶ ↪ ߒ ߚ㧚SPARTAN3 ߪ

Xilinx ␠ߦࠃࠅ᳃↢ᯏེߥߤߩ㊂↥ຠ↪ߦࠦࠬ࠻ࠍ㊀ⷞߒ

ߡ㐿⊒ߐࠇߚ FPGA ߢ޽ࠅ㧘↥ᬺ⇇ߢߪᐢߊ૶ࠊࠇߡ޿ࠆ㧚 ߎߩߚ߼㧘㐿⊒ߔࠆߚ߼ߩᖱႎ߇Ყセ⊛౉ᚻߒ߿ߔ޿㧚 SPARTAN3 ߩ 72 ⇟ pin ߆ࠄ 2 MHz ⍱ᒻᵄ 0-3.3 V ߩࠢࡠ࠶

ࠢାภࠍ౉ജߒߡ㧘 76 ⇟ pin ߆ࠄ 14.5 MHz 77 ⇟ pin ߦߪ

15.0 MHz ߩ⍱ᒻᵄ߇౉ജߒߚᤨߩ಴ജାภࠍ࿑ 2 ߦ␜ߔ㧚

VHDL ࠦ࡯࠼ߩ Q1,Q2 ߩჇಽߪ 1 ߦ⸳ቯߔࠆ㧚㧔ߎߩᤨⵝ

⟎ߩ౉ജ┵ሶߦශടߐࠇߚᱜᒏᵄߩᝄ᏷ߪ 1.2Vp-p ߢ޽

ࠆ㧚㧕๟ᵄᢙᏅ߇ 500 kHz ࠃࠅ12 bit ߩDAࠦࡦࡃ࡯࠲ࠍ૶

↪ߒߡ޿ࠆߩߢ (1/500 kHz) 4096 = 8.192 msec ๟ᦼߩ ฝ਄߇ࠅߩᢳ✢߇ࠝࠪࡠߩ↹㕙ߦ⴫␜ߐࠇࠆ㧚ⵝ⟎ߩ౉

FPGAߩធ⛯╬ߩ࿁〝࿑㧘 VHDLߦࠃࠆࡊࡠࠣ࡜ࡓ㐿⊒ߪ㧘

ᄙߊߩᢥ₂ߣ૶߁࠺ࡃࠗࠬߩࠗࡦ࠲࡯ࡀ࠶࠻ᬌ⚝ߦࠃࠆ

⾗ᢱߩ࠳࠙ࡦࡠ࡯࠼ߐࠄߦ࠺ࡃࠗࠬࡔ࡯ࠞ߳ߩ໧޿วࠊ ߖ╬ߦࠃࠅ⸳⸘ࠍⴕߞߚ

㧚 PFD ߪ౉ജߩࠦࡦࡄ࡟࡯

࠲ TA8504F ߢ ౉ ജ ᵄ ᒻ ߇ Ꮕ േ ECL 㧔 Emitter-coupled logic 㧕಴ജߣߥࠅ -1.2 V ࠍਛᔃߦr 0.4 V ߩ⍱ᒻᵄߦᄌ឵

ߐࠇࠆ㧚 ECL ߩᦨᄢߩ․ᓽߪ㧘࠻࡜ࡦࠫࠬ࠲ࠍ㘻๺ߐߖ ߕߦ೑↪ߔࠆߚ߼㧘⁁ᘒᄌൻ߇㕖Ᏹߦ㜞ㅦߦⴕ߃ࠆὐߢ

޽ࠆ㧚ᓥߞߡ㧘ECL ߢ᭴ᚑߐࠇߚ࿁〝ߪ㕖Ᏹߦ㜞ㅦߦേ

૞ߔࠆ

㧚৻⥸ߦ಴࿁ߞߡ޿ࠆ ECL ࿁〝ߪ⽶ߩ㔚Ḯ㔚࿶

㧔-5.2V㧕ࠍଏ⛎ߐࠇ㧘⺰ℂ࡟ࡌ࡞߽ઁߩ⺰ℂ⚛ሶߣߪ⇣

ߥࠆ㧚ᓥߞߡ㧘ઁߩ TTL 㧔 Transistor-transistor-logic 㧕ߥ ߤߣ ECL ࠍ⚿วߔࠆߦߪ㧘ࠗࡦ࠲࡯ࡈࠚࠗࠬ࿁〝߇ᔅⷐ ߣߥࠅ㧘ߎߩߚ߼ߩᄌ឵⚛ሶߣߒߡ MC10H125 ࠍ૶↪ߒ ߚ㧚 MC10H12 ߪ ON Semiconductor ␠ߩࠛࡒ࠶࠲⚿วࡠࠫ

࠶ࠢߢ࠻࡜ࡦࠫࠬ࠲ߩ⫾Ⓧᤨ㑆ࠍߥߊߒ㜞ㅦേ૞ࠍน⢻

ߦߔࠆ㕖㘻๺ဳ࠺ࠖࠫ࠲࡞࡮ࡠࠫ࠶ࠢߢ޽ࠆ

㧚 TTL ࡟ ࡌ࡞ߦᄌ឵ߐࠇߚାภߪ FPGA ߳౉ജߐࠇ㧘ࠢࡠ࠶ࠢା

ภߣߒߡ೑↪ߐࠇࠆ㧚VHDL ߦࠃࠅࠢࡠ࠶ࠢߏߣߦࠞ࠙

ࡦ࠻ߔࠆ࡟ࠫࠬ࠲ࠍ↪ᗧߒߡߎߩࠢࡠ࠶ࠢࠍᢙ߃ߡ޿ߊ㧚

ࠦࡦࡄ࡟࡯࠲ߣECL-TTL ᄌ឵⚛ሶࠍ 2 ୘↪ᗧߔࠆߎߣߦ ࠃࠅ 2 ߟߩ౉ജ๟ᵄᢙߩࠞ࠙ࡦ࠻ᢙ߆ࠄߘߩᏅࠍ᳞߼㧘 FPGA ߦ૶↪ߔࠆࠢࡠ࠶ࠢାภࠍၮḰߣߒߚ޽ࠆ৻ቯ๟

ᦼߏߣߦ FPGA 㧔 XC3S400PQBF 㧕߆ࠄ 12 bit ߩࡄ࡜࡟࡞

ାภߣߒߡ಴ജߐߖߡ㧘ߘߩାภࠍ DA ᄌ឵ེߢࠕ࠽ࡠࠣ

ାภߦᄌ឵ߐߖࠆߎߣߦࠃࠅ PFD ࠍ᭴ᚑߔࠆߎߣ߇ߢ߈ ࠆ㧚

3. VHDL プログラム

ޓ⺰ℂ࿁〝ࠍ᭴ᚑߔࠆߦߪࡠࠫ࠶ࠢIC ࠍ⚿✢ߒߡ޿ߊᣇ ᴺ߽޽ࠆ߇㧘 IC 㑆ߩ㈩✢߇ⶄ㔀ߦߥߞߚࠅ㧘ାภߩㆃࠇ㧔ࠬ

ࠠࡘ࡯㧕㧘ࠨࠗ࠭߇ᄢ߈ߊߥࠆߣ޿ߞߚ໧㗴߇↢ߓࠆ㧚ߘ

図 2ޓࠝࠪࡠࠬࠦ࡯ࡊߦ⴫␜ߐࠇߚ಴ജାภ

図 1ޓPFD ࡏ࡯࠼

ේሶߣࡑࠗࠢࡠᵄߩ⋧੕૞↪߆ࠄᬌ಴ߒߡ޿ࠆାภᒝᐲ ߇ࠊߕ߆ߦᄌൻߔࠆ㧚ߎߩᄌൻࠍࠨ࡯ࡏᯏ᭴ߦࠃࠅ10 MHz ╬ߩ᳓᥏⊒ᝄེ߳Ꮻㆶߔࠆߎߣߦࠃࠅ㧘ࡑࠗࠢࡠᵄ

ේሶ๟ᵄᢙᮡḰߪߟߊࠄࠇࠆ

㧚࿑ 4 ߦ PFD 㧔࠺ࠖࠫ࠲

࡞૏⋧๟ᵄᢙᲧセེ㧕ࠍࡑࠗࠢࡠᵄࠛࠠࠨࠗ࠲࡯߳ㆡ↪

ᐔ㊁ޓ⢒ *㧘⪤ᧄޓᙗ 㧘ᩉ↸ ᥙሶ 㧘ฎ⾐ ଻༑ **

↪ߒߡ޿ࠆߩߢ (1/500 kHz) 4096 = 8.192 msec ๟ᦼߩ ฝ਄߇ࠅߩᢳ✢߇ࠝࠪࡠߩ↹㕙ߦ⴫␜ߐࠇࠆ㧚ⵝ⟎ߩ౉

ࡠ࠶ࠢ⺃㔚૕⊒ᝄེ (PLO) ߢ 499 ㅛ୚ߐࠇ 4990 MHz ߣߥ ࠆ㧚 ৻ ᣇ㧘⺃㔚 ૕ ⊒ ᝄ ེ DRO㧔Dielectric Resonant Oscillator㧕ߪ 5002 MHzㄭறߢ⊒ᝄߔࠆࠃ߁ߦ⸳ቯߔࠆ㧚 ߎߩ๟ᵄᢙߣ 4990 MHzߩ๟ᵄᢙߪ࠳ࡉ࡞ࡃ࡜ࡦࠬ࠼ࡒࠠ

ߦ 1 ⑽ᐔဋߢ 4 10

ߩ಴ജߩ࠴ࡖ࡯࠻ࠍ࿑ 3ߦ␜ߔ㧚10 000 000 Hz ߣ10 000 010 Hzߩାภࠍട߃ߚᤨߦߪ಴ജାภ߇-1.0 V 㨪 0.9 V ߹ ߢᄌൻߒ㧘 410 ⑽๟ᦼߢᄌൻߔࠆ㧚 (1/10) 4096 = 409.6

⑽ޓࠃߞߡ࿑ 4 ߩ࠴ࡖ࡯࠻ߩ 1 ⑽㑆ߩ㔚࿶ߩᦨᄢᄌൻߪ 9 μ Vߢ޽ࠆߩߢ10Hz : 1.9 / 410 = x : 9 μ V / 1 ⑽ࠃࠅ4.3 10

⏕ᐲߪ 4.3 10

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