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APPLICATION NOTE

AND9630/D

Audio Functions User’s Manual for LC823450 Software

Development

Overview

This application note describes the audio functions of LC823450 Series (called LC823450 hereafter) for software development using this device. Each functions as follow blocks are described in this manual.

This user manual is designed to provide a good understanding of the audio functions of LC823450 as a reference document.

Intended audience is customers who are building audio application using LC823450.

AudioModule AudioBuffer SSRC EQ BEEP DAC DAMPCTL DGMIC PCKGEN ATM SINGEN ASRC MP3DEC MP3ENC AUDCTRL PCMSP PCMPS MUTEDV MUTE VOLUME METER

External Memory Controller

APB Bridge ARM Cortex-M3

SWD/SWV ICE

DMAC (8ch)

Plain Timer (1ch×3)

SPI (1ch) 10bit ADC

(6ch)

SD I/F (3ch)

OSC

XT1 RC

USB2.0

32.768kHz

Audio PLL PORT0~4

(80 I/O) PORT5 (10 I/O) Main

Module Manager Reset Controller

BUF (512/512 byte×3)

USB2.0 Device PHY

1MHz~

50MHz

EXT1

EXT3 BUF (4.5 Kbyte)

XT1

XT1 XTRTC

I2C (2ch) UART

(3ch)

BCK0/1 MCLK0/1 (PCM I/F)

ROM (256k byte) SDRAM

CTRL

Multiple Timer (2ch×4)

MS PB MS I/F

ISOLATED-B ISOLATED-D ARM Cortex-M3 LPDSP32

JTAG ICE

Multilayer Bus

RTC

ISOLATED XTRTC S-Flash I/F

(1ch)

ROM (220k byte) SRAM

(120k byte)

BASIC EXT4

Cache (16 Kbyte)

ISOLATED-G

SRAM (512k byte)

SRAM (512k byte)

SRAM (512k byte)

ISOLATED-C ISOLATED-I

USB2.0 Host ISOLATED-E

ISOLATED-H

EXT2 not used intentionally System

PLL

XTRTC

OSC

XT1 XTRTCAHB CLK (HCLK) MP3

Encoder PCM

I/F Audio Buffer

(64 Kbyte)

MP3 Decoder

ATM

ISOLATED-A PCM

I/F

BEEP VOLUME

SSRC MUTE

Class-D AMP 16bit Audio

DAC

Digital Mic

METER EQ3

ASRC

Audio block on LC823450

(3)

1 Audio Module ... 13

1-1 Introduction ... 13

1-1-1 About the Audio Module ... 14

1-2 Functional Overview ... 15

1-2-1 Functional description... 16

1-3 Programmer’s Model ... 17

1-3-1 About the programmer’s model ... 23

1-3-2 Summary of Audio Module registers ... 23

1-4 Operation ... 24

1-4-1 Operation Setting Descriptions ... 24

1-4-2 Standard Operation Flow ... 47

1-4-3 SRC Operation Flow... 75

2 Audio Buffer ... 85

2-1 Introduction ... 85

2-1-1 Brief Summary of ABUF ... 85

2-2 Functional Overview ... 86

2-2-1 ABUF Circuit Configuration ... 87

2-3 Programmer’s Model ... 88

2-3-1 About the programmer’s model ... 88

2-3-2 Summary of ABUF registers ... 88

2-3-3 Register Descriptions ... 92

2-4 Operation ... 140

2-4-1 Access Register Data Alignment ... 140

2-4-2 Access Register ... 142

2-4-3 Data Transfer Between Audio Buffer and AUDIO H/W ... 143

2-4-4 RAM Allocation ... 144

2-4-5 Internal Transfer (Redirect) ... 146

2-4-6 Accumulation Mode ... 148

2-4-7 Recording Monitor ... 151

2-4-8 Overflow and Underflow ... 152

2-4-9 Interrupt ... 153

2-4-10 DMA Hardware Request ... 154

2-4-11 Audio Buffer Clock Frequency ... 155

3 Synchronous Sampling Rate Converter (SSRC) ... 165

3-1 Introduction ... 165

3-1-1 Brief Summary of SSRC ... 165

(4)

3-2 Functional Overview ... 167

3-2-1 SSRC Circuit Configuration ... 167

3-3 Programmer’s Model ... 168

3-3-1 About the programmer’s model ... 168

3-3-2 Summary of SSRC registers ... 168

3-3-3 Register Descriptions ... 169

3-4 Operation ... 176

3-4-1 SSRC-SRC Start Operation Flow ... 176

3-4-2 SSRC-SRC Stop Operation Flow ... 177

3-4-3 SSRC- Input and Output Sampling Rate Change Flow ... 178

3-4-4 Through Start Operation Flow ... 178

3-4-5 Precautions for use... 178

4 Equalizer (EQ3) ... 179

4-1 Introduction ... 179

4-1-1 About the EQ3 module ... 180

4-2 Functional Overview ... 181

4-2-1 Functional description... 182

4-2-2 Secondary IIR filter structure ... 183

4-3 Programmer’s Model ... 184

4-3-1 About the programmer’s model ... 185

4-3-2 Summary of EQ3 registers ... 185

4-3-3 Register Descriptions ... 186

4-4 Operation ... 195

4-4-1 EQ3 reset ... 195

4-4-2 EQ3 bypass ... 196

4-4-3 EQ3 coefficient RAM setting ... 197

4-4-4 Flow chart ... 212

4-4-5 Important notice ... 217

5 Beep Generator (BEEP) ... 218

5-1 Introduction ... 218

5-1-1 About the BEEP module ... 219

5-2 Functional Overview ... 220

5-2-1 Functional description... 221

5-3 Programmer’s Model ... 222

5-3-1 About the programmer’s model ... 223

5-3-2 Summary of BEEP registers ... 223

(5)

5-3-3 Register Descriptions ... 224

5-4 Operation ... 229

5-4-1 BEEP output setting ... 229

5-4-2 BEEP reset ... 231

5-4-3 BEEP bypass ... 231

5-4-4 BEEP motion ... 232

5-4-5 Flow chart ... 237

6 Class-D Amplifier PWM modulator (DAC) ... 244

6-1 Introduction ... 244

6-1-1 About the DAC module ... 245

6-2 Functional Overview ... 246

6-2-1 Functional description... 247

6-3 Programmer’s Model ... 248

6-3-1 About the programmer’s model ... 249

6-3-2 Summary of DAC registers ... 249

6-3-3 Register Descriptions ... 250

6-4 Operation ... 257

6-4-1 Filter responses ... 257

6-4-2 Operation explanation ... 260

6-4-3 PCM output format ... 261

6-4-4 Flow chart ... 261

6-4-5 Important notice ... 261

7 Class-D amplifier control (DAMPCTL) ... 262

7-1 Introduction ... 262

7-1-1 About the DAMPCTL module ... 263

7-2 Functional Overview ... 264

7-2-1 Functional description... 265

7-3 Programmer’s Model ... 266

7-3-1 About the programmer’s model ... 267

7-3-2 Summary of DAMPCTL registers ... 267

7-3-3 Register Descriptions ... 268

7-4 Operation ... 276

7-4-1 Operation explanation ... 276

7-4-2 Flow chart ... 278

7-4-3 Important notice ... 281

8 Digital Mic Interface (DGMIC) ... 282

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8-1 Introduction ... 282

8-1-1 Brief Summary of DGMIC ... 283

8-2 Functional Overview ... 284

8-2-1 DGMIC Circuit Configuration ... 285

8-3 Programmer’s Model ... 286

8-3-1 About the programmer’s model ... 287

8-3-2 Summary of DGMIC registers ... 287

8-3-3 Register Descriptions ... 288

8-4 Operation ... 318

8-4-1 Filter characteristics... 318

8-4-2 Reset Operation ... 322

8-4-3 Input Data Format ... 322

8-4-4 PDM Input Register Setting ... 323

8-4-5 Programmable Filter ... 324

8-4-6 Soft mute / Attenuator ... 326

8-4-7 ALC Operation Description ... 327

8-4-8 Digital Mic Control Procedure ... 337

8-4-9 Precautions ... 337

9 PCM Clock Generator (PCKGEN) ... 338

9-1 Introduction ... 338

9-1-1 About the PCKGEN module ... 339

9-2 Functional Overview ... 340

9-2-1 Functional description... 341

9-3 Programmer’s Model ... 342

9-3-1 About the programmer’s model ... 343

9-3-2 Summary of PCKGEN registers ... 343

9-3-3 Register Descriptions ... 344

9-4 Operation ... 356

9-4-1 MCLK output frequency ... 356

9-4-2 Important notice ... 356

10 AudioTimer (ATM) ... 357

10-1 Introduction ... 357

10-1-1 About the ATM module ... 358

10-2 Functional Overview ... 359

10-2-1 Functional description ... 360

10-3 Programmer’s Model ... 361

(7)

10-3-1 About the programmer’s model ... 362

10-3-2 Summary of ATM registers ... 362

10-3-3 Register Descriptions ... 363

10-4 Operation ... 368

10-4-1 ATM counter underflow duration ... 368

11 SINE Wave Generator (SINGEN) ... 369

11-1 Introduction ... 369

11-1-1 About the SINGEN module ... 370

11-2 Functional Overview ... 371

11-2-1 Functional description ... 372

11-3 Programmer’s Model ... 373

11-3-1 About the programmer’s model ... 374

11-3-2 Summary of SINGEN registers ... 374

11-3-3 Register Descriptions ... 375

11-4 Operation ... 378

11-4-1 SINGEN output level ... 378

11-4-2 SINGEN output frequency ... 378

11-4-3 Important notice ... 378

12 Async Sampling Rate Converter (ASRC) ... 379

12-1 Introduction ... 379

12-1-1 Brief Summary of ASRC ... 379

12-2 Functional Overview ... 380

12-2-1 ASRC Circuit Configuration ... 380

12-2-2 SSRC Circuit Configuration ... 381

12-2-3 FSI ADJUST function and circuit configuration ... 382

12-2-4 Regarding block(*2) ... 383

12-3 Programmer’s Model ... 386

12-3-1 About the programmer’s model ... 386

12-3-2 Summary of ASRC registers ... 386

12-3-3 Register Descriptions ... 388

12-4 Operation ... 414

12-4-1 ASRC Start Operation Flow of Manual Adjustment Mode ... 415

12-4-2 ASRC Start Operation Flow of Automatic Adjustment Mode ... 417

12-4-3 ASRC Stop Operation Flow ... 421

12-4-4 ASRC Input and Output Sampling Rate Change Flow ... 422

12-4-5 Audio Data Termination Flow ... 422

(8)

12-4-6 Precautions for use... 422

13 MP3 Decoder (MP3DEC) ... 423

13-1 Introduction ... 423

13-1-1 The Outline of MP3DEC ... 424

13-2 Functional Overview ... 425

13-2-1 MP3DEC Circuit Configuration ... 426

13-3 Programmer’s Model ... 427

13-3-1 About the Programmer’s Model ... 428

13-3-2 Summary of MP3DEC Registers ... 428

13-3-3 Register Descriptions ... 429

13-4 Operation ... 445

13-4-1 Status Ready Set Timing ... 445

13-4-2 MP3 Decoder Internal Process ... 446

13-4-3 MP3 Format ... 447

13-4-4 Normal play ... 447

13-4-5 PAUSE processing ... 447

13-4-6 SKIP Process ... 448

13-4-7 Reading out Header Information ... 448

13-4-8 Error Processing ... 450

13-4-9 Frame Counter ... 450

13-4-10 Precautions For Use ... 451

14 MP3 Encoder (MP3ENC) ... 452

14-1 Introduction ... 452

14-1-1 Outline of MP3ENC ... 453

14-2 Functional Overview ... 454

14-2-1 MP3ENC circuit configuration ... 455

14-3 Programmer's Model ... 456

14-3-1 About the programmer's model ... 457

14-3-2 Summary of MP3ENC registers ... 457

14-3-3 Register Descriptions ... 458

14-4 Operation ... 467

14-4-1 PCM sampling frequency setting ... 467

14-4-2 MP3 data bit rate ... 467

14-4-3 Format for MP3 encoder ... 468

14-4-4 Control flow ... 469

14-4-5 Directions ... 474

(9)

15 AudioControl (AUDCTRL) ... 475

15-1 Introduction ... 475

15-1-1 About the AUDCTRL module ... 476

15-2 Functional Overview ... 477

15-2-1 Functional description ... 478

15-3 Programmer’s Model ... 480

15-3-1 About the programmer’s model ... 481

15-3-2 Summary of AUDCTRL registers... 482

15-3-3 Register Descriptions ... 486

15-4 Operation ... 526

15-4-1 Important notice ... 526

16 PCMIF S/P (PCMSP) ... 527

16-1 Introduction ... 527

16-1-1 Outline of PCMSP ... 528

16-2 Functional Overview ... 529

16-2-1 PCMSP circuit configuration ... 530

16-3 Programmer's Model ... 531

16-3-1 About the programmer's model ... 532

16-3-2 Summary of PCMSP registers ... 532

16-3-3 Register Descriptions ... 533

16-4 Operation ... 536

16-4-1 PCM input setting ... 537

16-4-2 PCM input corrugate... 538

16-4-3 Width of output PCM data ... 541

16-4-4 Directions ... 554

17 PCMIF P/S (PCMPS) ... 555

17-1 Introduction ... 555

17-1-1 Outline of PCMPS ... 556

17-2 Functional Overview ... 557

17-2-1 PCMPS circuit composition ... 558

17-3 Programmer's Model ... 559

17-3-1 About the programmer's model ... 560

17-3-2 Summary of PCMPS registers ... 560

17-3-3 Register Descriptions ... 561

17-4 Operation ... 564

17-4-1 PCM output setting ... 565

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17-4-2 PCM output formats... 566

17-4-3 Width of input PCM data ... 569

17-4-4 Directions ... 582

18 Mute Demand/Valid control (MUTE DV) ... 583

18-1 Introduction ... 583

18-1-1 Outline of MUTE DV ... 584

18-2 Functional Overview ... 586

18-2-1 MUTE DV circuit configuration ... 587

18-3 Programmer's Model ... 588

18-3-1 About the programmer's model ... 589

18-3-2 Summary of MUTE DV registers ... 589

18-3-3 Register Descriptions ... 590

18-4 Operation ... 599

18-4-1 Setting at data waiting time ... 599

18-4-2 Setting at holding time ... 600

18-4-3 Setting of automatic mute release time ... 600

18-4-4 Mute status ... 601

18-4-5 Function explanation ... 601

18-4-6 Set flow ... 602

18-4-7 Directions ... 605

19 Mute (MUTE) ... 606

19-1 Introduction ... 606

19-1-1 Outline of MUTE ... 607

19-2 Functional Overview ... 608

19-2-1 MUTE circuit configuration ... 609

19-3 Programmer's Model ... 610

19-3-1 About the programmer's model ... 611

19-3-2 Summary of MUTE registers ... 611

19-3-3 Register Descriptions ... 612

19-4 Operation ... 621

19-4-1 Setting at holding time ... 621

19-4-2 Setting of automatic mute release time ... 622

19-4-3 Mute status ... 622

19-4-4 Function explanation ... 623

19-4-5 Set flow ... 624

19-4-6 Directions ... 625

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20 Volume (VOLUME) ... 627

20-1 Introduction ... 627

20-1-1 About the VOLUME module ... 628

20-2 Functional Overview ... 629

20-2-1 Functional description ... 630

20-3 Programmer’s Model ... 631

20-3-1 About the programmer’s model ... 632

20-3-2 Summary of VOLUME registers ... 632

20-3-3 Register Descriptions ... 633

20-4 Operation ... 642

20-4-1 VOLUME gain ... 642

20-4-2 VOLUME hold time ... 643

20-4-3 VOLUME transition ... 644

20-4-4 VOLUME mute ... 646

20-4-5 VOLUME direct setting ... 647

20-4-6 VOLUME mode change ... 648

20-4-7 Flow chart ... 651

20-4-8 Important notice ... 652

21 Meter (METER) ... 653

21-1 Introduction ... 653

21-1-1 Outline of METER... 654

21-2 Functional Overview ... 655

21-2-1 METER circuit configuration ... 656

21-3 Programmer's Model ... 657

21-3-1 About the programmer's model ... 658

21-3-2 Summary of METER registers ... 658

21-3-3 Register Descriptions ... 659

21-4 Operation ... 671

21-4-1 Software setting flow ... 671

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Preface

Intended audience

This user manual is designed to provide a good understanding of the hardware and software functions of LC823450.

This can also be used as a reference document for hardware and software development of the system using these devices.

Typographical

This manual uses the following typographical conventions:

* : Explanation of the note which is attached in the text Note : The contents which want to be read carefully Footnote : Footnote during the text

Data notation : High-order digit is on the left, low-order digit is on the right Attention : Please be sure to read this comment with care

Remarks : Remarks of the context Heaviness of the data notation

: Left is MSB(Most Significant Bit), Right is LSB(Least Significant Bist) Numerical notation

binary : XXXXb decimal : XXXX hexadecimal : 0xXXXX

Data type

word : Four bytes (32 bits) half word : Two bytes (16 bits) byte : Eight bits (8 bits)

Description of Terms

This is a list of terms and their definitions that are used in this manual.

No Terms Descriptions

1 PCM Pulse code modulation.

2 Sampling frequency This is a numeric value to express how many times the conversion from an analog signal to digital signal is performed within one second.

3 256/384fs 256 or 384 times the qualitized frequency.

4 MP3 MPEG Audio Layer-3. A kind of audio compression format used for Digital audio.

5 MPEG-1

MPEG-2 MPEG-2.5

One of a standard picture spec created by the Moving Picture Experts Group that was formed by ISO and IEC JTC 1.

(13)

6 Equalizer (EQ3)

Changes the frequency characteristics of audio signals.

7 BEEP “Beep” sound.

8 LR clock (LRCLK / LRCK)

A signal to distinguish between L and R channels of an audio signal in the 2 channel stereo.

9 I2S Inter-IC Sound. It is a standard used for digital audio serial data transfer in between ICs.

10 Demand signal Valid signal

A signal to be used for data transmission. A valid signal for a demand signal.

11 MP3 ripping Converting digital data to MP3 format.

12 CODEC Executes data encode and decode using encoding system.

Indicates MP3 Decoder and MP3 Encoder.

13 XT1 / XTRTC External clock input pin.

14 BCK (BCLK) Bit Clock. A signal to execute accurate transmission in accordance with the data timing.

15 MCLK Master Clock. An operation reference clock signal of the digital signal.

16 DOUT Digitalized audio data bit string.

17 TRIG (Trigger) Data transmission timing.

18 DMA Direct Memory Access. A method of transferring data without using CPU.

19 Slot The number of times that BCLK is counted for one LRCLK period.

20 IIR Infinite impulse response.

21 Shelving filter Adds shelf-formed gain to low (high) pass of the amplitude characteristic.

22 Peaking filter Creates peak and dip to the amplitude characteristic. This is used for the volume control per frequency.

23 Notch filter This filter gives steep decrement to specific frequencies.

24 De-emphasis Restores high pass level in order to reproduce audio data

25 ***DEC Indicates a common module which is placed in between C buffer and D buffer (e.g. volume)

26 ***SP0 Indicates a common module which is placed in between PCMSP0 and E buffer (e.g. volume)

27 ***PS0 Indicates a common module which is placed in between F buffer and PCMPS0 (e.g. volume)

28 ***SP1 Indicates a common module which is placed in between PCMSP1 and G buffer (e.g. volume)

29 ***PS1 Indicates a common module which is placed in between H buffer and PCMPS1 (e.g. volume)

30 One-shot reset Resets for a period of one clock

31 CRC Cyclic Redundancy Check. It is a type of error-detecting code.

32 Ancillary data Attached data.

33 L/R mode A mode to use L channel or R channel as a quantizing data

34 MS ONLY mode A mode to use the sum difference of L and R channels as a quantizing data

35 MSB Most significant bit.

36 LSB Least significant bit.

37 Over sampling Inserts high sampling frequency signals

38 Anti-aliasing filter Filtering process to prevent folding noise (aliasing) during sampling or down-sampling process.

39 VBR Variable bit rate. One of a method of bit rate change per second at the time of audio compression.

40 Polling Polling. A method of processing when a certain condition is met.

41 PWM Pulse width modulation. A type of modulation method which makes change in the pulse wave duty ratio for the modulation.

(14)

1 A u d io M o d u l e

1 - 1 I n t r o d u c t i o n

This chapter provides the brief summary of Audio Module in the sections below:

 About the Audio Module

(15)

1 - 1 - 1 Ab o u t t h e Au d i o M o d u l e

Here is the function outline of Audio Module.

1 - 1 - 1 - 1 F e a t u r e s

 256Fs-compliant (256/384Fs switching exists as an IP but this device is fixed to 256Fs.

There is a portion with 384 fs)

 MP3 hardware encoder/decoder - MP3 MPEG1, MPEG2, MPEG2.5

Corresponding sampling rate: 8 / 11.025 / 12 / 16 / 22.05 / 24 / 32 / 44.1 / 48 kHz.

Corresponding bit rate: 8 to 320 kbps (decoder: VBR-compliant).

 Various Audio function - 6 band equalizer (EQ3)

Equalizer characteristic can be changed by the coefficient setting.

(Can be allocated for Play and Record; commonly used).

- Digital volume, digital mute

Rate of variability can be either dB/Linear.

- Level meter - Audio timer

LR clock count and interrupt generation function.

- 16/24/32 bit ~192 kHz PCM I/O interface (2 ch) Master/Slave, I2S compliant

- Synchronous sampling rate converter (Hereinafter referred to as the SSRC).

Convertible within the range of ×0.25 ~ ×64.

- Asynchronous sampling rate converter (Hereinafter referred to as the ASRC).

Capable of adjusting clock error between devices at Audio streaming (e.g. for Bluetooth).

- BEEP

Frequency can be modified with the register settings.

- Digital mic interface (2 ch x 2).

Selects 2 ch x 1 system from 2 ch x 2 systems.

- Embedded AD converter D-class amp for 16 bit audio (Requires external LC LPF)

(16)

1 - 2 F u n c t i o n a l O v e r vi e w

This chapter provides overview of the functional blocks used for the Audio Module configuration in the sections below:

 Functional description

 Operation

(17)

1 - 2 - 1 F u n c t i o n a l d e s c r i p t i o n

MCLK0/

BCK0/

LRCK0 Internal

Bus

MP3 Encoder

MP3 Decoder

SSRC

PCM output

VOLUME (PS0) 32

VOLUME (SP0)

DIN0 (PCM input)

DOUT0 (PCM output) PCM

PS0 METER

(SP0)

BEEP 24

MUTE (PS0)

PCM SP0

METER (PS0)

PCM input S

I N S E L1

0

SINGEN VOLUME

(DEC)

32

AudioTimer0 LRCK0 METER

(DEC)

MUTE (DEC)

EQ3 EQ3 64KB SRAM divided into

A ~ N Audio Buffers by register settings

16bit Audio DAC

Class-D AMP 32

0

1

24

24

8

24 16

16 8

P C M S E L0

1 Digtal

Mic

DMCKO0 DMDIN0

32 RAM

RAM

RAM RAM A buffer

B buffer

C buffer

D buffer

E buffer

F buffer

K buffer

L buffer Dredirect Eredirect Gredirect

Eredirect Gredirect

Eredirect Dredirect Gredirect

Dredirect Eredirect

M buffer

N buffer Dredirect Eredirect

32 Jredirect

Jredirect

Jredirect

Gredirect

Gredirect G buffer

H buffer

Gredirect Dredirect Eredirect Jredirect

32

PCM output PCM PS1 PCM SP1

PCM input DIN1 (PCM input)

DOUT1 (PCM output) Lredirect

Lredirect

Lredirect

Lredirect

Jredirect

Jredirect I buffer

J buffer Dredirect Eredirect Gredirect Lredirect Nredirect

Nredirect

Nredirect

Nredirect

Nredirect

Nredirect

Lredirect

ASRC VOLUME

(SP1)

METER (SP1)

VOLUME (PS1)

METER (PS1)

24

S E L DMCKO1DMDIN1 24

32

32 32 32

32 32 Bit conv Bit convBit conv

Bit conv

Bit conv RAM Bit conv

Bit conv RAM Bit conv

RAM

Bit conv Bit conv

RAM

Bit conv

RAM

Bit conv

Bit conv 32Bit conv

RAM Bit conv

RAM Bit conv

RAM Bit conv 32Bit conv

RAM Bit conv 32Bit conv

24

RAM Bit conv 32Bit conv

BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO BIT1-0、MONO

BIT1-0、MONO BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO

BIT1-0、MONO BIT1-0、MONO CBIT1-0、CMONO

CBIT1-0、CMONO

MCLK1/

BCK1/

LRCK1

AudioTimer1 LRCK1

LOUT ROUT DWNMIX

(PS0)

DWNMIX (PS1)

D E C S E L

Figure ‎1-1

* : EQ3 can be switched at the solid line and dotted line.

(18)

1 - 3 P rog rammer ’s M od el

This chapter contains Audio Module register information and other information necessary for the register setup using microcontrollers in the sections below:

 About the programmer’s model

 Summary of Audio Module registers

(19)

Audio module function manuals are prepared for each IP as listed below. This manual includes information about functions that are unrelated to this listed IPs.

No IP Ver. Title (file name)

1 Audio Buffer 1.0 Audio Buffer User Manual

(ProgrammersModel_AudioBufferv1.0_Eng.docx)

2 SSRC 1.0 SSRC User Manual

(ProgrammersModel_SSRCv1.0_Eng.docx)

3 EQ3 2.0 EQ3 User Manual

(ProgrammersModel_EQ3v2.0_Eng.doc)

4 BEEP 2.0 BEEP User Manual

(ProgrammersModel_BEEPv2.0_Eng.doc)

5 DAC 2.0 DAC User Manual

(ProgrammersModel_DACv2.0_Eng.doc)

6 Damp CTL 2.0 DAMPCTL User Manual

(ProgrammersModel_DAMPCTLv2.0_Eng.doc) 7 Digital Mic 2.0 Digital Mic Interface User Manual

(ProgrammersModel_DGMIC_v2.0_Eng.doc) 8 PCM Clock Generator 2.0 PCKGEN User Manual

(ProgrammersModel_PCKGEN_v2.0_Eng.doc) 9 Audio Timer0

Audio Timer1

2.0 Audio Timer UserManual

(ProgrammersModel_ATMv2.0_Eng.doc)

10 SINGEN 2.0 SINGEN User Manual

(ProgrammersModel_SINGENv2.0_Eng.doc)

11 ASRC 1.1 ASRC User Manual

(ProgrammersModel_ASRCv1.1_Eng.docx)

12 MP3 Decoder 2.0 MP3 Decoder User Manual

(ProgrammersModel_MP3DECv2.0_Eng.doc)

13 MP3 Encoder 2.0 MP3 Encoder User Manual

(ProgrammersModel_MP3ENCv2.0_Eng.doc) 14 Audio Control 2.1 Audio Control User Manual

(ProgrammersModel_AUDCTRLv2.1_Eng.doc)

15 PCMSP0

PCMSP1

2.0 PCMSP User Manual

(ProgrammersModel_PCMSPv2.0_Eng.doc)

16 PCMPS0

PCMPS1

2.0 PCMPS User Manual

(ProgrammersModel_PCMPSv2.0_Eng.doc)

17 MUTE DEC 2.0 MUTE DV User Manual

(ProgrammersModel_MUTEDVv2.0_Eng.doc)

18 MUTE PS0 2.0 MUTE User Manual

(ProgrammersModel_MUTEv2.0_Eng.doc)

19 VOLUME DEC

VOLUME SP0 VOLUME PS0 VOLUME SP1 VOLUME PS1

2.1 VOLUME User Manual

(ProgrammersModel_VOLUMEv2.1_Eng.doc)

20 METER DEC

METER SP0 METER PS0 METER SP1 METER PS1

2.0 METER User Manual

(ProgrammersModel_METERv2.0_Eng.doc)

*1:In this device, the following parameter which is mentioned in each IP user manual is fixed. Making

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changes to the Reserved registers in each user manual may cause irregular operation. Therefore, don’t change the initial setting of those Reserved registers without designation in particular.

BUSSEL:0 (32-bit bus access) Register access bus width setting PCM_WIDTH / PCM_WIDTH2:In each IP PCM data bus width setting

*2:The following specification are for this device. Numbers in () indicates above mentioned item numbers.

(3) EQ3 User Manual

 80 cycles are needed for the IP to process one sample (2ch). When using PCM0 in the Slave mode, the Audio clock (256fs) must operate in faster frequency than the speed of Sampling frequency x 80.

 PCM_WIDTH (PCM data bus width):24 (4) BEEP User Manual

 PCM_WIDTH2 (PCM data bus width):32

 PCM_WIDTH (BEEP sound data bus width):24 (5) DAC User Manual

 XSELHQ of DAC step select register (0x10) listed in this IP specification can be used with putting together with DAMPCKSEL (bit11) of Audio Module Selector for AudioControl Users Manual. If you select the 17 quantization, set this bit to “1” which is 768fs.

 Bit clock is 48fs only.

 PCM_WIDTH (PCM data bus width):24 (6) DAMPCTL User Manual

 Function clock is necessary to reflect the settings to D-class Amp.

(7) DGFIL User Manual

 Digital filter setting must be done after the reset and before supplying FCE_DGMIC(bit7) that is digital mic function clock (setting it to “1”) of Clock enable control register (0x4000) in the Audio Control User Manual. Changing register while supplying function clock may cause

irregular operation.

 LRCKFS listed in the IP specification indicates PCM control register’s DGMICFS (bit21-20) in the Audio Control User Manual.

 PCM_WIDTH (PCM data bus width):24

 When stopping the function clock supply (setting “0”), DMCKO will stop at either “H” or “L”

according to the stop timing. DMCKO will become ”H” by the reset.

(8) PCKGEN User Manual

 Please note that when output stop (“1”) is set for LRCKSTOP (bit0) of PCM clock control register (0x00), Internal data transfer will stop regardless of the Master/Slave status.

 Noise may be generated when stopping each PCM clock; please set Mute before stopping each PCM clock.

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 Slot error will occur on the PCK0SLTERR (bit1) of Slave clock error status register (0x0C) if it detects a slot count which is different from what is set for the PCM0SLT (bit5-4) of PCM control register (0x504) in the AudioControl Users Manual.

 Slot error will occur on the PCK1SLTERR (bit4) of Slave clock error status register (0x0C) if it detects a slot count which is different from what is set for the PCM1SLT (bit13-12) of PCM control register (0x504) in the AudioControl Users Manual.

 To operate PCM0 in the Slave mode, set 0x0001 to bit14-0 of the Reserved register (0x14).

To operate PCM1 in the Slave mode, set 0x0001 to bit30-16 of the Reserved register (0x14).

(9) ATM User Manual

 There is a possibility of missing interrupt detection when the ATMINTMOD (bit8) of ATM interrupt register (0x10) is set to “1” so please use “0”.

 AudioTimer0 is counting PCM0 I/F sampling period.

 AudioTimer1 is counting PCM1 I/F sampling period.

(10) SINGEN User Manual

 PCM_WIDTH (PCM data bus width):24

 Operation sampling frequency of SINGEN will operate with the sampling frequency which was generated for PCM0 Master mode.

(12) MP3DEC User Manual

 Using a data which the MP3 data is in the range from less than -75dB to silence and fits in the full band (i.e. White noise) may cause an unusual noise.

(13) MP3ENC User Manual

 Setting “L” or stopping the encoding process of ENCSTART (bit0) of MP3 encoder control register (0x04) at the end of MP3 encoding process will start completion process inside the chip. Once that process is complete and everything is written into the Audio buffer, then the BUFEND (bit0) of MP3 encoder end status register (0x1C) will be set to “1”. MP3 encoder complete interrupt will be generated at this time.

(14) AudioControl User Manual

 In case of using PCM0 P/S while using DAC, PCM0 P/S will not output normal data if a different sampling frequency is used for the operation.

 WAITCTL (bit0) of D-buffer wait control register (0x700) must be set to “1” in case of using VOLUME DEC.

 Register blocks in the SSRC module will reset along with the reset if RSTSSRC (bit4) of Audio reset register (0x0004) is set to “0”.

(15) PCMSP User Manual

 Register addresses are assigned to an individual IP. In this device, PCM0 input and PCM1 input will have different addresses.

PCMSP0 (PCM0 input):AudioControl address + 0x100 PCMSP1 (PCM1 input):AudioControl address + 0x120

Please refer to the Audio Control User Manual’s Audio control registers for the full list.

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 PCM_WIDTH (PCM data bus width):32 (16) PCMPS User Manual

 Register addresses are assigned to an individual IP. In this device, PCM0 output and PCM1 output will have different addresses.

PCMPS0 (PCM0 output):AudioControl address + 0x110 PCMPS1 (PCM1 output):AudioControl address + 0x130

Please refer to the Audio Control User Manual’s Audio control registers for the full list.

 PCM_WIDTH (PCM data bus width):32 (17) MUTE DV User Manual

 Automatic mute control pins are connected as follows:

 (Signals listed below can be masked by MSK3-0(bit19-16) of Automatic mute control register (0x20C)).

ATMUTEON0: MP3 decoder error ATMUTEON1: Not in use

ATMUTEON2: Not in use ATMUTEON3: Not in use

 Register addresses are assigned to an individual IP.

AudioControl address + 0x400

Please refer to Audio Control User Manual’s AudioControl registers for the full list.

 There is an error processing function which activates by having no data for a fixed intervals with the setting of MUTE wait control register (0x204) AUTOSET (bit0) and MANU11-0 (bit27-16). But this function is not used for this device so please do not change the setting.

There is a possibility of having abnormal operation if it does not have appropriate setting.

 PCM_WIDTH (PCM data bus width):24 (18) MUTE User Manual

 Automatic mute control pins are connected as follows:

(Signals listed below can be masked by MSK3-0(bit19-16) of Automatic mute control register (0x20C)).

ATMUTEON0: MP3 decoder error ATMUTEON1: Not in use

ATMUTEON2: Not in use ATMUTEON3: Not in use

 Register addresses are assigned to an individual IP.

AudioControl address + 0x420

Please refer to Audio Control User Manual’s AudioControl registers for the full list.

 It will require 60 cycles for an IP to process 1 sample (2ch). In case of using PCM0 output in the slave mode, the Audio clock (256fs) must operate in faster speed than the sampling frequency x 60.

 PCM_WIDTH (PCM data bus width):32

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(19) VOLUME User Manual

 Register addresses are assigned for an individual IP. This device has different addresses for Decoder, PCM0 input, PCM0 output, PCM1 input, and PCM1 output.

VOLUME DEC (for decoder):AudioControl address + 0x300 VOLUME SP0 (PCM0 input):AudioControl address + 0x320 VOLUME PS0 (PCM0 output):AudioControl address + 0x340 VOLUME SP1 (PCM1 input):AudioControl address + 0x360 VOLUME PS1 (PCM1 output):AudioControl address + 0x380

Please refer to Audio Control User Manual’s AudioControl registers for the full list.

 It will require 72 cycles for an IP to process 1 sample (2ch). D-buffer wait control register (0x4700) must be set for an adjustment in case of using VOLUME for decoder. When

using PCM0/1 input/output VOLUME and PCM in the Slave mode, Audio clock (256fs) must be operating in faster speed than the sampling frequency x 72.

 PCM_WIDTH (PCM data bus width) For decoder:24

PCM0 input, PCM0 output, PCM1 input, PCM1 output:32 (20) METER User Manual

 Register addresses are assigned for an individual IP. This device has different addresses for Decoder, PCM0 input, PCM0 output, PCM1 input, and PCM1 output.

METER DEC (for decoder):AudioControl address + 0x400 METER SP0 (PCM0 input):AudioControl address + 0x430 METER PS0 (PCM0 output):AudioControl address + 0x460 METER SP1 (PCM1 input):AudioControl address + 0x490 METER PS1 (PCM1 output):AudioControl address + 0x4C0

Please refer to Audio Control User Manual’s AudioControl registers for the full list.

 In this device, monitoring range of Lch METER level monitor register, Rch METER level monitor register and the setting range of Lch METER ThresHold register and Rch METER ThresHold register are as follows:

For decoder:

Lch/Rch METER level monitor register = Bit23-0 Lch/Rch METER ThresHold register = Bit22-0 PCM0 input, PCM0 output, PCM1 input PCM1 output:

Lch/Rch METER level monitor register = Bit31-0 Lch/Rch METER ThresHold register = Bit30-0

 PCM_WIDTH (PCM data bus width) For decoder:24

PCM0 input, PCM0 output, PCM1 input, PCM1 output:32

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1 - 3 - 1 About the programmer ’s model

Audio Module base address is not fixed and will vary by the system implementation.

Please refer to the System specifications for more information about the base address.

Offset is fixed for all registers.

1 - 3 - 2 S u m m a r y o f Au d i o M o d u l e r e g i s t e r s

Table 1-1 Audio Module registers

Address Module Name Description

BaseAddress+0x4000 Audio Control Audio and other function control

BaseAddress+0x3000 MP3 Encoder MP3 encoder control

BaseAddress+0x2000 MP3 Decoder MP3 decoder control

BaseAddress+0x1F00 UNDEFINED ABORT area

BaseAddress+0x1E00 UNDEFINED ABORT area

BaseAddress+0x1D00 UNDEFINED ABORT area

BaseAddress+0x1C00 UNDEFINED ABORT area

BaseAddress+0x1B00 UNDEFINED ABORT area

BaseAddress+0x1A00 ASRC Asynchronous SRC control

BaseAddress+0x1900 SINGEN SINE wave generator

BaseAddress+0x1800 AudioTimer1 Audio Timer control (for PCM1) BaseAddress+0x1700 AudioTimer0 Audio Timer control (for PCM0) BaseAddress+0x1600 PCM Clock Generator PCM clock generator

BaseAddress+0x1500 Digital Mic Digital mic input control

BaseAddress+0x1400 Damp CTL Damp control

BaseAddress+0x1300 DAC DAC control

BaseAddress+0x1200 BEEP BEEP control

BaseAddress+0x1100 EQ3 EQ3 control

BaseAddress+0x1000 SSRC SSRC control

BaseAddress+0x0000 Audio Buffer Audio buffer control

Attention) Audio clock must be supplied when accessing to the Audio module (excluding Audio buffer).

Please refer to the ProgrammersModel_OSC for Audio clock supplying method.

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1 - 4 O p e r a t i o n

1 - 4 - 1 O p e r a t i o n S e t t i n g D e s c r i p t i o n s

Here are the lists of operation setting.

1. Audio play

MP3 play (MP3 standard compliant)

PCM play (SSRC usage route, data set to Audio C-buffer) * : PCM data width is 24-bit.

PCM play (Not using SSRC route, data set to Audio F-buffer) * : PCM data width is 24-bit when using EQ3.

PCM play 2 outputs

* : 2 outputs using 1 PCM clock.

2. Audio recording PCM recording

PCM recording 2 inputs

* : 2 inputs using 1 PCM clock 3. Ripping

MP3 ripping (quad data rate compliant) 4. Speech-rate conversion

MP3 speech-rate conversion PCM speech-rate conversion

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1 - 4 - 1 - 1 O p e r a t i o n C o n t r o l S e t t i n g

Here are the controls necessary for Reproduction and Record:

(0) PCM I/F, Digital mic, and between DAC and Audio buffer (the whole)

Figure ‎1-2

(*1) PCM0 Master/Slave selection

PCM0MODE (bit17) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*2) PCM0 Master-side LRCK0/BCK0/MCLK0 and internal sampling frequency division setting LRCK0FS (bit2-0) of the AUDCTRL’s PCM control register [0x4006_4504]

(*3) MCLK0 output frequency setting

FS0SEL (bit8) of the PCKGEN’s MCLK control register [0x4006_1608]

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(*4) MCLK0 division setting

LRCK0FS_DIV (bit4) of the PCKGEN’s MCLK control register [0x4006_1608]

(*5) PCM1 Master/Slave selection

PCM1MODE (bit19) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*6) PCM1 master-side LRCK1/BCK1/MCLK1 and internal sampling frequency division setting LRCK1FS (bit10-8) of the AUDCTRL’s PCM control register [0x4006_4504]

(*7) MCLK1 output frequency setting

FS1SEL (bit9) of the PCKGEN’s MCLK control register [0x4006_1608]

(*8) MCLK1 division setting

LRCK1FS_DIV (bit5) of the PCKGEN’s MCLK control register [0x4006_1608]

(*9) PCM clock selection for PCMSP0

PCM0COMI (bit8) of the PCKGEN’s PCM clock control register [0x4006_1600]

(*10) PCM clock selection for PCMPS0

PCM0COMO (bit9) of the PCKGEN’s PCM clock control register [0x4006_1600]

(*11) PCM clock selection for PCMSP1

PCM1COMI (bit10) of the PCKGEN’s PCM clock control register [0x4006_1600]

(*12) PCM clock selection for PCMPS1

PCM1COMO (bit11) of the PCKGEN’s PCM clock control register [0x4006_1600]

(*13) Division setting for Digital mic internal sampling frequency

Combination of LRCK2FS(bit17-16) and DGMICFS0(bit21-20) of the AUDCTRL’s PCM control register [0x4006_4504]

(*14) Division setting for DAC internal sampling frequency

Combination of LRCK2FS(bit17-16) and DACFS0(bit23-22) of the AUDCTRL’s PCM control register [0x4006_4504]

(*15) Digital mic and PCMSP0 input data and internal signal selection

PCMSEL (bit4) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*16) Internal signal selection of DAC and PCMPS0

DACEN (bit8) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*17) Data selection of Input data and Sine wave data

SINSEL (bit5) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*18) Selection of the Digital mic pin to be in use

System Controller’s Port Function Switching register [0x4008_0400 – 0x4008_0414]

*A : Assuming the internal signal selected in (*11) above is used for each IP when SINSEL is selecting an input data from outside (when using PCM0 clock).

Attention) Digital mic and DAC operation cannot be executed at the sampling frequency of more than 48 kHz. When using DAC, be sure to set the same sampling frequency when outputting data from PCMPS0.

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(1) Between Digital mic/PCMSP0 and Buffer “E”

Figure ‎1-3

(*1) PCM0 Master/Slave selection

PCM0MODE (bit17) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*2) PCM0 Master-side LRCK0/BCK0/MCLK0 and Internal sampling frequency division setting LRCK0FS (bit2-0) of the AUDCTRL’s PCM control register [0x4006_4504]

(*3) MCLK0 output frequency setting

FS0SEL (bit8) of the PCKGEN’s MCLK control register [0x4006_1608]

(*4) MCLK0 division setting

LRCK0FS_DIV (bit4) of the PCKGEN’s MCLK control register [0x4006_1608]

(*5) PCM1 Master/Slave selection

PCM1MODE (bit19) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*6) PCM1 Master-side LRCK1/BCK1/MCLK1 and Internal sampling frequency division setting LRCK1FS (bit10-8) of the AUDCTRL’s PCM control register [0x4006_4504]

(*7) MCLK1 Output frequency setting

FS1SEL (bit9) of the PCKGEN’s MCLK control register [0x4006_1608]

(*8) MCLK1 division setting

LRCK1FS_DIV (bit5) of the PCKGEN’s MCLK control register [0x4006_1608]

(*9) PCM clock selection for PCMSP0

PCM0COMI (bit8) of PCKGEN’s PCM clock control register [0x4006_1600]

(*13) Digital mic internal sampling frequency division setting

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Combination of LRCK2FS (bit17-16) and DGMICFS0 (bit21-20) of the AUDCTRL’s PCM control register [0x4006_4504]

(*15) Digital mic and PCMSP0 input data, and Internal signal selection

PCMSEL (bit4) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*17) Data selection of Input data and Sin wave data

SINSEL (bit5) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*18) Digital mic pin selection for use

System Controller’s Port Function Switching register [0x4008_0400 – 0x4008_0414]

Attention) Digital mic is not operative above 48 kHz sampling frequency.

(30)

(2) Between Buffer “F” and DAC/PCMPS0

Figure ‎1-4

(*1) PCM0 Master/Slave selection

PCM0MODE (bit17) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*2) PCM0 Master-side LRCK0/BCK0/MCLK0 and Internal sampling frequency division setting LRCK0FS (bit2-0) of the AUDCTRL’s PCM control register [0x4006_4504]

(*3) MCLK0 output frequency setting

FS0SEL (bit8) of the PCKGEN’s MCLK control register [0x4006_1608]

(*4) MCLK0 division setting

LRCK0FS_DIV (bit4) of the PCKGEN’s MCLK control register [0x4006_1608]

(*5) PCM1 Master/Slave selection

PCM1MODE (bit19) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*6) PCM1 Master-side LRCK1/BCK1/MCLK1 and Internal sampling frequency division setting LRCK1FS (bit10-8) of the AUDCTRL’s PCM control register [0x4006_4504]

(*7) MCLK1 Output frequency setting

FS1SEL (bit9) of the PCKGEN’s MCLK control register [0x4006_1608]

(*8) MCLK1 division setting

LRCK1FS_DIV (bit5) of the PCKGEN’s MCLK control register [0x4006_1608]

(*10) PCM clock selection for PCMPS0

PCM0COMO (bit9) of the PCKGEN’s PCM clock control register [0x4006_1600]

(*14) DAC internal sampling frequency division setting

Combination of LRCK2FS (bit17-16) and DACFS0 (bit23-22) of the AUDCTRL’s PCM control

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register [0x4006_4504]

(*16) Internal signal selection of DAC and PCMPS0

DACEN (bit8) of the AUDCTRL’s Audio module select register [0x4006_401C]

Attention) The same sampling frequency shall be used for PCMPS0 output when using DAC. However, it will not operate at the sampling frequency of 48 kHz or more when using DAC.

(32)

(3) Between PCMSP1 and Buffer “G”

Figure ‎1-5

(*1) PCM0 Master/Slave selection

PCM0MODE (bit17) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*2) PCM0 Master-side LRCK0/BCK0/MCLK0 and Internal sampling frequency division setting LRCK0FS (bit2-0) of the AUDCTRL’s PCM control register [0x4006_4504]

(*3) MCLK0 Output frequency setting

FS0SEL (bit8) of the PCKGEN’s MCLK control register [0x4006_1608]

(*4) MCLK0 division setting

LRCK0FS_DIV (bit4) of the PCKGEN’s MCLK control register [0x4006_1608]

(*5) PCM1 Master/Slave setting

PCM1MODE (bit19) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*6) PCM1 Master-side LRCK1/BCK1/MCLK1 and Internal sampling frequency division setting LRCK1FS (bit10-8) of the AUDCTRL’s PCM control register [0x4006_4504]

(*7) MCLK1 Output frequency setting

FS1SEL (bit9) of the PCKGEN’s MCLK control register [0x4006_1608]

(*8) MCLK1 division setting

LRCK1FS_DIV (bit5) of the PCKGEN’s MCLK control register [0x4006_1608]

(*11) PCM clock selection for PCMSP1

PCM1COMI (bit10) of the PCKGEN’s PCM clock control register [0x4006_1600]

*A : Assuming the internal signal selected in (*11) above is used for each IP when SINSEL is selecting

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an input data from outside (when using PCM0 clock).

(34)

(4) Between Buffer “H” and PCMPS1

Figure ‎1-6

(*1) PCM0 Master/Slave selection

PCM0MODE (bit17) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*2) PCM0 Master-side LRCK0/BCK0/MCLK0 and Internal sampling frequency division setting LRCK0FS (bit2-0) of the AUDCTRL’s PCM control register [0x4006_4504]

(*3) MCLK0 Output frequency setting

FS0SEL (bit8) of the PCKGEN’s MCLK control register [0x4006_1608]

(*4) MCLK0 division setting

LRCK0FS_DIV (bit4) of the PCKGEN’s MCLK control register [0x4006_1608]

(*5) PCM1 Master/Slave selection

PCM1MODE (bit19) of the AUDCTRL’s Audio module select register [0x4006_401C]

(*6) PCM1 Master-side LRCK1/BCK1/MCLK1 and Internal sampling frequency division setting LRCK1FS (bit10-8) of the AUDCTRL’s PCM control register [0x4006_4504]

(*7) MCLK1 Output frequency setting

FS1SEL (bit9) of the PCKGEN’s MCLK control register [0x4006_1608]

(*8) MCLK1 division setting

LRCK1FS_DIV (bit5) of the PCKGEN’s MCLK control register [0x4006_1608]

(*12) PCM clock selection for PCMPS1

PCM1COMO (bit11) of the PCKGEN’s PCM clock control register [0x4006_1600]

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1 - 4 - 1 - 2 E x a m p l e o f O p e r a t i o n C o n t r o l S e t t i n g

Example of a control method is shown below:

(1) Operating PCM0 in Master mode, PCM1 and External CODEC in Slave mode:

VOLUME (SP0)

DIN0 (PCM input) METER

(SP0)

PCM SP0 S

I N S E L1

0

SINGEN 32

EQ3

32 P C M S E L0

1 DigtalMic

DMCKO0 DMDIN0

E buffer

S E

L DMCKO1

DMDIN1 24

32 32

RAM Bit conv

BIT1-0, MONO

LRCK0

BCK0

LRCK1

BCK1 (*18) (*15)

(*17)

(*13)

(*9) (*1)

(*2)

(*5) (*6)

PCM input

*A

24

32 PCM output

VOLUME (PS0)

DOUT0 (PCM output) PCM

PS0 MUTE BEEP

(PS0)

METER (PS0) EQ3

F buffer

Eredirect Dredirect

Gredirect Jredirect Lredirect Nredirect

32 Bit conv RAM Bit conv

BIT1-0, MONO

(*14)

G buffer

32 PCM

SP1

PCM input DIN1 (PCM input) VOLUME

(SP1)

METER (SP1)

32

RAM Bit conv

BIT1-0, MONO

32 H buffer

Gredirect Dredirect Eredirect

Jredirect

PCM output PCM PS1

DOUT1 (PCM output) Lredirect

Nredirect

VOLUME (PS1)

METER (PS1)

32

Bit conv RAM Bit conv BIT1-0, MONO

(*12)

AudioTimer0

AudioTimer1

MCLK0

MCLK1 (*3)

(*4)

(*7) (*8) 256fs clock

384fs clock

(*2)

256fs clock 384fs clock

(*6)

LOUT ROUT Internal Signal

Select

PCM master Clock &

Internal Signal Generator DigitalMic Fs Divide

PCM0 master/slave

Select

Internal Signal Generator for slave

Clock Observe

PCM0 Fs Divide

MCLK0 Fs Select

MCLK0 Fs Divide 1 MCLK0 Fs Divide 0 Sign al

Sele ct for PCM0 inpu t

Signal Select for PCM0

output DAC Fs Divide

Internal Signal Select

16bit Audio DAC

Class-D AMP

PCM1 master/slave

Select

Internal Signal Generator for slave

Clock Observe MCLK1 Fs Select

MCLK1 Fs Divide 1 MCLK1 Fs Divide 0

PCM1 Fs Divide Signal Select

for PCM1 input

Sign al Sele ct for PCM1 inpu t

DOWNMIX (PS1) DOWNMIX

(PS0)

External Audio Codec (*15)

(*10)

(*16)

(*11)

Figure ‎1-7

- Set PCM0 Master mode (*1), PCM1 Slave mode (*5), Input data and Internal signals to PCMSP0 (*15), Internal signal for output to PCMPS0 (*16), and SIN data to be unused (*17).

AUDCTRL’s Audio module select register [0x4006_401C] = 0x0003_0000

- Set PCM0 Master-side LRCK0/BCK0/MCLK0 and Internal sampling frequency to 1/1fs(*2), PCM0 Bit clock (BCK0) to 64fs, and PCM1 bit clock (BCK1) to 64fs.

AUDCTRL’s PCM control register [0x4006_4504] = 0x0000_1010 - PCM0 output, PCM1 DOUT1 output

AUDCTRL’s PCM output enable control register [0x4006_4500] = 0x0000_008F

(36)

- set MCLK0 output frequency to 256fs(*3), divider to 1/1fs(*4).

PCKGEN’s MCLK control register [0x4006_1608] = 0x0000_0000 - Set PCM clock to be used for PCMSP0 and PCMPS0 to PCM0 (*9, *10), Set PCM clock to be used for PCMSP1 and PCMPS1 to PCM1(*11, *12).

PCKGEN’s PCM clock control register [0x4006_1600] = 0x0000_0000 - Set LRCK1 monitoring counter

PCKGEN’s LRCK control register [0x4006_1604] = 0x0181_0180 - Set Reserve register whne using PCM1 in the Slave mode.

PCKGEN’s Reserved register [0x4006_1614] = 0x0001_0001

- Set PCMSP0, PCMPS0, PCMSP1, PCMPS1 to I2S mode with 32 bit input/output.

PCMSP0’s PCM input control register [0x4006_4100] = 0x0000_0064 PCMPS0’s PCM output control register [0x4006_4110] = 0x0000_0064 PCMSP1’s PCM input control register [0x4006_4120] = 0x0000_0064 PCMPS1’s PCM output control register [0x4006_4130] = 0x0000_0064 - Selecting pins to use

System Controller’s Port Function Switching register 0[0x4008_0400] = 0xXXXX_XX3X System Controller’s Port Function Switching register 1[0x4008_0404] = 0xX155_X54X

Attention) Above mentioned circuit configuration and the setting values are an example use for the counter setting for LRCK1 monitoring.

参照

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