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## Application Note AN4138

### Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPS ^{TM} )

**Abstract**

This application note presents practical design consider- ations for battery chargers employing Green Mode FPS (Fairchild Power Switch). It includes designing the transformer and output filter, selecting the components and implementing constant current / constant voltage control.

The step-by-step design procedure described in this paper will help engineers design battery chargers more easily. In order to make the design process more efficient, a software design tool, FPS design assistant that contains all the equations described in this paper is also provided. The design procedure is verified through an experimental prototype converter.

Rev. 1.0.0

**1. Introduction**

As penetration rates of portable electronics devices such as cellular phones, digital cameras or PDAs have increased significantly, the demands for low cost battery chargers are rising these days. Fairchild Power Switch (FPS) reduces total component count, design size, weight and, at the same time increases efficiency, productivity, and system reliability when compared to a discrete MOSFET and controller or RCC switching converter solution. Table 1 shows the FPS lineup for a battery charger application. Figure 1 shows the schematic of the basic battery charger using FPS, which also serves as the reference circuit for the design process

described in this paper. An experimental flyback converter from the design example has been built and tested to show the validity of the design procedure.

**Table 1. FPS lineup for a battery charger **
**Figure 1. Basic Battery charger Using FPS**

**Np****N**_{S}

**R**_{sn}**C**_{sn}**-****V**_{sn}

**+****V**_{DC}

**+****-**

**AC line**

**D**_{sn}

**D**_{R}

**C**_{O}

**Drain**

**Vcc****GND****FB**

**FPS**

**N**_{a}**D**_{a}**R**_{a}

**C**_{a}

**H11A817A****R**_{d}**Bridge**

**rectifier**

**diode****V**_{O}

**L**_{P}

**C**_{P}

**C**_{B}**C**_{DC}

**I**_{O}

**I**_{O}^{ref}

**V**_{O}^{ref}

**Current****Controller**

**Voltage****Controller**

**V**_{bias}

**H11A817A**

Device Switching frequency

Current limit

Rdson (typ.) FSDH0165 100 kHz 0.35 A 15.6 Ω

FSD311 67 kHz 0.55 A 14 Ω

FSD200 134 kHz 0.32 A 28 Ω

FSD210 134 kHz 0.32 A 28 Ω

**2. Step-by-step Design Procedure**

**Figure 2. Flow chart of design procedure**

In this section, a design procedure is presented using the schematic of Figure 1 as a reference. Figure 2 illustrates the design flow chart. The detailed design procedures are as follows:

**(1) STEP-1 : Define the system specifications **
- Line voltage range (V_{line}* ^{min}* and V

_{line}*).*

^{max}- Line frequency (f* _{L}*).

- Maximum output power (P* _{o}*).

- Estimated efficiency (E* _{ff}*) : It is required to estimate the
power conversion efficiency to calculate the maximum input
power. In the case of a battery charger, the efficiency is
relatively low due to the low output voltage and loss in the
output current sense resistor. The typical efficiency is about
0.65-0.7.

With the estimated efficiency, the maximum input power is given by

**(2) STEP-2 : Determine DC link capacitor (C**_{DC}**) and the**
** DC link voltage range.**

It is typical to select the DC link capacitor as 2-3uF per watt of input power for universal input range (85-265Vrms) and 1uF per watt of input power for European input range (195V- 265Vrms). With the DC link capacitor chosen, the minimum link voltage is obtained as

where *D** _{ch}* is the DC link capacitor charging duty ratio
defined as shown in Figure 3, which is typically about 0.2
and P

*, V*

_{in}

_{line}*and f*

^{min}*are specified in step-1.*

_{L}The maximum DC link voltage is given as

where V_{line}* ^{max}* is specified in step-1.

**Figure 3. DC Link Voltage Waveform**
**1. Determine the system specifications**

**(V**_{line}^{min}**, V**_{line}^{max}**, f**_{L}**, Po, E**_{ff}**)**

**2. Determine DC link capacitor (C**_{DC}**)**
** and DC link voltage range**

**3. Determine the reflected output voltage**
**(V**_{RO}**)**

**6. Determine the proper core and the**
**minimum primary turns (N**_{p}^{min}**)**

**7. Determine the number of turns for each**
**output**

**8. Determine the wire diameter for each**
**winding**

**9. Choose the proper rectifier diode for each**
**output**

**10. Determine the output capacitor**

**11. Design the RCD snubber**

**12. Control Circuit design**
**5. Choose proper FPS considering input**

**power and I**_{ds}^{peak}

**4. Determine the transformer primary side**
**inductance (L**_{m}**) and maximum duty (D**_{max}**)**

**Is the winding window**
**area (Aw) enough ?**

**Design finished**

**Y**

**N**

**Is it possible to change the core ?**
**Y**

**N**

*P*_{in}*P*_{o}

*E*_{ff}*---*

*=* * (1)*

*V*_{DC}* ^{min}* 2⋅(

*V*

_{line}*)*

^{min}

^{2}

^{P}*⋅*

^{in}^{(}

^{1}^{–}

^{D}

^{ch}^{)}

*C*

*⋅*

_{DC}*f*

_{L}*---*–

*=* * (2)*

*V*_{DC}^{max}*=* *2V*_{line}^{max}* (3)*

**DC link voltage****Minimum DC link voltage**

**T**_{1}**T**_{2}**D**_{ch}** = T**_{1}** / T**_{2}

**= 0.2**

**(3) STEP-3 : Determine the reflected output voltage **
**(V**_{RO}**). **

When the MOSFET in the FPS is turned off, the input
voltage (V* _{DC}*) together with the output voltage reflected to
the primary (V

*) are imposed on the MOSFET as shown in Figure 4. After determining V*

_{RO}*the maximum nominal MOSFET voltage (V*

_{RO,}

_{ds}*) is obtained as*

^{nom}where V_{DC}* ^{max}* is specified in equation (3). The typical value
for V

*is 65-85V.*

_{RO}** Figure 4. The output voltage reflected to the primary**

**(4) STEP-4 : Determine the transformer primary side**
** inductance (L**_{m}**) and the maximum duty ratio (D**_{max}**).**

A Flyback converter has two kinds of operation modes;

continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The operation changes between CCM and DCM as the load condition and input voltage vary and each operation mode has their own advantages and disadvantages, respectively. The transformer size can be reduced using DCM because the average energy stored is lower compared to CCM. However, DCM inherently causes higher RMS current, which increases the conduction loss of the MOSFET and the current stress on the output capacitors.

For low power applications under 10W where the MOSFET conduction loss is not so severe, it is typical to design the converter to operate in DCM for the entire operating range, or to operate in CCM only for low input voltage conditions in order to minimize the transformer size.

** Figure 5. Simplified flyback converter**

The design procedures for CCM and DCM are slightly
different. Once the reflected output voltage (V_{RO}) is
determined in step-3, the flyback converter can be simplified
as shown in Figure 5 by neglecting the voltage drops in
MOSFET and diode.

For CCM operation, the maximum duty ratio is given by

where *V*_{DC}* ^{min}* and V

*are specified in equations (2) and step-3, respectively.*

_{RO}For DCM operation, the maximum duty ratio should be
determined as smaller than the value obtained in equation
(5). By reducing D* _{max}*, the transformer size can be reduced.

However, this increases the RMS value of the MOSFET
drain current and D* _{max}* should be determined by trade-off
between the transformer size and MOSFET conduction loss.

With the maximum duty ratio, the primary side inductance
(L* _{m}*) of the transformer is obtained. The worst case in
designing

*L*

*is full load and minimum input voltage*

_{m}*V*

_{ds}

^{nom}*=*

*V*

_{DC}

^{max}*+V*

_{RO}*(4)*

**-****V**_{R O}

**+****V**_{D C}

**+****-**

**D ra in**

**G N D****F P S**

**+****V**_{d s}

**-**

**0 V****V**_{D C}**V**_{R O}

**L**_{m}**V**_{DC}^{min}

**V**_{RO}

**I**_{ds}

**I**_{D}**I**_{m}

**I**_{m}

**I**_{m}

**I**_{ds}

**I**_{ds}**D**_{max}

**D**_{max}

**I**_{D}

**I**_{D}

min
*DC*
*RO*

*RO*

*V*
*V*

*V*

= +

min
*DC*
*RO*

*RO*

*V*
*V*

*V*

≤ +

*D*_{max}*V*_{RO}

*V*_{RO}*+V*_{DC}^{min}*---*

*=* * (5)*

condition. Therefore, L* _{m}* is obtained in this condition as

where V_{DC}* ^{min}* is specified in equation (2), D

*is specified in equation (5), P*

_{max}*is specified in step-1, f*

_{in}*is the switching frequency of the FPS device and K*

_{s}*is the ripple factor in full load and minimum input voltage condition, defined as shown in Figure 6. For DCM operation, K*

_{RF}*= 1 and for CCM operation K*

_{RF}*< 1. The ripple factor is closely related to the transformer size and the RMS value of the MOSFET current. In the case of low power applications such as battery chargers, a relatively large ripple factor is used in order to minimize the transformer size. It is typical to set K*

_{RF}*= 0.5- 0.7 for the universal input range and K*

_{RF}*= 1.0 for the European input range.*

_{RF}Once L* _{m}* is determined, the maximum peak current and RMS
current of the MOSFET in normal operation are obtained as

where *P** _{in}*, V

_{DC}*, D*

^{min}*and L*

_{max}*are specified in equations (1), (2), (5) and (6) respectively and f*

_{m}*is the FPS switching frequency.*

_{s}**Figure 6. MOSFET Drain Current and Ripple Factor (K**_{RF}**)**

** (5) STEP-5 : Choose the proper FPS considering input **
**power and peak drain current.**

With the resulting maximum peak drain current of the
MOSFET (I_{ds}* ^{peak}*) from equation (7), choose the proper FPS
of which the pulse-by-pulse current limit level (I

*) is higher than I*

_{over}

_{ds}*. Since FPS has ± 12% tolerance of I*

^{peak}*, there should be some margin in choosing the proper FPS device.*

_{over}** (6) STEP-6 : Determine the proper core and the minimum**
** primary turns.**

Table 2 shows the commonly used cores for battery chargers with output power under 10W. The cores recommended in table 2 are typical for the universal input range and 100kHz switching frequency.

With the chosen core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by

where L* _{m}* is specified in equation (6), I

*is the FPS pulse- by-pulse current limit level, A*

_{over}*is the cross-sectional area of the core as shown in Figure 7 and B*

_{e}*is the saturation flux density in tesla. Figure 8 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (B*

_{sat}*) decreases as the temperature goes high, the high temperature characteristics should be considered.*

_{sat}If there is no reference data, use B* _{sat}* =0.3~0.35 T. Since the
MOSFET drain current exceeds I

_{ds}*and reaches I*

^{peak}*in a transition or fault condition, I*

_{over}*is used in equation (11) instead of I*

_{over}

_{ds}*to prevent core saturation during transition.*

^{peak}**Figure 7. Window Area and Cross Sectional Area**
*L** _{m}* (

*V*

_{DC}*⋅*

^{min}*D*

*)*

_{max}

^{2}*2P*_{in}*f*_{s}*K*_{RF}*---*

*=* * (6)*

*I*_{ds}^{peak}*I** _{EDC}* ∆

^{I}*---2*
*+*

*=* * (7)*

*I*_{ds}^{rms}*3 I*( * _{EDC}*)

*∆*

^{2}

^{I}*---2*

^{2}

*+* *D*_{max}

*---3*

*=* ( )*8*

* * *I*_{EDC}*P*_{in}

*V*_{DC}* ^{min}*⋅

*D*

_{max}*---*

*=* * (9)*

* * ∆^{I}^{V}^{DC}

*min** D*_{max}*L*_{m}*f*_{s}*---*

*=* * (10)*

∆*I* *I**EDC*

*EDC*
*RF* *I*
*K* *I*

2

= ∆

**CCM operation : K**_{RF}** < 1**

∆*I* ^{I}^{EDC}

*EDC*
*RF* *I*
*K* *I*

2

= ∆

**DCM operation : K**_{RF}** =1***peak*

*I**ds*
*peak*

*I**ds*

*N*_{P}^{min}*L*_{m}*I*_{over}*B*_{sat}*A*_{e}

*---*×*10*^{6}* (turns)*

*=* * (11)*

### Aw Aw Aw Aw

### Ae Ae

### Ae Ae

**Figure 8. Typical B-H characteristics of ferrite core **
**(TDK/PC40) **

**Table 2. Typical cores for battery charger (For universal **
**input range, 5V output and fs=100kHz)**

**(7) STEP-7 : Determine the number of turns for each **
**output**

Figure 9 shows the simplified diagram of the transformer.

First, determine the turns ratio (n) between the primary side and the secondary side.

where *N** _{p}* and N

*are the number of turns for primary side and reference output, respectively, V*

_{s}*is the output voltage,*

_{o}*V*

*is the diode (D*

_{F}*) forward voltage drop and V*

_{R}*is the maximum voltage drop in the output current sensing resistor.*

_{sense}Then, determine the proper integer for N* _{s}* so that the
resulting

*Np is larger than N*

_{p}*obtained from equation (11).*

^{min}The number of turns for Vcc winding is determined as

where V_{cc}** is the nominal value of the supply voltage of the*
FPS device, and V* _{Fa}* is the forward voltage drop of D

*as defined in Figure 9. Since V*

_{a}_{cc}increases as the output load increases, it is proper to set V

_{cc}** as V*

*start voltage (refer to the data sheet) to avoid triggering the over voltage protection during normal operation.*

_{cc}**Figure 9. Simplified diagram of the transformer**

With the determined turns of the primary side, the gap length of the core is obtained as

where A* _{L}* is the AL-value with no gap in nH/turns

^{2}, Ae is the cross sectional area of the core as shown in Figure 8, L

*is specified in equation (6) and N*

_{m}*is the number of turns for the primary side of the transformer*

_{p}**(8) STEP-8 : Determine the wire diameter for each**
** winding based on the rms current of each output.**

The rms current of the n-th secondary winding is obtained as

where *V** _{RO}* and I

_{ds}*are specified in step-3 and equations (8), V*

^{rms}*is the output voltage, V*

_{o}*is the diode (D*

_{F}*) forward voltage drop and D*

_{R)}*is specified in equation (5).*

_{max}The current density is typically 5A/mm^{2} when the wire is
Core Cross sectional

area

Window area Output power
range
EE13-Z 17.1 mm^{2} 33.4 mm^{2} 3-5W
EI16-Z 19.8 mm^{2} 38.8 mm^{2} 3-5W
EE16-Z 21.7 mm^{2} 51.3 mm^{2} 5-10W
EI19-Z 24.0 mm^{2} 54.4 mm^{2} 5-10W

**100**
**500**

**400**

**300**

**200**

**800** **1600**

**0**
**0**

**M agnetic field H (A /m )**

**F****lux**** d****ensit****y**** B ****(m****T)**

**M agnetization C urves (typical)**
**M aterial :PC 40**

**100 ℃**℃℃℃
**120 ℃**℃℃℃
**60 ℃**℃℃℃
**25 ℃**℃℃℃

*n* *N*_{P}

*N*_{s}

*---* *V*_{R0}

*V*_{o}*+V*_{F}*+V*_{sense}*---*

*=* *=* * (12)*

*N*_{a}*V*_{cc}**+V*_{Fa}*V*_{o}*+V*_{F}*---*

*=* ⋅*N** _{s1}* (

*) ( )*

^{turns}*13*

**Np**

**N**_{S}**-**

**V**_{RO}**+**

**D**_{R}**N**_{a}

**D**_{a}**+**

**V**_{O}**-****+ V**_{F }**-****- V**_{Fa }**+**

**+****V**_{cc}^{*}

**-**

**- V**_{sense }**+**

)
( _{o}_{F}_{sense}

*s*
*p*

*RO* *V* *V* *V*

*N*

*V* = *N* + +

*G* *40*πA_{e} ^{N}^{P}

*2*

*1000L*_{m}

*---* *1*
*A*_{L}*---*

–

*=* (*mm*) ( )*14*

*I*_{s}^{rms}*I*_{ds}^{rms}*1*–*D*_{max}

*D*_{max}

*---* *V*_{RO}*V*_{o}*+V*_{F}

( )

*---*

⋅

*=* ( )*15*

long (>1m). When the wire is short with a small number of
turns, a current density of 6-10 A/mm^{2} is also acceptable.

Avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier.

For high current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect.

Check if the winding window area of the core, A* _{w}* (refer to
Figure 8) is enough to accommodate the wires. Because
bobbin, insulation tape and gaps between wires, the wire can
not fill the entire winding window area. Typically the fill
factor is about 0.15-0.2 for a battery charger. When
additional dummy windings are employed for EMI
shielding, the fill factor is reduced. The required winding
window area (A

*) is given by*

_{wr}where A* _{c}* is the actual conductor area and K

*is the fill factor.*

_{F}If the required window (A* _{wr}*) is larger than the actual window
area (A

*), go back to the step-6 and change the core to a bigger one. Sometimes it is impossible to change the core due to cost or size constraints. If so, go back to step-4 and reduce L*

_{w}*by increasing the ripple factor (K*

_{m}*) or reducing the maximum duty ratio. Then, the minimum number of turns for the primary (N*

_{RF}

_{p}*) of the equation (11) will decrease, which results in the reduced required winding window area (A*

^{min}*).*

_{wr}**(9) STEP-9 : Choose the rectifier diode in the secondary**
** side based on the voltage and current ratings.**

The maximum reverse voltage and the rms current of the
output rectifier diode (D* _{R}*) are obtained as

where *V*_{DC}* ^{max}*,

*D*

*and I*

_{max}

_{ds}*are specified in equations (3), (5) and (8), respectively, V*

^{rms}*is the output voltage, V*

_{o}*is the diode (D*

_{F}*) forward voltage and V*

_{R}*is the maximum voltage drop in the output current sensing resistor.*

_{sense}The typical voltage and current margins for the rectifier diode are as follows

where *V** _{RRM}* is the maximum reverse voltage and I

*is the average forward current of the diode.*

_{F}A quick selection guide for Fairchild Semiconductor rectifier diodes is given in table 3.

**Table 3. Fairchild Diode quick selection table **

**(10) STEP-10 : Determine the output capacitor **
**considering the voltage and current ripple.**

The ripple current of the output capacitor (C* _{o}*) is obtained as

where I_{o}* is the load current and I*_{D}^{rms}* is specified in equation*
(18). The ripple current should be smaller than the ripple
current specification of the capacitor. The voltage ripple on
the n-th output is given by

where C* _{o}* is the output capacitance, R

*is the effective series resistance (ESR) of the output capacitor, D*

_{c}*and I*

_{max}

_{ds}*are specified in equations (5) and (7), respectively, I*

^{peak }*and V*

_{o}*are the load current and output voltage, respectively, V*

_{o}*is the diode (D*

_{F}*) forward voltage and V*

_{R}*is the maximum voltage drop in the output current sensing resistor.*

_{sense}Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. Then, additional LC filter stages (post filter) can be used. When using the post filters, be careful not to place the corner frequency too low. Too low a corner frequency may make the system unstable or limit the control bandwidth. It is typical to set the corner frequency of the post filter at around 1/10~1/5 of the switching frequency.

**(11) STEP-11 : Design the RCD snubber. **

When the power MOSFET is turned off, there is a high voltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the FPS. Therefore, it is necessary to use an additional network to clamp the voltage.

The RCD snubber circuit and MOSFET drain voltage
waveform are shown in Figure 10 and 11, respectively. The
RCD snubber network absorbs the current in the leakage
inductance by turning on the snubber diode (D* _{sn}*) once the
MOSFET drain voltage exceeds the voltage of node X as
depicted in Figure 10. In the analysis of snubber network, it
is assumed that the snubber capacitor is large enough that its
voltage does not change significantly during one switching

*A*

_{w}_{r}

^{=}*A*

*⁄K*

_{c}

_{F}*(16)*

*V*_{D}*V*_{o}*V*_{DC}* ^{max}*⋅(

*V*

_{o}*+V*

_{F}*+V*

*)*

_{sense}*V*

_{RO}*---*
*+*

*=* ( )*17*

*I*_{D}^{rms}*I*_{ds}^{rms}*V*_{DC}^{min}

*V*_{RO}

*---* *V*_{RO}*V*_{o}*+V*_{F}*+V*_{sense}

( )

*---*

⋅

*=* ( )*18*

*V** _{RRM}*>

*1.3 V*⋅

_{D}*(19)*

*I*

*>*

_{F}*1.5 I*⋅

_{D}

^{rms}*(20)*

**Schottky Barrier Diode**

**Products** **V**_{RRM }**I**_{F}**Package**

SB340 40 V 3 A TO-210AD

SB350 50 V 3 A TO-210AD

SB360 60 V 3 A TO-210AD

*I*_{cap}^{rms}*=* (*I*_{D}* ^{rms}*)

*–*

^{2}*I*

_{o}

^{2}*(21)*

∆^{V}_{o}^{I}^{o}^{D}^{max}*C*_{o}*f*_{s}

*---* *I*_{ds}^{peak}*V*_{RO}*R*_{C}*V*_{o}*+V*_{F}*+V*_{sense}

( )

*--- (22)*
*+*

*=*

cycle. The snubber capacitor used should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable due to these reasons.

**Figure 10. Circuit diagram of the snubber network**

The first step in designing the snubber circuit is to determine
the snubber capacitor voltage at the minimum input voltage
and full load condition (V* _{sn}*). Once V

*is determined, the power dissipated in the snubber network at the minimum input voltage and full load condition is obtained as*

_{sn }where *I*_{ds}* ^{peak}* is specified in equation (8), f

_{s}is the FPS switching frequency, L

_{lk}is the leakage inductance, V

_{sn}is the snubber capacitor voltage at the minimum input voltage and full load condition, V

_{RO}is the reflected output voltage and R

_{sn}is the snubber resistor. V

_{sn}should be larger than V

_{RO}and it is typical to set V

_{sn }to be 2~2.5 times V

_{RO}. Too small a V

_{sn}results in a severe loss in the snubber network as shown in equation (23). The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted.

Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as

where f* _{s}* is the FPS switching frequency. In general, 5~10%

ripple of the selected capacitor voltage is reasonable.

The snubber capacitor voltage (V* _{sn}*) of equation (26) is for
the minimum input voltage and full load condition. When
the converter is designed to operate in CCM under this
condition, the peak drain current together with the snubber
capacitor voltage decrease as the input voltage increases as
shown in Figure 11. The peak drain current at the maximum

input voltage and full load condition (I_{ds2}^{peak}) is obtained as

where *P** _{in}*, and L

*are specified in equations (1) and (6), respectively and f*

_{m}*is the FPS switching frequency.*

_{s}The snubber capacitor voltage under maximum input voltage and full load condition is obtained as

where f* _{s}* is the FPS switching frequency, L

*is the primary side leakage inductance, V*

_{lk}*is the reflected output voltage and R*

_{RO}*is the snubber resistor.*

_{sn}**Figure 11. MOSFET drain voltage and snubber **
**capacitor voltage**

From equation (26), the maximum voltage stress on the internal MOSFET is given by

where V_{DC}* ^{max}* is specified in equation (3).

Check if V_{ds}* ^{max}* is below 85% of the rated voltage of the
MOSFET (BVdss) as shown in Figure 12. The voltage rating
of the snubber diode should be higher than BVdss. Usually,
an ultra fast diode with 1A current rating is used for the
snubber network.

**R**_{sn}**C**_{sn}**Np****-****V**_{sn}

**+****V**_{DC}

**+****-**

**D**_{sn}

**Drain**

**GND****FPS****C**_{DC}

**-****V**_{RO}

**+**

**+****V**_{ds}

**-****L**_{lk}**V**_{X}

**X**

*P** _{sn}* (

*V*

*)*

_{sn}

^{2}*R*

_{sn}*---*

*1*

*2---f*_{s}*L** _{lK}*(

*I*

_{ds}*)*

^{peak}

^{2}*V*

_{sn}*V*

*–*

_{sn}*V*

_{RO}*---*

*=* *=* * (23)*

∆^{V}_{sn}^{V}^{sn}*C*_{sn}*R*_{sn}*f*_{s}*---*

*=* * (24)*

*I*_{ds2}^{peak}*2 P*⋅ _{in}*f** _{s}*⋅

*L*

_{m}*---*

*=* * (25)*

*V*_{sn2}*V*_{RO}*+* (*V** _{RO}*)

^{2}*+2R*

_{sn}*L*

_{lk}*f*

*(*

_{s}*I*

_{ds2}*)*

^{peak}

^{2}*---2*

*=* * (26)*

**V**_{DC }^{min}

**V**_{RO}**V**_{sn}

**V**_{DC }^{max}

**V**_{RO}**V**_{sn2}

**I**_{ds}^{peak}

**I**_{ds2}^{peak}

**Minimum input voltage**

**& Full load**

**Maximum input voltage**

**& Full load****I**_{ds2}^{peak}** < I**_{ds}^{peak }**==> V**_{sn2 }**< V**_{sn}

*V*_{ds}^{max}*=* *V*_{DC}^{max}*+V*_{sn2}* (27)*

In the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered.

In the actual converter, the loss in the snubber network is less than the designed value due to this effects.

**Figure 12. MOSFET drain voltage and snubber capacitor **
**voltage**

** (12) STEP-12 : Design the Control circuit.**

In general, a battery charger employs constant current (CC) / constant voltage (CV) control circuit for an optimal charge of a battery. This design note presents two basic CC/CV control circuits for FPS flyback converters. A simple, low cost circuit using a transistor and shunt regulator (KA431) is presented first. The second circuit features highly accurate current control using an op amp together with a shunt regulator (KA431) and secondary bias winding. In the circuit analysis, it is assumed that the CTR of the opto-coupler is 100%.

**(a) Transistor and regulator (KA431) scheme**

Figure 13 shows the CC/CV control circuit using a transistor
and KA431 for 5.2V/0.65A output application. This circuit is
widely used when low cost and simplicity are major
concerns. Since the transistor base-emitter voltage drop
depends on the temperature, a temperature compensation
circuit is required for temperature stability. To turn on the
transistor (Q), about 0.7V voltage drop across the sensing
resistor (R_{sense}) is required and this current control circuit
should be used for output currents below 1A due to the
power dissipated in current sense resistor. For output currents
greater than 1A, or if output current accuracy and

temperature stability are a key factor, the op amp current control circuits shown in Figure 15 should be used.

**Figure 13. Transistor and KA431 CC/CV control**

**Constant voltage (CV) control : The voltage divider**
network of R_{1} and R_{2} should be designed to provide 2.5V to
the reference pin of the KA431. The relationship between R_{1}
and R_{2} is given by

where V* _{o}* is the output voltage.

By choosing R1 to be 2.2kΩ, R2 is obtained as

The feedback capacitor (C_{F}) introduces an integrator for CV
control. To guarantee stable operation, C_{F} of 470nF is
chosen.

The resistors R_{bias} and R_{d} should be designed to provide
proper operating current for the KA431 and to guarantee the
full swing of the feedback voltage for the FPS device chosen.

In general, the minimum cathode voltage and current for the
KA431 are 2.5V and 1mA, respectively. Therefore, R_{bias} and
R_{d }should be designed to satisfy the following conditions.

**0 V**

**V**_{DC }^{max}

**V**_{RO}**V**_{sn2}

**Effect of stray inductance (5-10V)****BVdss**

**Voltage Margin > 10% of BVdss**

**N**_{S}**D**_{R}

**C**_{O}

**KA431****817A**

**R**_{d}

**R**_{bias}

**R**_{1}

**R**_{2}**C**_{F}

**V**_{O}**L**_{P}

**C**_{P}

**R**_{sense}

**R**_{base}**Q**

**R**_{TH}

**C**_{B}**v**_{FB}

**1:1****FPS**

**R**_{B}

**GND****I**_{FB}

**I**_{o}

**250uA*** 56Ω*ΩΩΩ

*ΩΩΩ*

**510Ω****470nF****KSP2222**

* 10kΩ*ΩΩΩ

* 510Ω*ΩΩΩ

*ΩΩΩ*

**1Ω****5.2V / 0.65A**

* 2.2kΩ*ΩΩΩ

* 2kΩ*ΩΩΩ

*R*_{2}*2.5 R*⋅ _{1}

*V** _{o}*–

*2.5*

*---*

*=* * (28)*

*R*_{2}*2.5 2.2k*⋅ Ω

*5.2V*–*2.5V*

*---* *2k*Ω

*=* *=* * *

*V** _{o}*–

*V*

*–*

_{OP}*2.5*

*R*

_{d}

*--->I*_{FB}* (29)*
*V*_{OP}

*R*_{bias}

*--->1mA* * (30)*

where *V** _{o}* is the output voltage, V

*is opto-diode forward voltage drop, which is typically 1V and I*

_{OP}

_{FB}*is the feedback*current of FPS. With I

*=0.25mA (FSD210), R*

_{FB}*and R*

_{d}*are determined as 56Ω and 510Ω, respectively.*

_{bias}**Constant Current (CC) control : The current control**
circuit is shown in detail in Figure 14. The CC control is
implemented using a transistor. Because the transistor base-
emitter voltage drop varies with the temperature, negative
thermal coefficient (NTC) thermistor is used for a
temperature compensation.

**Figure 14. Current control circuit in detail**

When the voltage across the sensing resistor is sufficient to
turn on the transistor, CC controller is enabled while CV
controller is disabled. Then, the KA431 consumes very small
current and most of the currents through R* _{d}* and R

*flow into the collector of the transistor Q. By assuming that the feedback voltage of FPS (V*

_{bias}*) is in the middle of its operating range, half of the FPS feedback current (I*

_{FB}*) sinks into the opto-coupler transistor. Since it is also assumed that the CTR of the opto-coupler is 100%, the transistor collector current is given by*

_{FB}where I_{FB}* is the feedback current of FPS, V** _{OP}* is opto-diode
forward voltage drop, which is typically 1V.

From the circuit in Figure 14, I* _{C}* is obtained as

By assuming that the current gain (β) of Q is 100, the transistor base current is obtained as

The voltage drop in the sensing resistor (V* _{sense}*) should be set
to be 40-100mV higher than the transistor base-emitter
voltage (V

*) at room temperature (25°C). The actual transistor base-emitter voltage (V*

_{BE}_{BE}) temperature is measured at room temperature as 0.608V with I

*of 2.1mA and V*

_{C}*is determined to be 0.650V.*

_{sense}With the V* _{sense}* chosen, the sensing resistor (R

*) is obtained as*

_{sense}where I_{o}* is SMPS output current.*

It is typical to design the NTC thermistor so that the current
through the thermistor would be about 3-6 times of the
transistor base current at room temperature. The resistance
of the thermistor at room temperature (R_{TH}) is determined as
10 kΩ. The current through the thermistor is obtained as

The base resistor is determined by

Variations in the junction temperature of Q will cause
variations in the value of controlled output current (I_{o}). The
base-emitter voltage decreases with increasing temperature
at a rate of approximately 2mV/°C. When the base-emitter
voltage is changed to V_{BE}* ^{T}* as the temperature changes to T

°C, the thermistor resistance at T °C required to compensate this variation is given by

With -2mV/°C, *V** _{BE}* reduces to 0.508V from 0.608V as
temperature increases from 25°C to 75°C. From equation

**KA431****R**_{d}**R**_{bias}

**R**_{sense}

**R**_{base}**Q**

**R**_{TH}

**I**_{o }**= 0.65A**

* 510*ΩΩΩΩ

*ΩΩΩΩ*

**56****KSP2222*** 10k*ΩΩΩΩ

* 510*ΩΩΩΩ

*ΩΩΩΩ*

**1****I**_{RTH}

**b****e**

**c****I**_{FB }**/2**

**+****V**_{OP}

**-****I**_{C}

**I**_{B}**V**_{BE}

**V**_{sense}

*I** _{C}* (

*I*

*⋅*

_{FB}*R*

*)⁄*

_{d}*2*

^{+}^{V}

_{op}*R*

_{bias}*---* *1*
*2--- I*⋅ _{FB}*+*

*=* * (31)*

*I** _{C}* (

*250*µ

*⋅ Ω)⁄*

^{A 56}*2*

^{+}^{1V}*510*Ω

*---* *1*

*2--- 250*⋅ µ^{A}

*+* *2.1mA*

*=* *=*

*I*_{B}*I*_{C}

*---*β *2.1mA*

*---100* *21uA*

*=* *=* *=* * (32)*

*R*_{sense}*V*_{sense}*I*_{o}

*---* *0.65V*
*0.65A*
*---* *1*Ω

*=* *=* *=* * (33)*

*I*_{RTH}*V*_{BE}

*R*_{TH}

*---* *0.608V*

*10k*Ω

*---* *61*µ^{A}

*=* *=* *=* * (34)*

*R*_{base}*V** _{sense}*–

*V*

_{BE}*V*

_{BE}*R*

_{TH}*---+I*

_{B}*---* *0.65V*–*0.608V*
*0.608V*

*10k*Ω

*--- ^{+}21*µ

^{A}*---* *513*Ω

*=* *=* *= (35)*

*R*_{TH}^{T}*V*_{BE}^{T}

*V** _{sense}*–

*V*

_{BE}

^{T}*R*

_{base}*---*–

*I*

_{B}*---*

*=* * (36)*

(36), the resistance of the thermistor at 75°C to keep the same output current is given by

NTC thermistor 103Χ2 from DSC is chosen for the compen- sation, whose resistance is 10kΩ at 25°C and 1.92kΩ at 75°C.

**(b) OP amp and shunt regulator (KA431) scheme**

Figure 15 shows a 4.2 V, 0.8A CC/CV control circuit using
the LM358 dual op amp shunt regulator (KA431). This
circuit provides higher accuracy compared with the simple
transistor circuit. Power loss is lower and efficiency is better
because smaller resistance values can be used for sense
resistor R_{sense}. The shunt regulator (KA431) is used as a
voltage reference for an accurate control.

**Constant voltage (CV) control : The Output voltage is**
sensed by R1 and R2 and then compared by OP amp
LM358B to reference of 2.5V. The output of the OP amp
drives current through D_{2} and R_{d} into the LED of the opto-
coupler. The voltage divider network of R_{1} and R_{2} should be
designed to provide 2.5V to the reference pin of the KA431.

The relationship between R_{1} and R_{2} is given by

where V* _{o}* is the output voltage.

By choosing R_{1} to be 680Ω, R_{2} is obtained as

C_{F2}, R_{F2}, and R_{6} compensate the voltage control loop.

**Constant Current (CC) control : The voltage drop across**
the sensing resistor (R_{sense}) is given by

It is typical to set V_{sense} as 0.1-0.2V.

Since the inverting input of OP amp is virtually grounded, the relationship between R4 and R5 is given by

By choosing R5 as 33kΩ, R4 is obtained as 2.1kΩ. C_{F2}, R_{F2},
and R_{6} compensate the current control loop.

*0.508V*

*0.65V*–*0.508V*

*---513* ^{–}*21*µ^{A}

*---=1.99k *

*R*_{2}*2.5 R*⋅ _{1}

*V** _{o}*–

*2.5*

*---*

*=* * (37)*

*R*_{2}*2.5*⋅680

4.2V–*2.5V*
*---* *1k*Ω

*=* *=* * *

*V*_{sense}*=* *I*_{o}*R** _{sense}* ( )

*38*

*R*_{4}*V** _{sense}*⋅

*R*

_{5}*---2.5*

*=* * (39)*

**Figure 15. CC/CV control using OP amp and shunt regulator**

**N**_{S}**D**_{R}

**C**_{O}

**H 11A 81 7A****R**_{d}

**R**_{1}

**R**_{2}**V**_{O}**L**_{P}

**C**_{P}**R**_{sen se}**D**_{b ias}

**C**_{bia s}**V**_{b ias}

**R**_{3}

**K A 431****V**_{R E F}**= 2 .5 V****R**_{4}

**R**_{5}**C**_{F 1}

**C**_{F 2}**L M 3 58 A**

**L M 3 58 B****1**

**3****2**

**4****8**

**5****6****7**

**I**_{O}**N**_{b ias}

**C**_{B}**v**_{F B}

**1 :1**

**F P S**

**R**_{B}

**G N D****I**_{F B}

**1N 4 148**

**R**_{F 1}

* 0 .2 Ω*ΩΩΩ

**4.2V**

**0.8 A**

* 6 8 0Ω*ΩΩΩ

* 1 .0kΩ*ΩΩΩ

*ΩΩΩ*

**4 .7 kΩ****R**_{F 2}* 4 .7 kΩ*ΩΩΩ

**0.1 uF**

* 1 kΩ*ΩΩΩ

**R**_{6}* 1 0 0 kΩ*ΩΩΩ

* 20 0Ω*ΩΩΩ

**0 .1 u F**

* 3 3kΩ*ΩΩΩ

*ΩΩΩ*

**2 .1 kΩ****1N 4 14 8****D**_{1}

**D**_{2}

**- Summary of symbols - **

**A**_{w}**: Winding window area of the core in mm**^{2}
**Ae** **: Cross sectional area of the core in mm**^{2}
**B**_{sat }**: Saturation flux density in tesla. **

**C**_{o}**: Output capacitor**

**D**_{max}**: Maximum duty cycle ratio**
**E**_{ff}**: Estimated efficiency**
**f**_{L}**: Line frequency**

**f**_{s}**: Switching frequency of FPS**

**I**_{ds}^{peak}**: Maximum value of peak current through MOSFET at the minimum input voltage condition**
**I**_{ds2}^{peak}**: Maximum value of peak current through MOSFET at the maximum input voltage condition**
**I**_{ds}^{rms}**: RMS current of MOSFET**

**I**_{ds2}**: Maximum peak drain current at the maximum input voltage condition.**

**I**_{over}**: FPS current limit level.**

**I**_{se}^{rms}**: RMS current of the secondary winding**

**I**_{D}^{rms}** : **Maximum rms current of the output rectifier diode
**I**_{cap}^{rms}**: RMS Ripple current of the output capacitor **
**I**_{o}**: Output load current **

**K**_{RF}**: Current ripple factor **

**L**_{m}**: Transformer primary side inductance **
**L**_{lk}**: Transformer primary side leakage inductance **

**Loss**_{sn}**: Maximum power loss of the snubber network in normal operation**

**N**_{p}^{min}**: The minimum number of turns for the transformer primary side to avoid saturation**
**N**_{p}**: Number of turns for primary side winding**

**N**_{s}**: Number of turns for the output winding**
**N**_{a}**: Number of turns for the Vcc winding**
**P**_{o}**: Maximum output power**

**P**_{in}**: Maximum input power **

**R**_{c}**: Effective series resistance (ESR) of the output capacitor.**

**R**_{sn}**: Snubber resistor**

**R**_{L}**: Effective total output load resistor of the controlled output**
**V**_{line}^{min}**: Minimum line voltage**

**V**_{line}^{max}**: Maximum line voltage**
**V**_{DC}^{min}**: Minimum DC link voltage **
**V**_{DC}^{max}**: Maximum DC line voltage**

**V**_{ds}^{nom}**: Maximum nominal MOSFET voltage**
**V**_{o}**: Output voltage **

**V**_{F}**: Forward voltage drop of the output rectifier diode. **

**V**_{cc}^{*}**: Nominal voltage for Vcc**

**V**_{Fa}**: Diode forward voltage drop of Vcc winding**
**V**_{D}**: Maximum voltage of the output rectifier diode **
**V**_{RO}**: Output voltage reflected to the primary**

**V**_{sn}**: Snubber capacitor voltage under minimum input voltage and full load condition**
**V**_{sn2}**: Snubber capacitor voltage under maximum input voltage and full load condition **
**V**_{ds}^{max}**: Maximum voltage stress of the MOSFET**