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Application Note AN4138

Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPS ^TM )

Abstract

This application note presents practical design consider- ations for battery chargers employing Green Mode FPS (Fairchild Power Switch). It includes designing the transformer and output filter, selecting the components and implementing constant current / constant voltage control.

The step-by-step design procedure described in this paper will help engineers design battery chargers more easily. In order to make the design process more efficient, a software design tool, FPS design assistant that contains all the equations described in this paper is also provided. The design procedure is verified through an experimental prototype converter.

Rev. 1.0.0

1. Introduction

As penetration rates of portable electronics devices such as cellular phones, digital cameras or PDAs have increased significantly, the demands for low cost battery chargers are rising these days. Fairchild Power Switch (FPS) reduces total component count, design size, weight and, at the same time increases efficiency, productivity, and system reliability when compared to a discrete MOSFET and controller or RCC switching converter solution. Table 1 shows the FPS lineup for a battery charger application. Figure 1 shows the schematic of the basic battery charger using FPS, which also serves as the reference circuit for the design process

described in this paper. An experimental flyback converter from the design example has been built and tested to show the validity of the design procedure.

Table 1. FPS lineup for a battery charger Figure 1. Basic Battery charger Using FPS

Np N_S

R_sn C_sn - V_sn

+ V_DC

+ -

AC line

D_sn

D_R

C_O

Drain

Vcc GND FB

FPS

N_a D_a R_a

C_a

H11A817A R_d Bridge

rectifier

diode V_O

L_P

C_P

C_B C_DC

I_O

I_O^ref

V_O^ref

Current Controller

Voltage Controller

V_bias

H11A817A

Device Switching frequency

Current limit

Rdson (typ.) FSDH0165 100 kHz 0.35 A 15.6 Ω

FSD311 67 kHz 0.55 A 14 Ω

FSD200 134 kHz 0.32 A 28 Ω

FSD210 134 kHz 0.32 A 28 Ω

2. Step-by-step Design Procedure

Figure 2. Flow chart of design procedure

In this section, a design procedure is presented using the schematic of Figure 1 as a reference. Figure 2 illustrates the design flow chart. The detailed design procedures are as follows:

(1) STEP-1 : Define the system specifications - Line voltage range (V_line^min and V_line^max).

- Line frequency (f_L).

- Maximum output power (P_o).

- Estimated efficiency (E_ff) : It is required to estimate the power conversion efficiency to calculate the maximum input power. In the case of a battery charger, the efficiency is relatively low due to the low output voltage and loss in the output current sense resistor. The typical efficiency is about 0.65-0.7.

With the estimated efficiency, the maximum input power is given by

(2) STEP-2 : Determine DC link capacitor (C_DC) and the DC link voltage range.

It is typical to select the DC link capacitor as 2-3uF per watt of input power for universal input range (85-265Vrms) and 1uF per watt of input power for European input range (195V- 265Vrms). With the DC link capacitor chosen, the minimum link voltage is obtained as

where D_ch is the DC link capacitor charging duty ratio defined as shown in Figure 3, which is typically about 0.2 and P_in, V_line^min and f_L are specified in step-1.

The maximum DC link voltage is given as

where V_line^max is specified in step-1.

Figure 3. DC Link Voltage Waveform 1. Determine the system specifications

(V_line^min, V_line^max, f_L, Po, E_ff)

2. Determine DC link capacitor (C_DC) and DC link voltage range

3. Determine the reflected output voltage (V_RO)

6. Determine the proper core and the minimum primary turns (N_p^min)

7. Determine the number of turns for each output

8. Determine the wire diameter for each winding

9. Choose the proper rectifier diode for each output

10. Determine the output capacitor

11. Design the RCD snubber

12. Control Circuit design 5. Choose proper FPS considering input

power and I_ds^peak

4. Determine the transformer primary side inductance (L_m) and maximum duty (D_max)

Is the winding window area (Aw) enough ?

Design finished

Y

N

Is it possible to change the core ? Y

N

P_in P_o

E_ff ---

= (1)

V_DC^min 2⋅(V_line^min)^{2 Pin}⋅^(1–Dch) C_DC⋅f_L --- –

= (2)

V_DC^max= 2V_line^max (3)

DC link voltage Minimum DC link voltage

T₁ T₂ D_ch = T₁ / T₂

= 0.2

(3) STEP-3 : Determine the reflected output voltage (V_RO).

When the MOSFET in the FPS is turned off, the input voltage (V_DC) together with the output voltage reflected to the primary (V_RO) are imposed on the MOSFET as shown in Figure 4. After determining V_RO, the maximum nominal MOSFET voltage (V_ds^nom) is obtained as

where V_DC^max is specified in equation (3). The typical value for V_RO is 65-85V.

Figure 4. The output voltage reflected to the primary

(4) STEP-4 : Determine the transformer primary side inductance (L_m) and the maximum duty ratio (D_max).

A Flyback converter has two kinds of operation modes;

continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The operation changes between CCM and DCM as the load condition and input voltage vary and each operation mode has their own advantages and disadvantages, respectively. The transformer size can be reduced using DCM because the average energy stored is lower compared to CCM. However, DCM inherently causes higher RMS current, which increases the conduction loss of the MOSFET and the current stress on the output capacitors.

For low power applications under 10W where the MOSFET conduction loss is not so severe, it is typical to design the converter to operate in DCM for the entire operating range, or to operate in CCM only for low input voltage conditions in order to minimize the transformer size.

Figure 5. Simplified flyback converter

The design procedures for CCM and DCM are slightly different. Once the reflected output voltage (V_RO) is determined in step-3, the flyback converter can be simplified as shown in Figure 5 by neglecting the voltage drops in MOSFET and diode.

For CCM operation, the maximum duty ratio is given by

where V_DC^min and V_RO are specified in equations (2) and step-3, respectively.

For DCM operation, the maximum duty ratio should be determined as smaller than the value obtained in equation (5). By reducing D_max, the transformer size can be reduced.

However, this increases the RMS value of the MOSFET drain current and D_max should be determined by trade-off between the transformer size and MOSFET conduction loss.

With the maximum duty ratio, the primary side inductance (L_m) of the transformer is obtained. The worst case in designing L_m is full load and minimum input voltage V_ds^nom = V_DC^max+V_RO (4)

- V_{R O}

+ V_{D C}

+ -

D ra in

G N D F P S

+ V_{d s}

-

0 V V_{D C} V_{R O}

L_m V_DC^min

V_RO

I_ds

I_D I_m

I_m

I_m

I_ds

I_ds D_max

D_max

I_D

I_D

min DC RO

RO

V V

V

= +

min DC RO

RO

V V

V

≤ +

D_max V_RO

V_RO+V_DC^min ---

= (5)

condition. Therefore, L_m is obtained in this condition as

where V_DC^min is specified in equation (2), D_max is specified in equation (5), P_in is specified in step-1, f_s is the switching frequency of the FPS device and K_RF is the ripple factor in full load and minimum input voltage condition, defined as shown in Figure 6. For DCM operation, K_RF = 1 and for CCM operation K_RF < 1. The ripple factor is closely related to the transformer size and the RMS value of the MOSFET current. In the case of low power applications such as battery chargers, a relatively large ripple factor is used in order to minimize the transformer size. It is typical to set K_RF = 0.5- 0.7 for the universal input range and K_RF = 1.0 for the European input range.

Once L_m is determined, the maximum peak current and RMS current of the MOSFET in normal operation are obtained as

where P_in, V_DC^min, D_max and L_m are specified in equations (1), (2), (5) and (6) respectively and f_s is the FPS switching frequency.

Figure 6. MOSFET Drain Current and Ripple Factor (K_RF)

(5) STEP-5 : Choose the proper FPS considering input power and peak drain current.

With the resulting maximum peak drain current of the MOSFET (I_ds^peak) from equation (7), choose the proper FPS of which the pulse-by-pulse current limit level (I_over) is higher than I_ds^peak. Since FPS has ± 12% tolerance of I_over, there should be some margin in choosing the proper FPS device.

(6) STEP-6 : Determine the proper core and the minimum primary turns.

Table 2 shows the commonly used cores for battery chargers with output power under 10W. The cores recommended in table 2 are typical for the universal input range and 100kHz switching frequency.

With the chosen core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by

where L_m is specified in equation (6), I_over is the FPS pulse- by-pulse current limit level, A_e is the cross-sectional area of the core as shown in Figure 7 and B_sat is the saturation flux density in tesla. Figure 8 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (B_sat) decreases as the temperature goes high, the high temperature characteristics should be considered.

If there is no reference data, use B_sat =0.3~0.35 T. Since the MOSFET drain current exceeds I_ds^peak and reaches I_over in a transition or fault condition, I_over is used in equation (11) instead of I_ds^peak to prevent core saturation during transition.

Figure 7. Window Area and Cross Sectional Area L_m (V_DC^min⋅D_max)²

2P_inf_sK_RF ---

= (6)

I_ds^peak I_EDC ∆^I

---2 +

= (7)

I_ds^rms 3 I( _EDC)² ∆^I

---2

  ²

+ D_max

---3

= ( )8

I_EDC P_in

V_DC^min⋅D_max ---

= (9)

∆^{I VDC}

min D_max L_mf_s ---

= (10)

∆I IEDC

EDC RF I K I

2

= ∆

CCM operation : K_RF < 1

∆I ^IEDC

EDC RF I K I

2

= ∆

DCM operation : K_RF =1 peak

Ids peak

Ids

N_P^min L_mI_over B_satA_e

---×10⁶ (turns)

= (11)

Aw Aw Aw Aw

Ae Ae

Ae Ae

Figure 8. Typical B-H characteristics of ferrite core (TDK/PC40)

Table 2. Typical cores for battery charger (For universal input range, 5V output and fs=100kHz)

(7) STEP-7 : Determine the number of turns for each output

Figure 9 shows the simplified diagram of the transformer.

First, determine the turns ratio (n) between the primary side and the secondary side.

where N_p and N_s are the number of turns for primary side and reference output, respectively, V_o is the output voltage, V_F is the diode (D_R) forward voltage drop and V_sense is the maximum voltage drop in the output current sensing resistor.

Then, determine the proper integer for N_s so that the resulting Np is larger than N_p^min obtained from equation (11).

The number of turns for Vcc winding is determined as

where V_cc* is the nominal value of the supply voltage of the FPS device, and V_Fa is the forward voltage drop of D_a as defined in Figure 9. Since V_cc increases as the output load increases, it is proper to set V_cc* as V_cc start voltage (refer to the data sheet) to avoid triggering the over voltage protection during normal operation.

Figure 9. Simplified diagram of the transformer

With the determined turns of the primary side, the gap length of the core is obtained as

where A_L is the AL-value with no gap in nH/turns², Ae is the cross sectional area of the core as shown in Figure 8, L_m is specified in equation (6) and N_p is the number of turns for the primary side of the transformer

(8) STEP-8 : Determine the wire diameter for each winding based on the rms current of each output.

The rms current of the n-th secondary winding is obtained as

where V_RO and I_ds^rms are specified in step-3 and equations (8), V_o is the output voltage, V_F is the diode (D_R)) forward voltage drop and D_max is specified in equation (5).

The current density is typically 5A/mm² when the wire is Core Cross sectional

area

Window area Output power range EE13-Z 17.1 mm² 33.4 mm² 3-5W EI16-Z 19.8 mm² 38.8 mm² 3-5W EE16-Z 21.7 mm² 51.3 mm² 5-10W EI19-Z 24.0 mm² 54.4 mm² 5-10W

100 500

400

300

200

800 1600

0 0

M agnetic field H (A /m )

Flux density B (mT)

M agnetization C urves (typical) M aterial :PC 40

100 ℃℃℃℃ 120 ℃℃℃℃ 60 ℃℃℃℃ 25 ℃℃℃℃

n N_P

N_s

--- V_R0

V_o+V_F+V_sense ---

= = (12)

N_a V_cc*+V_Fa V_o+V_F ---

= ⋅N_s1 (^turns) ( )13

Np

N_S -

V_RO +

D_R N_a

D_a +

V_O - + V_F - - V_Fa +

+ V_cc^*

-

- V_sense +

) ( _{o F sense}

s p

RO V V V

N

V = N + +

G 40πA_e ^NP

2

1000L_m

--- 1 A_L ---

 – 

 

 

= (mm) ( )14

I_s^rms I_ds^rms 1–D_max

D_max

--- V_RO V_o+V_F

( )

---

⋅

= ( )15

long (>1m). When the wire is short with a small number of turns, a current density of 6-10 A/mm² is also acceptable.

Avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses as well as to make winding easier.

For high current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect.

Check if the winding window area of the core, A_w (refer to Figure 8) is enough to accommodate the wires. Because bobbin, insulation tape and gaps between wires, the wire can not fill the entire winding window area. Typically the fill factor is about 0.15-0.2 for a battery charger. When additional dummy windings are employed for EMI shielding, the fill factor is reduced. The required winding window area (A_wr) is given by

where A_c is the actual conductor area and K_F is the fill factor.

If the required window (A_wr) is larger than the actual window area (A_w), go back to the step-6 and change the core to a bigger one. Sometimes it is impossible to change the core due to cost or size constraints. If so, go back to step-4 and reduce L_m by increasing the ripple factor (K_RF) or reducing the maximum duty ratio. Then, the minimum number of turns for the primary (N_p^min) of the equation (11) will decrease, which results in the reduced required winding window area (A_wr).

(9) STEP-9 : Choose the rectifier diode in the secondary side based on the voltage and current ratings.

The maximum reverse voltage and the rms current of the output rectifier diode (D_R) are obtained as

where V_DC^max, D_max and I_ds^rms are specified in equations (3), (5) and (8), respectively, V_o is the output voltage, V_F is the diode (D_R) forward voltage and V_sense is the maximum voltage drop in the output current sensing resistor.

The typical voltage and current margins for the rectifier diode are as follows

where V_RRM is the maximum reverse voltage and I_F is the average forward current of the diode.

A quick selection guide for Fairchild Semiconductor rectifier diodes is given in table 3.

Table 3. Fairchild Diode quick selection table

(10) STEP-10 : Determine the output capacitor considering the voltage and current ripple.

The ripple current of the output capacitor (C_o) is obtained as

where I_o is the load current and I_D^rms is specified in equation (18). The ripple current should be smaller than the ripple current specification of the capacitor. The voltage ripple on the n-th output is given by

where C_o is the output capacitance, R_c is the effective series resistance (ESR) of the output capacitor, D_max and I_ds^peak are specified in equations (5) and (7), respectively, I_o and V_o are the load current and output voltage, respectively, V_F is the diode (D_R) forward voltage and V_sense is the maximum voltage drop in the output current sensing resistor.

Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. Then, additional LC filter stages (post filter) can be used. When using the post filters, be careful not to place the corner frequency too low. Too low a corner frequency may make the system unstable or limit the control bandwidth. It is typical to set the corner frequency of the post filter at around 1/10~1/5 of the switching frequency.

(11) STEP-11 : Design the RCD snubber.

When the power MOSFET is turned off, there is a high voltage spike on the drain due to the transformer leakage inductance. This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the FPS. Therefore, it is necessary to use an additional network to clamp the voltage.

The RCD snubber circuit and MOSFET drain voltage waveform are shown in Figure 10 and 11, respectively. The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode (D_sn) once the MOSFET drain voltage exceeds the voltage of node X as depicted in Figure 10. In the analysis of snubber network, it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching A_wr ⁼ A_c⁄K_F (16)

V_D V_o V_DC^max⋅(V_o+V_F+V_sense) V_RO

--- +

= ( )17

I_D^rms I_ds^rms V_DC^min

V_RO

--- V_RO V_o+V_F+V_sense

( )

---

⋅

= ( )18

V_RRM>1.3 V⋅ _D (19) I_F>1.5 I⋅ _D^rms (20)

Schottky Barrier Diode

Products V_RRM I_F Package

SB340 40 V 3 A TO-210AD

SB350 50 V 3 A TO-210AD

SB360 60 V 3 A TO-210AD

I_cap^rms = (I_D^rms)²–I_o² (21)

∆^V_o ^IoDmax C_of_s

--- I_ds^peakV_ROR_C V_o+V_F+V_sense

( )

--- (22) +

=

cycle. The snubber capacitor used should be ceramic or a material that offers low ESR. Electrolytic or tantalum capacitors are unacceptable due to these reasons.

Figure 10. Circuit diagram of the snubber network

The first step in designing the snubber circuit is to determine the snubber capacitor voltage at the minimum input voltage and full load condition (V_sn). Once V_sn is determined, the power dissipated in the snubber network at the minimum input voltage and full load condition is obtained as

where I_ds^peak is specified in equation (8), f_s is the FPS switching frequency, L_lk is the leakage inductance, V_sn is the snubber capacitor voltage at the minimum input voltage and full load condition, V_RO is the reflected output voltage and R_sn is the snubber resistor. V_sn should be larger than V_RO and it is typical to set V_sn to be 2~2.5 times V_RO. Too small a V_sn results in a severe loss in the snubber network as shown in equation (23). The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted.

Then, the snubber resistor with proper rated wattage should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained as

where f_s is the FPS switching frequency. In general, 5~10%

ripple of the selected capacitor voltage is reasonable.

The snubber capacitor voltage (V_sn) of equation (26) is for the minimum input voltage and full load condition. When the converter is designed to operate in CCM under this condition, the peak drain current together with the snubber capacitor voltage decrease as the input voltage increases as shown in Figure 11. The peak drain current at the maximum

input voltage and full load condition (I_ds2^peak) is obtained as

where P_in, and L_m are specified in equations (1) and (6), respectively and f_s is the FPS switching frequency.

The snubber capacitor voltage under maximum input voltage and full load condition is obtained as

where f_s is the FPS switching frequency, L_lk is the primary side leakage inductance, V_RO is the reflected output voltage and R_sn is the snubber resistor.

Figure 11. MOSFET drain voltage and snubber capacitor voltage

From equation (26), the maximum voltage stress on the internal MOSFET is given by

where V_DC^max is specified in equation (3).

Check if V_ds^max is below 85% of the rated voltage of the MOSFET (BVdss) as shown in Figure 12. The voltage rating of the snubber diode should be higher than BVdss. Usually, an ultra fast diode with 1A current rating is used for the snubber network.

R_sn C_sn Np - V_sn

+ V_DC

+ -

D_sn

Drain

GND FPS C_DC

- V_RO

+

+ V_ds

- L_lk V_X

X

P_sn (V_sn)² R_sn --- 1

2---f_sL_lK(I_ds^peak)² V_sn V_sn–V_RO ---

= = (23)

∆^V_sn ^Vsn C_snR_snf_s ---

= (24)

I_ds2^peak 2 P⋅ _in f_s⋅L_m ---

= (25)

V_sn2 V_RO+ (V_RO)²+2R_snL_lkf_s(I_ds2^peak)² ---2

= (26)

V_DC ^min

V_RO V_sn

V_DC ^max

V_RO V_sn2

I_ds^peak

I_ds2^peak

Minimum input voltage

& Full load

Maximum input voltage

& Full load I_ds2^peak < I_ds^peak ==> V_sn2 < V_sn

V_ds^max = V_DC^max+V_sn2 (27)

In the snubber design in this section, neither the lossy discharge of the inductor nor stray capacitance is considered.

In the actual converter, the loss in the snubber network is less than the designed value due to this effects.

Figure 12. MOSFET drain voltage and snubber capacitor voltage

(12) STEP-12 : Design the Control circuit.

In general, a battery charger employs constant current (CC) / constant voltage (CV) control circuit for an optimal charge of a battery. This design note presents two basic CC/CV control circuits for FPS flyback converters. A simple, low cost circuit using a transistor and shunt regulator (KA431) is presented first. The second circuit features highly accurate current control using an op amp together with a shunt regulator (KA431) and secondary bias winding. In the circuit analysis, it is assumed that the CTR of the opto-coupler is 100%.

(a) Transistor and regulator (KA431) scheme

Figure 13 shows the CC/CV control circuit using a transistor and KA431 for 5.2V/0.65A output application. This circuit is widely used when low cost and simplicity are major concerns. Since the transistor base-emitter voltage drop depends on the temperature, a temperature compensation circuit is required for temperature stability. To turn on the transistor (Q), about 0.7V voltage drop across the sensing resistor (R_sense) is required and this current control circuit should be used for output currents below 1A due to the power dissipated in current sense resistor. For output currents greater than 1A, or if output current accuracy and

temperature stability are a key factor, the op amp current control circuits shown in Figure 15 should be used.

Figure 13. Transistor and KA431 CC/CV control

Constant voltage (CV) control : The voltage divider network of R₁ and R₂ should be designed to provide 2.5V to the reference pin of the KA431. The relationship between R₁ and R₂ is given by

where V_o is the output voltage.

By choosing R1 to be 2.2kΩ, R2 is obtained as

The feedback capacitor (C_F) introduces an integrator for CV control. To guarantee stable operation, C_F of 470nF is chosen.

The resistors R_bias and R_d should be designed to provide proper operating current for the KA431 and to guarantee the full swing of the feedback voltage for the FPS device chosen.

In general, the minimum cathode voltage and current for the KA431 are 2.5V and 1mA, respectively. Therefore, R_bias and R_d should be designed to satisfy the following conditions.

0 V

V_DC ^max

V_RO V_sn2

Effect of stray inductance (5-10V) BVdss

Voltage Margin > 10% of BVdss

N_S D_R

C_O

KA431 817A

R_d

R_bias

R₁

R₂ C_F

V_O L_P

C_P

R_sense

R_base Q

R_TH

C_B v_FB

1:1 FPS

R_B

GND I_FB

I_o

250uA 56ΩΩΩΩ 510ΩΩΩΩ

470nF KSP2222

10kΩΩΩΩ

510ΩΩΩΩ 1ΩΩΩΩ

5.2V / 0.65A

2.2kΩΩΩΩ

2kΩΩΩΩ

R₂ 2.5 R⋅ ₁

V_o–2.5 ---

= (28)

R₂ 2.5 2.2k⋅ Ω

5.2V–2.5V

--- 2kΩ

= =

V_o–V_OP–2.5 R_d

--->I_FB (29) V_OP

R_bias

--->1mA (30)

where V_o is the output voltage, V_OP is opto-diode forward voltage drop, which is typically 1V and I_FB is the feedback current of FPS. With I_FB=0.25mA (FSD210), R_d and R_bias are determined as 56Ω and 510Ω, respectively.

Constant Current (CC) control : The current control circuit is shown in detail in Figure 14. The CC control is implemented using a transistor. Because the transistor base- emitter voltage drop varies with the temperature, negative thermal coefficient (NTC) thermistor is used for a temperature compensation.

Figure 14. Current control circuit in detail

When the voltage across the sensing resistor is sufficient to turn on the transistor, CC controller is enabled while CV controller is disabled. Then, the KA431 consumes very small current and most of the currents through R_d and R_bias flow into the collector of the transistor Q. By assuming that the feedback voltage of FPS (V_FB) is in the middle of its operating range, half of the FPS feedback current (I_FB) sinks into the opto-coupler transistor. Since it is also assumed that the CTR of the opto-coupler is 100%, the transistor collector current is given by

where I_FB is the feedback current of FPS, V_OP is opto-diode forward voltage drop, which is typically 1V.

From the circuit in Figure 14, I_C is obtained as

By assuming that the current gain (β) of Q is 100, the transistor base current is obtained as

The voltage drop in the sensing resistor (V_sense) should be set to be 40-100mV higher than the transistor base-emitter voltage (V_BE) at room temperature (25°C). The actual transistor base-emitter voltage (V_BE) temperature is measured at room temperature as 0.608V with I_C of 2.1mA and V_sense is determined to be 0.650V.

With the V_sense chosen, the sensing resistor (R_sense) is obtained as

where I_o is SMPS output current.

It is typical to design the NTC thermistor so that the current through the thermistor would be about 3-6 times of the transistor base current at room temperature. The resistance of the thermistor at room temperature (R_TH) is determined as 10 kΩ. The current through the thermistor is obtained as

The base resistor is determined by

Variations in the junction temperature of Q will cause variations in the value of controlled output current (I_o). The base-emitter voltage decreases with increasing temperature at a rate of approximately 2mV/°C. When the base-emitter voltage is changed to V_BE^T as the temperature changes to T

°C, the thermistor resistance at T °C required to compensate this variation is given by

With -2mV/°C, V_BE reduces to 0.508V from 0.608V as temperature increases from 25°C to 75°C. From equation KA431

R_d R_bias

R_sense

R_base Q

R_TH

I_o = 0.65A

510ΩΩΩΩ 56ΩΩΩΩ

KSP2222 10kΩΩΩΩ

510ΩΩΩΩ 1ΩΩΩΩ

I_RTH

b e

c I_FB /2

+ V_OP

- I_C

I_B V_BE

V_sense

I_C (I_FB⋅R_d)⁄2^+V_op R_bias

--- 1 2--- I⋅ _FB +

= (31)

I_C (250µ^{A 56}⋅ Ω)⁄2^+1V

510Ω

--- 1

2--- 250⋅ µ^A

+ 2.1mA

= =

I_B I_C

---β 2.1mA

---100 21uA

= = = (32)

R_sense V_sense I_o

--- 0.65V 0.65A --- 1Ω

= = = (33)

I_RTH V_BE

R_TH

--- 0.608V

10kΩ

--- 61µ^A

= = = (34)

R_base V_sense–V_BE V_BE R_TH ---+I_B

--- 0.65V–0.608V 0.608V

10kΩ

---⁺21µ^A

--- 513Ω

= = = (35)

R_TH^T V_BE^T

V_sense–V_BE^T R_base ---–I_B ---

= (36)

(36), the resistance of the thermistor at 75°C to keep the same output current is given by

NTC thermistor 103Χ2 from DSC is chosen for the compen- sation, whose resistance is 10kΩ at 25°C and 1.92kΩ at 75°C.

(b) OP amp and shunt regulator (KA431) scheme

Figure 15 shows a 4.2 V, 0.8A CC/CV control circuit using the LM358 dual op amp shunt regulator (KA431). This circuit provides higher accuracy compared with the simple transistor circuit. Power loss is lower and efficiency is better because smaller resistance values can be used for sense resistor R_sense. The shunt regulator (KA431) is used as a voltage reference for an accurate control.

Constant voltage (CV) control : The Output voltage is sensed by R1 and R2 and then compared by OP amp LM358B to reference of 2.5V. The output of the OP amp drives current through D₂ and R_d into the LED of the opto- coupler. The voltage divider network of R₁ and R₂ should be designed to provide 2.5V to the reference pin of the KA431.

The relationship between R₁ and R₂ is given by

where V_o is the output voltage.

By choosing R₁ to be 680Ω, R₂ is obtained as

C_F2, R_F2, and R₆ compensate the voltage control loop.

Constant Current (CC) control : The voltage drop across the sensing resistor (R_sense) is given by

It is typical to set V_sense as 0.1-0.2V.

Since the inverting input of OP amp is virtually grounded, the relationship between R4 and R5 is given by

By choosing R5 as 33kΩ, R4 is obtained as 2.1kΩ. C_F2, R_F2, and R₆ compensate the current control loop.

0.508V

0.65V–0.508V

---513 ^–21µ^A

---=1.99k

R₂ 2.5 R⋅ ₁

V_o–2.5 ---

= (37)

R₂ 2.5⋅680

4.2V–2.5V --- 1kΩ

= =

V_sense = I_oR_sense ( )38

R₄ V_sense⋅R₅ ---2.5

= (39)

Figure 15. CC/CV control using OP amp and shunt regulator

N_S D_R

C_O

H 11A 81 7A R_d

R₁

R₂ V_O L_P

C_P R_{sen se} D_{b ias}

C_{bia s} V_{b ias}

R₃

K A 431 V_{R E F}= 2 .5 V R₄

R₅ C_{F 1}

C_{F 2} L M 3 58 A

L M 3 58 B 1

3 2

4 8

5 6 7

I_O N_{b ias}

C_B v_{F B}

1 :1

F P S

R_B

G N D I_{F B}

1N 4 148

R_{F 1}

0 .2 ΩΩΩΩ

4.2V

0.8 A

6 8 0ΩΩΩΩ

1 .0kΩΩΩΩ 4 .7 kΩΩΩΩ

R_{F 2} 4 .7 kΩΩΩΩ

0.1 uF

1 kΩΩΩΩ

R₆ 1 0 0 kΩΩΩΩ

20 0ΩΩΩΩ

0 .1 u F

3 3kΩΩΩΩ 2 .1 kΩΩΩΩ

1N 4 14 8 D₁

D₂

- Summary of symbols -

A_w : Winding window area of the core in mm² Ae : Cross sectional area of the core in mm² B_sat : Saturation flux density in tesla.

C_o : Output capacitor

D_max : Maximum duty cycle ratio E_ff : Estimated efficiency f_L : Line frequency

f_s : Switching frequency of FPS

I_ds^peak : Maximum value of peak current through MOSFET at the minimum input voltage condition I_ds2^peak : Maximum value of peak current through MOSFET at the maximum input voltage condition I_ds^rms : RMS current of MOSFET

I_ds2 : Maximum peak drain current at the maximum input voltage condition.

I_over : FPS current limit level.

I_se^rms : RMS current of the secondary winding

I_D^rms : Maximum rms current of the output rectifier diode I_cap^rms : RMS Ripple current of the output capacitor I_o : Output load current

K_RF : Current ripple factor

L_m : Transformer primary side inductance L_lk : Transformer primary side leakage inductance

Loss_sn : Maximum power loss of the snubber network in normal operation

N_p^min : The minimum number of turns for the transformer primary side to avoid saturation N_p : Number of turns for primary side winding

N_s : Number of turns for the output winding N_a : Number of turns for the Vcc winding P_o : Maximum output power

P_in : Maximum input power

R_c : Effective series resistance (ESR) of the output capacitor.

R_sn : Snubber resistor

R_L : Effective total output load resistor of the controlled output V_line^min : Minimum line voltage

V_line^max : Maximum line voltage V_DC^min : Minimum DC link voltage V_DC^max : Maximum DC line voltage

V_ds^nom : Maximum nominal MOSFET voltage V_o : Output voltage

V_F : Forward voltage drop of the output rectifier diode.

V_cc^* : Nominal voltage for Vcc

V_Fa : Diode forward voltage drop of Vcc winding V_D : Maximum voltage of the output rectifier diode V_RO : Output voltage reflected to the primary

V_sn : Snubber capacitor voltage under minimum input voltage and full load condition V_sn2 : Snubber capacitor voltage under maximum input voltage and full load condition V_ds^max : Maximum voltage stress of the MOSFET