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レイトレ－シング専用コンピューティングシステム RAPLAS の FPGA による実装

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(1)W3«««r. 2007-SLDM-128C2). IPSJ SIG Technical Reports. 2007/1/17. ^. FPGA. T4 VWTr. RAPLAS <D. £^. t. ft 0 ^T-f • tT- • iix (*) HSil^f. T 242-8502 *?PrtTT»IW 1623-14. E-mail: t{zaitsu,yoshi,suzuki,egawa,nakamura} @ archi.is.tohoku.ac.jp, ttooba@jp.ibm.com i«. >* ^ A RAPLAS. RAPLAS <DFPGAfccfcSaS6£Stt£U FPGAO#*«:^^U^:ifttr^S<3 ^-e, RAPLAS. h U— W^Vn- K. FGPA Implementation of the Computing System RAPLAS for Ray-Tracing Daichi ZAITSU1, Yoshiyuki KAERIYAMAt, Kenichi SUZUKI, Ryusuke EGAWA1, Nobuyuki 0HBAn, and Tadao NAKAMURA1^ t Graduate School of Information Sciences, Tohoku University.. Aramaki Aza Aoba 6-6-01, Aoba-ku, Sendai-shi,. 980-8579 Japan. tt IBM Research Laboratory, IBM Japan, Ltd.. Shimo-tsuruma 1623-14, Yamato-shi, 242-8502 Japan. E-mail: t{zaitsu,yoshi,suzuki,egawa,nakamura) @archi.is.tohoku.ac.jp, ttooba@jp.ibm.com. Abstract. Ray-tracing is one of the rendering methods based on the global illumination model, which is extensively used. in the computer graphics. Although it generates photo-realistic images, it requires a large number of computations in the ray-object intersction test. To accelerate the intersection test, a new method based on a plane-sphere intersection algorithm and a hardware system RAPLAS have been proposed. This paper presents hardware implementation of the intersection core, which is the main unit of RAPLAS, using a FPGA. High performance intersection core is implemented by designing a dedi cated floating-point calculator using DPS cores.. Key words. Computer Graphics, Ray-tracing hardware, Intersection method. £ t \z.. , 1984^, Cook £(^. Lt, j&Mm^T'V. tz-<DM@L$LJ$.^m*. Whitted tc: J: Vm^Ztitz \"( h , Whitted H. -7-.

(2) IT,. A RAPLAS(Ray tracing Architecture based on PLane And Sphere. intersection) S: till L T V ^5 0. XxARAPLAS 2.1. 2 jfetd J: 9,. -8-.

(3) ffiii • Jftt!feflifkLTV^5o Xilinx ttW FPGA XhZ Virtex-4, Virtex-5 "^ U — Xfcti, XtremeDSP ^7>T ^ [7]. , Virtex-4 *> !i -X(7)37Clt, Z.(D XtremeDSP ^ 7. .3.3 #W), 16 x 16. (3.3.4. -^ RAPLAS 1212. 2.2. 2.2.1. U*f. -y Mi FPGA Ji:. DSP =>. RAPLAS Wftlg. RAPLAS fi,. '*>>( xbLX Xilinx tt Virtex-4 FPGA Srffl t ^50 3.2 2.2.2. -y Mi, # RAPLAS fi**. fcfcfc 0, ffitt^ksftSiitP FPGA \. 3.2.1. X. 5 [9].. h(Off 32 tfy. Triangle Memory. > Sphere Memory MtQ. _-j. Plane Memory Id. ^ «^. Ray Memory (C{i3t||(7) ID, &fiHt. 3 {;:. ^^ Xilinx & Virtex-4 FPGA #- K^^tt^nr^S XtremeDSP S: . XtremeDSP «§^T* 18 \f. 3. 16 tr 3.1. Lti 18 fy h $r XtremeDSP WA^f, CPU. -9-.

(4) : Ij. 8bil. 1. V \. 2]bi. I bit. Original 24-bit format. \ signl I sign2 fl naanl' |j man2' [j exp3' [•■;. 3.3 3.3.1. 3.2.2. 0*0) sign K exph. in 6 i. manl. H^t? DSP operation. XtremeDSP. riangle Memory •*> Ray Memory J: 0 x—. 3.3.2. -10-.

(5) Stage 1. Stage2. LTMollerClJ;. il 9 {ci. ^? hJK P: =. > O. o Moller \z. 3.3.3. (3). &$: P(px,py,pz) 0 ^ m, 0 ^ v,. nxx + nyy + nzz + p = 0. = \nxcx + nycy + nzcz + p\. u + v. (4). =. (5). (1). (2) -(Dx(Vo-0)).£2. 0 g u', 0 ^ v', u' + v'. (6). 10(3. .2 \z Add, Sub. 3.3.4. -11-. .2 tc.

(6) , RAPLAS W. .^y Mi,. , FPGA J. x m 10. [1]. it. J. T. Kajiya: "The rendering equation", SIGGRAPH '86: Proceed ings of the 13th annual conference on Computer graphics and inter. active techniques, New York, NY, USA, ACM Press, pp. 143-150 (1986). [2]. R. L. Cook, T. Porter and L. Carpenter: "Distributed ray tracing",. SIGGRAPH '84:. Proceedings of the 11th annual conference on. Computer graphics and interactive techniques, New York, NY, USA, ACM Press, pp. 137-145 (1984). T. Whitted: "An improved illumination model for shaded display",. Commun. ACM, 23, 6, pp. 343-349 (1980). Y.. Kaeriyama,. D. Zaitsu,. Nobuyuki Ohba:. 4.. K. Komatsu,. K. Suzuki and T. N.. "Hardware for a ray tracing technique using. plane-sphere intersections", Symposium Short Paperes Proceedings. of Eurographics Symposium on Parallel Graphics and Visualiza-. Xilinx. FPGA. tion(EGPGV 06), pp. 9-12 (2006). [5]. Avnet. XC4VSX35-10FF668, 64MB DRAM RTL. Y. Kaeriyama,. D. Zaitsu,. K. Komatsu, K. Suzuki and T. N.. Nobuyuki Ohba: "Ray tracing hardware system using plane-sphere. ^KO VHDL "C. intersections", FPL '06: Proceedings of International Conference on. IBJBU Xilinx *±<7> ISE8.2. Field Programmable Logic and Applications, pp. 315-320 (2006).. [6]. J. Schmittler, S. Woop, D. Wagner, W. J. Paul and P. Slusallek: "Realtime ray tracing of dynamic scenes on an fpga chip", HWWS '04: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS con ference on Graphics hardware, New York, NY, USA, ACM Press, pp. 95-106(2004).. [7]. Xilinx:. "XtremeDSP".. http://www.xilinx.com/products/. silicorusolutions/fpgas/virtex/virtex4/capab%ilities/ xtremedsp.htm.. [8]. ~y hit.. IEEE: "American National Standard - IEEE Standard for Binary Floating Point Arithmetic", American National Standards Institute, Inc. (1985).. [9]. Intel: "IA-32 IntelR Architecture Software Developer's Manual", http://developer.intel.com/design/intarch/pentium4/docs_ pent ium4_proc. htm#HXanuals.. f^y Mi,. [10]. R. Barzel Ed.: "Graphics Tools - the jgt editors' choice", A K Peters, Ltd (2005).. [11]. T. M6ller and B. Trumbore: "Fast, minimum storage ray-triangle in tersection", journal of graphics tools, 2, 1, pp. 21-28 (1997).. 5.. -12-.

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