Half-Bridge Drivers

(1)

Half-Bridge Drivers

A Transformer or an All-Silicon Drive?

(2)

Agenda

• Topologies using a half-bridge configuration

• The difference between soft and hard-switching

• The gate-drive transformer

• The all-silicon-solution

• Comparison

• Conclusions

(3)

Agenda

• Comparison

• Conclusions

(4)

Topology Trend for High Efficiency

• Soft Switching

– LLC-HB resonant – Active clamp forward – Active clamp flyback

– Asymmetrical half-bridge – Full bridge with phase shift

• Hard Switching – Flyback

– Forward – 2-sw flyback – 2-sw forward – Full bridge

LLC-HB

Active clamp Forward

Active clamp Flyback

AHB

FB Phase-shift

(5)

The High-Side Switch

• To achieve high efficiency, the topologies with ZVS (Zero- Voltage Switching) behavior are preferred.

• All the soft switching topologies implement the power switch with floating reference pin, e.g. the source pin of MOSFET.

• Why are MOSFETs used in soft switching applications?

– High frequency operation

– Body diode (current loop for ZVS)

How to drive the high side MOSFET?

(6)

Agenda

• Comparison

• Conclusions

(7)

D

G

S

Turn-on Procedure for Hard-switching

• Stages 2 and 3 dominate the switching losses of MOSFET and driver.

• DRV’s source capability as V_GS is around V_GS,Miller is important.

C_DS C_GD

C_GS R_G,I

R_GATE R_HI

V_DRV

I_D

V_TH V_GS

I_G

V_DS

I_D

V_GS,Miller

S₁ S₂ S₃ S₄ I_G

The Miller plateau

The miller plateau is caused by C_GD

(8)

D

G

S

Turn-off Procedure for Hard-switching

• Stages 2 and 3 dominate the switching losses of MOSFET and driver.

• DRV’s sink capability as V_GS is around V_GS,Miller is important.

C_DS C_GD

C_GS R_G,I

R_GATE R_LO

V_DRV

I_D

V_TH V_GS

I_G

V_DS

I_D

V_GS,Miller

S₁ S₂ S₃ S₄ I_G

The Miller plateau

The miller plateau is caused by C_GD

(9)

17

Vin 250

18

D1 1N4148

16

Resr 100m

C2 440uF

Rload 2.5

2 Vout

1

5

Ll 0.1uH Lp

1.75mH Rp 300m

Ip

RATIO_POW = -0.0667 RATIO_AUX = -0.0667

7

Aux

21

C5 10uF

22

R11 3.9k

C6 47pF

Isnub

R9 300m

Iout

3

Rg 15

13

Rsense 1

14

R13 C1 1k

470pF

23

Vgs

Vsense

12

Verr

11

Rupper 4.851k

Rlower 0.97k

9

R17 20k

C4 3.97nF C7

470pF 6 Vdrain

X1

MBRS340t3 Out

Out

Vramp

CMP FB OSC

SENS OUT GND

X2 PWMCM

10

D3 MUR160 Iclipp

Aux

R5 470 Rclamp

88k Cclamp 1.4nF

Δ

Vclipp

Vdrv

V1 Ipri

D2 1N4148

X3 IRF840

Simulation Circuit of Flyback

• Simulate the V_GS, V_DS, and I_DS on Flyback.

I_DS

(10)

0 4.00 8.00 12.0 16.0

vgs in voltsplot1

1

-100 100 300 500 700

vdrain in voltsplot3

2

1.01995m 1.02005m 1.02015m 1.02025m 1.02035m

time in seconds -400m

0 400m 800m 1.20

ipri in amperesplot2

3

VGS

VDS

IDS

Turn-on Simulation of Flyback

• V_GS rises with Miller effect.

50 ns / div 200 mA / div

50 ns / div 200 V / div

50 ns / div 2 V / div

(11)

0 4.00 8.00 12.0 16.0

vgs in voltsplot1

1

-100 100 300 500 700

vdrain in voltsplot3

2

1.0244m 1.0246m 1.0248m 1.0250m 1.0252m

time in seconds -400m

0 400m 800m 1.20

ipri in amperesplot2

3

VGS

VDS

IDS

Turn-off Simulation of Flyback

• Turn off with Miller effect.

100 ns / div 200 V / div

(12)

Turn-on Procedure for Soft-switching

• Because of ZVS, there is no Miller effect as turning on.

• The switching losses are dominated by

– The dead time (to reduce S₁), and – Source capability to charge C_GS to

reduce S₂

• Less driver capability requirement.

V_TH V_GS

I_G

V_DS

I_D

S₁ S₂ S₃ I_D depends on topology

-V_f

(13)

Turn-off Procedure for Soft-switching

• Similar as hard-switching: The Miller plateau exists as turning off.

• The difference is that I_DS also reduces at this duration since I_DS will go through the opposite MOSFET as V_DS changes.

• To avoid overlap between 2 MOSFETs, minimize the duration of S₁ ~ S₄.

• Strong DRV’s sink capability is needed.

V_TH V_GS

I_G

V_DS

I_DS

V_GS,Miller

S₁ S₂ S₃ S₄

The Miller plateau

(14)

10 12

Ls {Ls}

2

Lmag {Lmag}

Cs {Cs}

1

4

X3 XFMR-TAP RATIO = 1/N ILmag

ICs Vcs

Δ VLmag

26

V3 {Vbulk}

23

B1 Voltage

V(G2) < 2.5 ? 0 :

15

24

B2 Voltage

?

19

Mlower Vbridge

Cs

Δ

22

Mupper

* ^WV3

R10 5m R11

15

R14 15

11

V4 IML

M2 IRF840

5

M1 IRF840

X12 MBR2045

X13 MBR2045

Δ YM1

V10 D2 IM1

1N4148

D3 1N4148

Simulation Circuit of LLC-HB

• Simulate the V_{GS_MU}, V_{DS_MU}, and I_MU on LLC-HB

• To ease the reading of current, the direction of I_MU and I_ML is referred to I_CS.

I_MU

I_CS I_ML

(15)

Turn-on Simulation of LLC-HB

• V_{GS_ML} off, I_CS reduces V_{DS_MU} for ZVS.

• V_{DS_MU} is 0 V BEFORE V_{GS_MU}, so V_{GS_MU} rises smoothly.

-2.00 2.00 6.00 10.0 14.0

mlower, mupper in voltsplot1

1

2

0 100 200 300 400

ym1 in voltsplot2

3

10.1922m 10.1926m 10.1930m 10.1934m 10.1938m

time in seconds -2.00

-1.00 0 1.00 2.00

im1,iml in amperesplot3 4

5

VGS_MU VGS_ML

VDS_MU

I_ML I_MU

Not overlap; it is the current through C_DS

200 ns / div 200 V / div

(16)

Turn-off Simulation of LLC-HB

• Strong turn off capability is required.

-2.00 2.00 6.00 10.0 14.0

mlower, mupper in voltsPlot1

2 1

0 100 200 300 400

ym1 in voltsPlot2

3

10.1976m 10.1978m 10.1980m 10.1982m 10.1984m

time in seconds -2.00

-1.00 0 1.00 2.00

iml,im1 in amperesPlot3

45

VGS_ML VGS_MU

VDS_MU

I_MU VGS_ML

100 ns / div 200 V / div

(17)

Driver Comparison between Hard-Switching and Soft-Switching

Accurate Accurate

Dead time accuracy requirement

High High

Sink capability requirement

Low Medium

Source capability requirement

Soft-switching Hard-switching

(18)

The Solutions for High-Side Driver

• Transformer-based solution

– Single DRV input – Dual DRV inputs

• Silicon integrated circuit driver: dual outputs

– Single DRV input – Dual DRV inputs

(19)

Agenda

• Comparison

• Conclusions

(20)

Consideration as Designing Driver Transformer

• Ground-referenced floating drive – keep 500 V isolation if a 400 V pre-regulated PFC exists.

• Minimize the leakage inductance - the delay between output and input windings may kill the power MOSFETs.

• Follow Faraday’s law – keep V*T constant, otherwise, saturate.

• Keep enough margin from saturation – the worst case happens with transient load at high line.

• High permeability ferrite – minimize the I_M.

• Keep high sink current capability

(21)

Single DRV Input

• An ac coupling capacitor (C_C) is needed to reset the driver transformer flux.

• The amplitude of V_GS is dependent on duty. /

• With (-V_C) to turn off at steady state, but the sink capability is limited at start-up. /

• Need a fast time constant (L_M//R_GS * C_C) to avoid flux walking due to the fast transient.

• Watch out the ringing between C_C and drive transformer at skip mode or UVLO, a diode is needed to damp the ringing.

DRV

C_C R_C

+^V^C - Dead time generator

Driver

C M C

M

C C

L C

L

R ≥ Q1 =2

DRV

C DV

V =

V_DRV - V_C - V_C

R_GS

C_C to reset the driver transformer and R_C to damp the L-Cresonance.

5 .

1 =0

>

C M

C C

L Q R

(22)

Single DRV Input with DC Restore

• V_GS amplitude is independent on duty ratio at steady state.

• Limited sink capability. / DRV

C_C1 R_C

+ -^V^C Dead time generator Driver

C M

C C

R ≥ 2 L

DRV

C DV

V =

V_DRV- V_f - V_f

R_GS C_C2

+

V-_C-V_f

(23)

Single DRV Input with PNP Turn-Off

• A pnp transistor + diode help to improve the switching off.

DRV

Dead time generator Driver

(24)

Don’t Forget the AND Gate

• Add the totem-pole drivers if output capability of AND gate is limited.

• Is the design finished?

Î No, not yet. Pay attention to the ringing among C_C1, C_C2 and driver

transformer when skip or UVLO. A diode and resistor to damp the ringing. / DRV

Dead time generator High-side Driver

C_C1 C_C2

(25)

Dual Polarity Symmetrical DRV Inputs

• DRV_A and DRV_B are opposite-polarity and symmetrical Î no ac coupling capacitor.

• This is suitable for push-pull type circuit, e.g. LLC-HB, but NOT for asymmetrical type, e.g.

AHB or active clamp. /

• Pay attention to the flux of driver transformer at line/load transient.

• The strong turn off capability is still needed. /

• Pay attention to the delay caused by the leakage inductance. Î minimize the leakage inductance and use dual output windings instead of single output winding.

• Extra losses caused by voltage drop on R_off. / DRV_B

Driver ^V^DRV

- V_DRV

DRV_A

V_DRV

- V_f

R_off

(26)

The Driver Transformer

• Pros

– A transformer is more robust than a die!

– Less sensitivity to spurious noise and high dV/dt pulses – Cheap?

• Cons

– Complicated circuits

– Pay attention on extreme line/line condition & off mode ……

– Pay attention on the leakage inductance and isolation – Is the sink capability strong enough?

(27)

Agenda

• The all-silicon-solution

• Comparison

• Conclusions

(28)

IN Dead Time

Vcc

Gnd

in out

Vcc

Gnd

in out

M1

M2 VBoot

Vcc

Vbulk

DRV_HI

DRV_LO

GND GND_HI

Silicon Half Bridge Driver Principle

Integrated HB driver LLC converter

IN_HI

Vcc

Gnd

in out

Vcc

Gnd

in out

M1

M2 VBoot

Vcc

Vbulk

DRV_HI

DRV_LO

GND C1 GND_HI

IN_LO

• Principle

– Single or dual inputs – High & low side driver

Single Input

Dual Inputs

Integrated HB driver

(29)

Silicon Solution, What are its Limits?

• High-side isolation – 600 V is reached within the silicon.

• Matched propagation delay between high and low side drive – Prevents any unbalanced transformer usage.

• High side driver supply – Bootstrap supply is requested.

• Noise immunity – Negative voltage robustness of the high side driver.

(30)

Silicon Solution, High Voltage Isolation

IN_HI

Vcc

Gnd

in out

Vcc

Gnd

in out

M1

M2 VBoot

Vcc

Vbulk

DRV_HI

DRV_LO

GND GND_HI

S R Level Q

Shifter Pulse

Trigger

IN_LO

Floating area

• Pulse trigger: generates pulse on each edge from IN_HI input.

• Level shifter: shifts pulses from GND reference to GND_HI reference.

• SR flip flop: latches pulses information from the level shifter.

Level shifter sustains up to

600 V

(31)

IN_HI

Vcc

Gnd

in out

Vcc

Gnd

in out

M1

M2 VBoot

Vcc

Vbulk

DRV_HI

DRV_LO

GND GND_HI

S R Level Q

Trigger

IN_LO Delay

Silicon Solution, Matched Propagation Delay

Delay compensation

• Delay is inserted on the fastest path: Low side driver path

Î to compensate: Pulse trigger + level shifter and SR flip-flop delays.

(32)

Vcc

Gnd

in out

Vcc

Gnd

in out

M1

M2

Vbulk

DRV_HI

DRV_LO

GND Bridge Vboot

Cboot Dboot

Rboot

Vcc

Vcc

Vcc

CVcc

Silicon Solution, High Side Driver Supply

• Bootstrap technique is used for supplying the high side driver

Bootstrap connected to Vcc

Bootstrap Step:

• Step 1: M₂ is closed Î C_boot is grounded: C_boot is refueled via V_cc.

• Step 2: M₁ & M₂ are opened Î Bridge pin is floating, D_boot is

blocked & C_boot supplies floating area.

• Step 3: M₁ is closed Î bridge pin moved to bulk level, D_boot is still blocked & C_boot supplies floating area.

(33)

Root of High Side Driver Negative Voltage?

• Let’s focus on the half-bridge branch:

– the load connected to a half-bridge branch is inductive:

– like an LLC-HB

– Or with the most simple case in a synchronous buck (where body diodes of the mosfet are represented).

LLC-HB

M1

M2

Vbulk

Dbody1

Dbody2

(34)

Vbulk

Theory: Buck Converter Operation

• 1^st step of the buck converter:

Step 1:

M₁ ON M₂ OFF

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk M₁ ON

M₂ OFF

I_L

(35)

Vbulk

Theory: Buck Converter Operation

• 2^nd step of the buck converter:

Step 2:

M₁ OFF M₂ OFF

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ OFF

I_L

(36)

Vbulk

Theory: Buck Converter Operation

• 3^rd step of the buck converter:

Step 3:

M₁ OFF M₂ ON

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ ON

3

I_L

(37)

Vbulk

Theory: Buck Converter Operation

• 4^th step of the buck converter:

Step 4:

M₁ OFF M₂ OFF

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ OFF

3 4 1

I_L

(38)

Bench: Buck Converter Operation

• Anywhere but in a ppt file there are parasitic elements:

– True buck converter:

M1

M2

Vbulk

Dbody1

Dbody2

Parasitic inductances

Parasitic Capacitors

(39)

Vbulk

Bench: Buck Converter Operation

• 1^st step of the buck converter:

Step 1:

M₁ ON M₂ OFF

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk M₁ ON

M₂ OFF

I_L

(40)

Vbulk

Bench: Buck Converter Operation

• 2^nd step of the buck converter:

Step 2:

M₁ OFF M₂ OFF

I_L V_Bridge

I_L

Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ OFF

Time

1.453000ms 1.453200ms 1.453400ms 1.452846ms

V(BRIDGE) 0V

20.0V

-10.0V 31.8V

(41)

Bench: Buck Converter Operation

• 3^rd step of the buck converter:

Step 3:

M₁ OFF M₂ ON

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ ON

3

I_L

Vbulk

(42)

Vbulk

Bench: Buck Converter Operation

• 4^th step of the buck converter:

Step 4:

M₁ OFF M₂ OFF

V_Bridge Time

Time V_Bridge

Step: 1

V_Bulk

-V_f

2

M₁ OFF

M₂ OFF

3 4 1

I_L

(43)

Bench: Buck Converter Operation

• Negative voltage on bridge pin will create negative current injection inside the IC driver.

IN_HI

Vcc

Gnd

in out

M1

M2 VBoot

Vcc

Vbulk

DRV_HI

DRV_LO

GND Bridge

S R Level Q

Trigger

IN_LO Delay

Vcc

Gnd

in out V_Bridge

Floating area

Leaky path when V_Bridge < 0V

This leakage path could create some trouble inside the driver IC.

(44)

How to Characterize the Negative Voltage?

Time V_Bridge

V_Bulk

-V_f

Time V_Bridge

Width

Principle:

¾ Negative pulse is added on bridge pin:

¾ With adjustable Negative voltage

¾ And adjustable Width

V_neg

At each pulse width the neg. voltage is increased until the driver IC fails.

(45)

How the Negative Voltage has Been Created?

L1

100uH IN_LO

IN_HI

C7 10uF 25V

C19 100nF

C3 220uF 50V

D13 D1N4148

Rload 10R

Pulse gen. 0

0

VCC

D14 D1N4148

TX1

BZX84C18 D5 BZX84C18 D6

C13 100n

Q4 FDP3682 Q5 FDP3682

Q6 FDP3682 VCC

Vout

BZX84C18 D7 R10

47k

0

C4 330uF 100V

C12 100nF

Rload1 10R VDC_IN

20V

D11 D1N4148 U1

NCP5106A VCC 1

IN_HI 2

IN_LO 3

GND 4

DRV_LO 5 BRIDGE 6 DRV_HI 7 VBOOT 8

0

R1 1R R2

10R Q1 Q2N2907

R3 10R Q2 Q2N2907

Vneg 0Vdc to 50V D4

MBR1100 R4

10R C11

100n

U5 MC33152

1 2

Sync

R8 47k

R9 47k

Synchronous Buck Converter

Negative pulse generation IC Driver

Adj. V_Neg Adj. pulse

width

(46)

Example of Negative Voltage Measurement

VG_LO (10 V/div) VG_HI (10 V/div)

Vbridge pin (20 V/div)

Time

(80 ns/div) Width = 150 ns

V_neg = -18 V When the bridge pin is released, it generates some

noise on the hi- side driver.

Note: Negative voltage pulse is applied when the bridge pin voltage is reaching zero.

(47)

Negative Voltage versus Neg. pulse duration @ +25°C

-35 -30 -25 -20 -15 -10 -5 0

0 100 200 300 400 500 600

Negative pulse duration (ns)

Negative pulse voltage (V)

Negative Voltage Characterization

If the negative pulse is inside this area, the driver will not work properly or can be damaged.

If the negative pulse is inside this area, the driver will work properly.

(48)

Negative Voltage Characterization in Temperature

Negative Voltage versus Neg. pulse duration @ different Temp

-35 -30 -25 -20 -15 -10 -5 0

0 100 200 300 400 500 600

Negative pulse duration (ns)

Negative pulse voltage (V)

-40°C 25°C 125°C

• Note: These characterizations will be available in each IC driver datasheet

(49)

Driver IC Remarks

• ON Semiconductor defines electrical parameters on overall temperature range (here -40℃ < T_j < +125 ℃). See

electrical table & characterization curves.

• Competitors define the electrical parameters only at T_amb = +25℃. Temp characterization is not always available

Î what about min & max over extended temperature range?

• The competitors values extracted from the curves probably do not take into account the lot to lot process variations

Î the range variation is probably wider.

(50)

ON Semiconductor IC Driver Cross Reference

•3.3 V CMOS/TTL input

•Internal fixed dead time 650 ns

•One pin for creepage IR2111 –

IRS2111, NA

30 ns / 60 ns 750 ns /

100 ns 85 ns /

35 ns NCP5111

•3.3 V CMOS/TTL input

•Internal fixed dead time 520 ns IR2104 –

IRS2104 NA

10 ns /45 ns 620 ns /

100 ns 85 ns /

35 ns NCP5104

•3.3 V CMOS/TTL inputs

•Internal fixed dead time 100 ns IR2304 -

IRS2304, L6388/84 FAN7380 3

20 ns / 35 ns 100 ns /

100 ns 85 ns /

35 ns NCP5304

•3.3 V CMOS/TTL inputs

•Internal fixed dead time 100 ns IR2106 –

IRS2106, FAN7382 20 ns / 35 ns 3

100 ns / 100 ns 85 ns /

35 ns NCP5106B

•3.3 V CMOS/TTL inputs IR2106 –

IRS2106, FAN7382 -

20 ns / 35 ns 100 ns /

100 ns 85 ns /

35 ns NCP5106A

•3.3 V CMOS/TTL inputs IR2181 –

IRS2181 -

20 ns / 35 ns 100 ns /

100 ns 40 ns

/ 20 ns NCP5181

Remarks Pin-Out

Compati- bility Cross

Conduction Protection Matching

Delay Typ / Max Propag.

Delay typ.

t_ON/ t_OFF Drive trise /

tfall typ.

(C_L=1 nF)

(51)

Agenda

• Comparison

• Conclusions

(52)

3 26 L1

5 4

8 T1 XFMR

C1

C3a 1mF

7 C8 100p

R14 10k R15 15

D4 1N4148 17

28 M1 IRFB11N50A

24 M2 IRFB11N50A

40 16 U2 TL431

13 R6 10k

out

R7 86k

R8 10k C5

470p L3 4.7uH

C2 680uF

Part number = EEUFC1V681

int out

int

10 R1 22k

C4 10n

R2 22k

18 C6

470p R3

22k

C7 C10

+400 V

0 V R5

47k

R9 47k

45 11 2

30 12

42 14

41

19

23 1

2 3 4 5

8 6 7

9 10 11 12 13 14 15 29 16

37 38

39 6

1 31

NCP1395A

timer

BO

analog ground

C15 100n

C18 22u R16

R24 250k 75k

R11 160k C19 10u

R12150k C20 10u R195.2k 10n C14

C13 U5A

SFH615-A

C11 10n

R22 4.7k R25 1.8Meg

100n

540

R23 10k

U5B SFH615-A Vcc

InA

InB

Gnd

OutA

OutB VB

Gnd

C3b 1mF

C3c 1mF

Part number = EEUFC1V102 Irms=5 A

24 V / 10 A P = 4W

22nF

Part number = PHE450MB5220JR06 C1

0.47uF

Part number = PHE450MF6470JR06L2 C7

100uF

Part number = 2222-05737101 C10

Snap-in BC Comp. 450 V EVOX RIFA 630 V EVOX RIFA 630 V

D3 mbr1645

D6 mbr1645 D11 mbr1645 D12

mbr1645 Heatsink 18°C/W KL112-25

L1 PCV-0-274-04 220u

1 kV

PCV-0-472-20L

ETD44 ET4415A KL195/25,4SW

KL195/25,4SW R32

33k

R33 5.6k

FF

20

21 25

22 T2 Q3903-A

D15 1n5818

D17 1n5818

. .

Vcc

D5 1n5818 D7 1n5818

R17 1k R18 1k

27 D10 1N4148

R20 10

32 R21 1k

33 R4 1k 34 D8 1N4148 R10

10

.

Vcc

C16 10u C17 0.1u

R30 47k

R29 47k

1

6 2 5 3 4 Q1

2N2222

Q5 2N2907

Q2 2N2222

Q6 2N2907

Q10 2N2907

Q11 2N2907

LLC-HB Schematic with Driver Transformer

• LLC-HB with 24 V @ 10 A

• NCP1395, the LLC controller with dual DRV outputs.

• Transformer drivers the MOSFETs of LLC converter.

Driver Transformer LLC controller

NCP1395

(53)

3 26 L1

5 4

8 T1 XFMR

C1

C3a 1mF

7 C8 100p

R14 10k R15 15

D4 1N4148 17

28 M1 IRFB11N50A

24 M2 IRFB11N50A

40 16 U2 TL431

13 R6 10k

out

R7 86k

R8 10k C5

470p L3 4.7uH

C2 680uF

Part number = EEUFC1V681

int out

int

10 R1 22k

C4 10n

R2 22k

18 C6

470p R3

22k

C7 C10

+400 V

0 V R5

47k

R9 47k

45 11 2

30 12

42 14

41 35

23 1

2 3 4 5

8 6 7

9 10 11 12 13 14 15 29 16

37 38

39 6

1 31

NCP1395A

timer

BO

analog ground

C15 100n

C18 22u R16

R24 250k 75k

R11 160k C19 10u

R12 150k C20 10u R19 5.2k 10n C14

C13 U5A

SFH615-A

C11 10n

R22 4.7k R25 1.8Meg

100n

540

R23 10k

U5B SFH615-A Vcc

InA

InB

Gnd

OutA

OutB VB

Gnd

C3b 1mF

C3c 1mF

Part number = EEUFC1V102 Irms=5 A

24 V / 10 A P = 4W

22nF

Part number = PHE450MB5220JR06 C1

0.47uF

Part number = PHE450MF6470JR06L2 C7

100uF

Part number = 2222-05737101 C10

Snap-in BC Comp. 450 V EVOX RIFA 630 V EVOX RIFA 630 V

D3 mbr1645

D6 mbr1645 D11 mbr1645 D12

mbr1645 Heatsink 18°C/W KL112-25

L1 PCV-0-274-04 220u

1 kV

PCV-0-472-20L

ETD44 ET4415A KL195/25,4SW

KL195/25,4SW R32

33k

R33 5.6k

FF

1 2 3

4 5

8

6 7

51 44 36 U1 NCP5181

25 D1 1N4937

R13 10

C9 100nF

R26 10

R27 10 C12

100n

D2 1N4148

D9 1N4148 R28

47k

R31 47k

LLC-HB Schematic with Driver IC

• LLC-HB with 24 V @ 10 A

• NCP1395, the LLC controller with dual DRV outputs.

• NCP5181, driver IC drives the MOSFETs of LLC converter.

LLC controller NCP1395

Driver IC NCP5181

(54)

V

_GS

Waveform

• The waveforms seem similar.

Driver transformer Driver IC (NCP5181)

V_{GS_ML} (5 V/div)

V_{GS_MU} (5 V/div) I_MU

(2 A/div)

V_{DS_ML} (100 V/div)

2 µs / div

(55)

High Side MOSFET Turns Off

• The driver IC turns off the MOSFETs more vigorously.

• IC turn-off is 70 ns faster, lowering the switching losses

Turn-off comparison

80 ns / div

V_{GS_ML} (5 V/div)

(2 A/div) V_{DS_ML} (100 V/div)

(56)

High side MOSFET Turns On

• The driver IC keeps safe and enough dead time between high and low side MOSFETs.

200 ns / div

Turn-on comparison

V_{GS_ML} (5 V/div)

(2 A/div) V_{DS_ML} (100 V/div)

(57)

The Efficiency Comparison

• There is no efficiency difference between the IC driver and transformer solutions.

Input power

(W)

Output power

(W)

Vout (V)

Iout

(A) η

128.33 119.72 23.96 5.00 93.29%

257.2 235.46 23.57 9.99 91.55%

128.34 119.72 23.96 5.00 93.29%

258.5 236.46 23.67 9.99 91.48%

Driver Transformer

Driver IC

(58)

Agenda

• Comparison

• Conclusions

(59)

Conclusion: Transformer or IC?

• Both solutions work if well-trimmed.

• We recommend the IC solution because:

– We don’t sell the transformer.

– Manual insertion for the transformer.

– Ease the layout – Ease the design

– Free of transformer problems, e.g.:

• isolation is destroyed,

• flux walking away,

• unexpected ringing after turn off,

• Height of the transformer in low profile PSU

(60)

For More Information

• View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com

• View reference designs, design notes, and other material supporting the design of highly efficient power supplies at

www.onsemi.com/powersupplies