C-12-41 LSI Implementation of a Bit-Parallel Cellular Multiplier over GF(24) using Charge-Sharing Symmetric Adiabatic Logic.

Title

C-12-41 LSI Implementation of a Bit-Parallel Cellular Multiplier

over GF(24) using Charge-Sharing Symmetric Adiabatic Logic.(

本文(Fulltext) )

Author(s)

MONTEIRO, Cancio; TAKAHASHI, Yasuhiro; SEKINE,

_Toshikazu

Citation

[電子情報通信学会ソサイエティ大会講演論文集] vol.[2013]

_{no.[2] p.[101]-[101]}

Issue Date

2013-09-03

Rights

copyright 2013 IEICE

Version

出版社版 (publisher version) postprint

URL

http://hdl.handle.net/20.500.12099/53352

Institute of Electronics, Information, and Communication Engineers

NII-Electronic Library Service

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C-12-41

LSI

Implementation

of

a

Bit-Parallel

Cellular

Multiplier

over

GF(24)

using

Charge-Sharing

Symmetric

Adiabatic

Logic.

Cancio

Monteiroi

Yhsuhiro

Takahashi2

[[bshikazu

Sekine2

Graduate

School

of

Engineering,

C;ifu

Universityifecu}ty

of Engineering,

Gifu

IJniversity2

Abstract

This

paper

presents

a verification of

the

oporating speed

in

a

bit-paraltel

cellu]ar multiplier over

GF(24)

using a secure

dual-rail chargffsharing symmetric

adiabatic

logic.

The

multiplier

LSI

uhip nieasured

in

thls

work was

labricated

using

O.IS

ptm

C]MOS

process

technology.

Maximum

power

clock

frequency

for

chip measurement

is

5

MHz,

whereas

the

post-layout

simulation

is

up

to

50

MHz

aJid

the

pre-laorout

simulatioll reaches l25

MHz

using

the

same

individual

logic,

1

Introduction

Finitc

field

arithmetic

has

_played

an

important

role

in

modern

coding

theory,

computer

algebra,

and

cryp-tographic

system.

Ftom

the

yiew

peint

of

the

crypto-graphic

hardware

implementation,

one of

the

main

is-sues

is

related

to

the security of

_processed

iilformation.

Apart

form

the

secure

logic

ability

to

wlthstand

side

channel

analysis

attacks,

the

_power

eMciency isalso a

dernand

of our society.

Tb

the

best

of our

knowledge,

many works on secure

logic

design

in

the

simulation

level

and

further

in

the

LSI

implernentation

have

been

done

in

the

conventional CMOS

logic

operation,

As

a result,

thc

high

dynamic

_power

consumption

becomes

a challenge and

the

motivation

in

our work.

In

our approach

for

secure

and

low-power

logic

implementa-tion,

we

have

designed

a

new secure

logic

style

tliat

is

based

on

the

a[liabatic switching

_principle

[1].

The

full

custom

layout

was

designed

in

cadence virtuoso

IC6.1

with

the

chip

size

of 172×

155

pam2

[2].

In

this

work,

the

fabricated

LSI

chip measurement

is

conducted.

The

operating speed of the mukiplier in

the

LSI

ls

checked and compared with

the

_prfflasout

and

the

_post-layout

simulation result,

2

LSI

Measurement

Result

The

circuit schematic of

the

bit-parallel

cellular

multiplier over

GF(24)

and

the

_{photomicrograph}

are

shown

in

Figs.

1(a),(b),

respectively,

As

shown

in

Fig.

(a)

that

the

inner

cell composes of

dual-ii'Lput

AND

and

XOR

togic,

where

those

individ-ual

logic's

transistor

schematic

can

be

found

in

[1].

The

LSI

measurement result of

the

input

and

out-put

signals at

1.25

MHz

_power

clock

frequency

is

shown

in

Fig,

2,

In

this

measurement,

the

in-put

signals

of

the

Inl=

{AO,Al,A2,A3,A4},

Jn2=

{BO,Bl,B2,B3,B4}="1",

thus

the

output

voltage

of a multiplier

{CO,Cl,C2,C3,C4}

are corrently

pre-duced

as

Out="1".

The

Vpc

supply current

in

the

bottom

of

Flg,

2

indicates

that

the

_peak

current

is

uniformly

_plotted

which

may

resistive

to

side

channel

analysis attacks.

(a)

Cb)

Fig,

1

(a)

Circuit

structure of the

bit-parallel

cellular

multiplier

over

GF(24),

(b)

Photomicrograph

of

the

bit-paJrallel

cellu]ar

multiplier over

GF(24).

vpe ",:V

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;/

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A.iA.,.,A...LmaAw(･

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t

Et:llD:vl' t

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ov 1.ev lnl ov 1.ev 1ma ov 1,evOutpat ov I s,pp+y.C.'.rreni

Fig.

2

Input

and output signals ofthe

bit-parallel

cel-lular

multiplier oveT

CF(24)

from

the measuremeiit re-sult.

3

Conclusion

We

have

verified a multiplier

logic

functionality

in

the

LSI

measurement

that,

the

output

voltages

are

cor-rectly

measures,

The

maximum operating

_power

clock

frequency

in

the

measurement

is

5

MHz,

which

is

slow

down

from

50

MHz

in the

_post-layout

simulation and a

hundred

times

speed

down

from

_prelayout

simulation

using

the

sarne

individual

logic.

Referenoes

[11

C.

Monteiro,

Y.

Takahashi,

and

T.

Sekine,

``Charge-sharing

symmetric

adiabatic

Logic

in

counterTneasure aguinst power

analysis attacks at cell

leve1,"

thcrvetectronics

Jeurnat,

vol.44, no.6,

_pp.496-503,

June

2013.

[2]

C.

Monteiro,

Y.

Talcahashi,

alld

Fl'.

Sekine,

"Lew

power

cure

CSSAL

bit-parallel

multiplier over

GF(24)

in

O,18pm

CMOS

technology,"

in

Proc.

IEEE

ECCTD,

Dresden,

rnany,

Sept.

8-12,

2013,

(Accepted)

201319/17-20

reMpt

(=

tze

101

-n;Oxssraitscse2)

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