NCP1562A, NCP1562B PWM Controller, High Performance, Active Clamp / Reset

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PWM Controller, High

Performance, Active Clamp / Reset

The NCP1562x is a family of voltage mode controllers designed for dc--dc converters requiring high--efficiency and low parts count.

These controllers incorporate two in phase outputs with an overlap delay to prevent simultaneous conduction and facilitates soft switching. The main output is designed for driving a forward converter primary MOSFET. The secondary output is designed for driving an active clamp circuit MOSFET, a synchronous rectifier on the secondary side, or an asymmetric half bridge circuit.

The NCP1562 family reduces component count and system size by incorporating high accuracy on critical specifications such as maximum duty cycle limit, undervoltage detector and overcurrent threshold. Two distinctive features of the NCP1562 are soft--stop and a cycle skip current limit with a time threshold. Soft--stop circuitry powers down the converter in a controlled manner if a severe fault is detected. The cycle skip detector enables a soft--stop sequence if a continuous overcurrent condition is present.

Additional features found in the NCP1562 include line feed-- forward, frequency synchronization up to 1.0 MHz, cycle--by--cycle current limit with leading edge blanking (LEB), independent under and overvoltage detectors, adjustable output overlap delay, programmable maximum duty cycle, internal startup circuit and soft--start.

Features



Dual Control Outputs with Adjustable Overlap Delay



>2.0 A Output Drive Capability



Soft--Stop Powers Down Converter in a Controlled Manner



Cycle--by--Cycle Current Limit



Cycle Skip Initiated if Continuous Current Limit Condition Exists



Voltage Mode Operation with Input Voltage Feedforward



Fixed Frequency Operation up to 1.0 MHz



Bidirectional Frequency Synchronization



Independent Line Undervoltage and Overvoltage Detectors



Accurate Programmable Maximum Duty Cycle Limit



Programmable Maximum Volt--Second Product



Programmable Soft--Start



Internal 100 V Startup Circuit



Precision 5.0 V Reference



These are Pb--Free Devices Typical Applications



Telecommunications Power Converters



Low Output Voltage Converters using Control Driven Synchronous Rectifier



Industrial Power Converters

TSSOP--16 DT SUFFIX CASE 948F

x = Current Limit (A, B) A = Assembly Location WL, L = Wafer Lot

Y = Year

WW, W = Work Week G orG = Pb--Free Package

MARKING DIAGRAMS

NCP 562x ALYWG

G http://onsemi.com

SO--16 D SUFFIX CASE 751B

See detailed ordering and shipping information in the package dimensions section on page 24 of this data sheet.

ORDERING INFORMATION NCP1562xG

AWLYWW 1

16

(Note: Microdot may be in either location)

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Figure 1. Detailed Block Diagram

Vin 1

16 VAUX

Iinhibit Istart

Disable

+--

VAUX(on)

+--

Central Logic

Disable_VREF

5.0 V Reference VAUX P.O.R.

Bias VREF

8

S Dominant Reset Latch R

Q CAUX

VAUX(on)/ VAUX(off1)/ VAUX(off2) +

--

+ --

One Shot Pulse

VUV Soft--Stop Complete Thermal

Shutdown

UVOV STOP Detector UVOV

Vin

R2 R1

2 V 3 V

Vref

CT

RT 6

RTCT 500mA

SYNC DMAX

Clock Oscillator

7 SYNC

+ -- CSKIP Comparator

+ --VCSKIP CSKIP

Control Logic VREF

ICSKIP(C)

ICSKIP(D) 12

CSKIP CCSKIP

Clock

+-- Not Saturated

+ --3.6 V Saturation

Comparator S Dominant Reset Latch R

Q

Q Clock

FF Reset Delay Logic Enable_Output

OUT1 15 VAUX

14 PGND

OUT2 13 VAUX

11

270 kΩ 20 kΩ VREF

+-- PWM Comparator

-- +

Soft--Start Comparator

-- + FF

Comparator +

--0.2 V 3 V

+ --

Vin

RFF

CFF VEA

FF 3

5 GND FF Reset

Ilimit Comparator --+

+

-- 0.2 V = A ver.

(0.5 V = B ver.) OUT

Fixed 80 ns LEB Clock

Enable Not Saturated

Soft--Start Soft--Stop

Control Logic STOP VX Soft--Start

Complete Soft--Stop

Complete VREF

ISS(C)

ISS(D) 10 CSS SS

4 CS

Enable_Output 1 V

2

tD RD

9

VX

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PIN FUNCTION DESCRIPTION

Pin Symbol Description

1 V_in Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant current source supplies current from this pin to the capacitor connected to the V_AUXpin, eliminating the need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.

2 UVOV Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).

The minimum and maximum input supply voltage thresholds are adjusted independently. A UV condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain3% accuracy allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.

3 FF An external R--C divider from the input line generates the Feedforward Ramp. This ramp is used by the PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively grounded until the next cycle begins.

4 CS Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converter operates in cycle--by--cycle current limit. Once a current limit pulse is detected, the cycle skip timer is enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.

The leading edge blanking is disabled during soft--start and output overload conditions to improve the response to faults.

5 GND Control circuit ground. All control and timing components that connect to GND should have the shortest loop possible to this pin to improve noise immunity.

6 R_TC_T An external R_T--C_Tdivider from V_REFsets the operating frequency and maximum duty cycle of OUT1.

The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is generated by sequentially charging and discharging C_T. The peak and valley of the Ramp are accurately controlled to provide precise control of the duty cycle and frequency. The outputs are disabled during the C_Tdischarge time.

7 SYNC Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices to synchronize together. The lower frequency device becomes the slave. It can also synchronize to an external signal.

8 V_REF Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference with a capacitor. The recommended capacitance range is between 0.047mF and 1.0mF.

9 V_EA The error signal from an external error amplifier is fed to this input and compared to the Feedforward Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.

10 SS A 10mA current source charges the external capacitor connected to this pin. Duty cycle is limited during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip fault is detected, the SS capacitor is discharged in a controlled manner with a 100mA current source. The duty cycle is then slowly reduced until reaching 0%.

11 t_D An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2 transitions.

12 CSKIP The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault and the time the converter is disabled are programmed by the capacitor (C_CSKIP) connected to this pin.

The cycle skip timer is enabled after a current limit fault is detected. Once enabled, C_CSKIPis charged with a 100mA source. If the overcurrent fault is removed before entering the soft--stop mode, the capacitor is discharged with a 10mA source. Once C_CSKIPreaches 3.0 V, the converter enters a soft--stop mode and C_CSKIPis discharged with a 10mA source. The converter is re--enabled once C_CSKIPreaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, C_CSKIP discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.

13 OUT2 Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay against OUT1. OUT2 has source and sink resistances of 12Ω(typ.). OUT2 is designed to handle up to 1.0 A.

14 PGND Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.

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PIN FUNCTION DESCRIPTION(continued)

Pin Symbol Description

15 OUT1 Main output of the PWM Controller. OUT1 has a source resistance of 4.0Ω(typ.) and a sink resistance of 2.5Ω(typ.). OUT1 is designed to handle up to 2.5 A. OUT1 trails OUT2 during a low to high transition and leads OUT2 during a high to low transition.

16 V_AUX Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from V_into this pin. Once the voltage on V_AUXreaches approximately 10.3 V, the current source turns OFF and the outputs are enabled. It turns ON again once V_AUXfalls to 8.0 V. If the bias current consumption exceeds the startup current, V_AUXwill continue to discharge. Once V_AUX reaches 7.0 V, the outputs are disabled allowing V_AUXto charge. During normal operation, power is supplied to the IC via this pin by means of an auxiliary winding. The startup circuit is disabled once the voltage on the V_AUXpin exceeds 10.3 V. If the V_AUXvoltage drops below 1.2 V (typ), the startup current is reduced to 200mA.

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MAXIMUM RATINGS(Notes 1 and 2)

Rating Symbol Value Unit

Line Voltage V_in 100 V

Auxiliary Supply, OUT1, OUT2 V_AUX, V_outx 20 V

All Other Inputs/Outputs Voltage V_IO 10 V

All Other Inputs/Outputs Current I_IO 5.0 mA

5.0 V Reference Output Current I_REF 10 mA

5.0 V Reference Output Voltage V_REF --0.3 to 6.0 V

OUT1 Peak Output Current (D = 2%) I_out1 2.5 A

OUT2 Peak Output Current (D = 2%) I_out2 1.0 A

Operating Junction Temperature T_J –40 to +125 _C

Storage Temperature Range T_stg –55 to +150 _C

Power Dissipation (T_A= 25_C, 2.0 Oz Cu, 1.0 Sq Inch Printed Circuit Copper Clad) DT Suffix, Plastic Package Case 948F (TSSOP--16)

D Suffix, Plastic Package Case 751B (SO--16)

P_D

0.75 0.95

W

Thermal Resistance, Junction to Ambient (2.0 Oz Cu Printed Circuit Copper Clad) DT Suffix, Plastic Package Case 948F (TSSOP--16)

0.36 Sq In 1.0 Sq In

D Suffix, Plastic Package Case 751B (SO--16) 0.36 Sq In

1.0 Sq In

R_θJA

155 133 120 105

_C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. This device series contains ESD protection and exceeds the following tests:

Pins 2--16: Human Body Model 2000 V per MIL–STD–883, Method 3015.

Machine Model Method 160 V.

Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 100 V.

2. This device contains Latchup protection and exceeds100 mA per JEDEC Standard JESD78.

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ELECTRICAL CHARACTERISTICS(V_in= 48 V, V_AUX= 12 V, V_UVOV= 2.3 V, V_EA= open, V_CSKIP= 0 V, V_CS= 0 V, V_SS= open, R_T= 13.3 kΩ, C_AUX= 10mF, C_T= 470 pF, C_out1= C_out2= 100 pF, C_UVOV= 0.01mF, C_CSKIP= 6800 pF, R_D= 25 kΩ, R_SYNC= 5.0 kΩ, C_REF= 0.1mF, R_FF= 29.4 kΩ, C_FF= 470 pF. For typical values T_J= 25C, for min/max values, T_Jis – 40C to 125C, unless otherwise noted.)

Characteristic Symbol Min Typ Max Unit

STARTUP CONTROL AND V_AUXREGULATOR V_AUXRegulation (V_UVOV= 0 V)

Inhibit Threshold Voltage

Startup Threshold/V_AUXRegulation Peak (V_AUXIncreasing) Operating V_AUXValley Voltage

Minimum Operating V_AUXValley Voltage after Turn--On (V_UVOV= 2.3 V, V_EA= 0 V)

V_inhibit V_AUX(on) V_AUX(off1) V_AUX(off2)

– 9.65 7.42 6.50

1.15 10.3 8.0 7.0

1.5 10.97

8.48 7.42

V

Minimum Startup Voltage (Pin 1)

I_AUX= 1.0 mA, V_AUX= V_AUX(on)– 0.2 V V_start(min)

– – 23.2 V

Inhibit Bias Current

V_AUX= 0 V I_inhibit 70 170 300

mA Startup Circuit Output Current

V_AUX= V_inhibit+ 0.2 V V_AUX= V_AUX(on)– 0.2 V

I_start1 I_start2

7.16 4.03

9.3 6.1

11.3 8.1

mA

Startup Circuit Off--State Leakage Current (V_in= 200 V, V_UVOV= 0 V) T_J= 25_C

T_J= –40_C to 125_C

I_start(off)

– –

25 –

50 100

mA

Startup Circuit Breakdown Voltage (Note 3) I_start(off)= 50mA, T_J= 125_C

V_BR(DS)

100 – –

V

Auxiliary Supply Current after V_AUXTurn--On Outputs Disabled

V_UVOV= 0 V V_EA= 0 V Outputs Enabled

V_EA= 4.0 V

I_AUX1 I_AUX2 I_AUX3

– – –

3.0 4.2 5.5

3.6 4.94

7.0

mA

LINE UNDER/OVERVOLTAGE DETECTOR

Undervoltage Threshold (V_inIncreasing) V_UV 1.979 2.05 2.116 V

Undervoltage Hysteresis V_UV(H) 0.074 0.093 0.118 V

Undervoltage Ratio (V_UV(H)/V_UV) V_UV(ratio) 3.65 4.50 5.62 %

Overvoltage Threshold (V_inIncreasing) V_OV 2.80 2.95 3.10 V

Overvoltage Hysteresis V_OV(H) 0.075 0.093 0.127 V

Offset Current (V_UVOV= 2.8 V) Ioffset(UVOV) 38 48 58 mA

Offset Current Turn ON Threshold (5%, Ioffset(UVOV)= 40mA) Voffset(UVOV) 2.4 2.6 2.8 V LINE FEEDFORWARD

Peak Voltage (Volt--Second Clamp) V_FF(peak) 2.8 3.0 3.2 V

Discharge Current (V_FF= 0.5 V, V_SS= 0 V) I_FF(D) 8.5 – – mA

Offset Voltage (V_FF= 0 V, Ramp Down V_SS) V_offset(FF) 0.118 0.185 0.268 V

Feedforward Offset Minus Soft--Stop Reset Voltage Δ_(FF--SS) 7 70 183 mV

3. Guaranteed by design only.

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ELECTRICAL CHARACTERISTICS(continued)(V_in= 48 V, V_AUX= 12 V, V_UVOV= 2.3 V, V_EA= open, V_CSKIP= 0 V, V_CS= 0 V, V_SS= open, R_T= 13.3 kΩ, C_AUX= 10mF, C_T= 470 pF, C_out1= C_out2= 100 pF, C_UVOV= 0.01mF, C_CSKIP= 6800 pF,

R_D= 25 kΩ, R_SYNC= 5.0 kΩ, C_REF= 0.1mF, R_FF= 29.4 kΩ, C_FF= 470 pF. For typical values T_J= 25C, for min/max values, T_Jis – 40C to 125C, unless otherwise noted.)

CURRENT LIMIT AND THERMAL SHUTDOWN Cycle–by–Cycle Threshold Voltage (V_out= 10 V)

NCP1562A NCP1562B

V_ILIM

191 472

203 495

217 512

mV

Propagation Delay to Output

(V_CS= V_ILIMto 1.0 V, LEB Disabled, V_out= 10 V) T_J= 25_C

T_J= –40_C to 125_C

t_ILIM

–

– 78

– 90

110

ns

Thermal Shutdown Threshold (Junction Temperature Increasing, Note 4) T_SHDN – 160 – _C

Thermal Shutdown Hysteresis (Temperature Decreasing, Note 4) T_H – 25 – _C

LEADING EDGE BLANKING

Offset Voltage VLEB(offset) – 10 – mV

Blanking Time t_LEB 50 80 110 ns

V_EAThreshold the Disables LEB (Measured together with t_LEB) V_LEB(dis) 4.1 – – V CYCLE SKIP CURRENT LIMIT MODE

Charge Current (V_CSKIP= 1.25 V) I_CSKIP(C) 70 90 111 mA

Discharge Current (V_CSKIP= 1.25 V) I_CSKIP(D) 6.5 8.6 11 mA

Number of Pulses to Exit Cycle Skip Mode Pulse_CSKIP – 3 – --

Upper Threshold Voltage (Ramp up V_CSKIP, V_CS= 1.0 V) VCSKIP(peak) 2.83 3.03 3.24 V

Lower Threshold Voltage (Ramp down V_CSKIP) VCSKIP(valley) 0.39 0.465 0.52 V

Threshold Voltage Hysteresis V_CSKIP(H) – 2.5 – V

5.0 V REFERENCE

Output Voltage (I_REF= 0 mA) V_REF 4.9 5.0 5.1 V

Load Regulation (I_REF= 0 to 5.0 mA) V_REF(Load) – 16 50 mV

Line Regulation (V_AUX= 7.5 to 20 V, I_REF= 0 mA) V_REF(line) – 10 50 mV

Discharge Current (V_UVOV= 0 V, V_REF= 2.5 V) I_REF(D) 3.8 – – mA

OSCILLATOR Frequency T_J= 25_C

T_J= --40_C to 125_C

f_OSC

222 211.2

246 –

272.2 277.2

kHz

Peak Voltage V_RTCT(peak) -- 2.95 -- V

Valley Voltage VRTCT(valley) -- 2.1 -- V

Discharge Current (V_RTCT= 2.3 V) I_RTCT -- 490 -- mA

Maximum Operating Frequency (Note 4) f_MAX 1.0 – – MHz

Duty Cycle (R_D= 25 kΩ) D 58.5 62.0 64.7 %

Adjustable Maximum Duty Cycle (Note 4) D_MAX 85 -- -- %

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ELECTRICAL CHARACTERISTICS(continued)(V_in= 48 V, V_AUX= 12 V, V_UVOV= 2.3 V, V_EA= open, V_CSKIP= 0 V, V_CS= 0 V, V_SS= open, R_T= 13.3 kΩ, C_AUX= 10mF, C_T= 470 pF, C_out1= C_out2= 100 pF, C_UVOV= 0.01mF, C_CSKIP= 6800 pF,

R_D= 25 kΩ, R_SYNC= 5.0 kΩ, C_REF= 0.1mF, R_FF= 29.4 kΩ, C_FF= 470 pF. For typical values T_J= 25C, for min/max values, T_Jis – 40C to 125C, unless otherwise noted.)

SYNCHRONIZATION

Output Pulse Width t_O(SYNC) 70 110 -- ns

Output Voltage High (R_SYNC=∞) V_H(SYNC) – 4.3 – V

Sync Threshold Voltage (Note 5) V_SYNC 3.5 – – V

Sync Input Pulse Width (V_SYNC= 3.5 V) t_SYNC -- – t_O(SYNC)min ns

Maximum Sync Frequency (Note 5) f_SYNC – – 1.0 MHz

Source Current (Note 5) I_SYNC(D) – 1.0 – mA

SOFT--START/STOP

Charge Current (V_SS= 1.6 V) I_SS(C) 8.3 10.2 13.1 mA

Discharge Current (V_UVOV= 0 V, V_SS= 1.6 V) I_SS(D) 72 95 115 mA

Soft--Stop Reset Voltage (V_FF= 0 V) V_reset(SS) – 115 -- mV

OUTPUTS

Overlap Time Delay (Tested at 50% of Waveform) Leading

Trailing

t_D(leading) tD(trailing)

37 72

45 90

-- --

ns

Output Voltage (I_OUT= 0 mA, Note 5) Low State

High State

V_OL V_OH

– 11.8

– –

0.25 –

V

Drive Resistance (FT ONLY)

OUT1 Sink (V_RTCT= 4.0 V, V_out1= 1.0 V) T_J= 25_C

T_J= –40_C to 125_C

OUT1 Source (V_RTCT= 2.5 V, V_out1= 11 V) T_J= 25_C

T_J= –40_C to 125_C

OUT2 Sink (V_RTCT= 4.0 V, V_out2= 1.0 V) T_J= 25_C

T_J= –40_C to 125_C

OUT2 Source (V_RTCT= 2.5 V, V_out2= 11 V) T_J= 25_C

T_J= –40_C to 125_C

R_SNK1

R_SRC1

R_SNK2

R_SRC2

– – – – – – – –

2.8 – 4.7

– 11.4

– 11.6

–

3.6 5.03 5.75 7.45 12.7 20.0 13.5 20.0

Ω

Rise Time (10% to 90%, C_out1= 2200 pF, C_out2= 220 pF) OUT1

OUT2

t_r1 t_r2

– –

26 19

– –

ns

Fall Time (90% to 10%, C_out1= 2200 pF, C_out2= 220 pF) OUT1

OUT2

t_f1 t_f2

– –

10 10

– –

ns

PWM COMPARATOR

Input Resistance R_IN(VEA) 11 25 58 kΩ

Lower Input Threshold V_EA(L) 0.48 0.83 1.04 V

Delay to Output (From V_OHto 0.5 V_OH) t_PWM – 100 – ns

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Vinhibit,INHIBITTHRESHOLDVOLTAGE(V) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C)

Figure 2. Startup Circuit Inhibit Voltage Threshold vs. Junction Temperature

VAUX,AUXILIARYSUPPLYVOLTAGE(V) 11.0

6.0--50 --25 0 25 50 75 100 125 150

T_J, JUNCTION TEMPERATURE (C) Figure 3. Auxiliary Supply Voltage Thresholds

vs. Junction Temperature 10.5

10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5

V_AUX(on)

Istart,STARTUPCURRENT(mA) 12

2

150 125 100 75 50 25 0 --25 --50

Figure 4. Startup Current vs. Junction Temperature 11

10 9 8 7 6 5 4 3

V_AUX= V_inhibit+ 0.2 V

V_AUX= V_AUX(on)-- 0.2 V

V_in= 48 V

Istart,STARTUPCURRENT(mA) 4 10 9 8 7 6 5

2 4 6 8 10 12

V_AUX, SUPPLY VOLTAGE (V)

Figure 5. Startup Current vs. Supply Voltage V_in= 48 V T_J= 25C

Istart(off),STARTUPCIRCUITLEAKAGE CURRENT(mA)

100

10

200 175 150 125 100 75 50 25 0

V_in, INPUT VOLTAGE (V)

Figure 6. Startup Circuit Leakage Current vs. Input Voltage

90 80 70 60 50 40 30 20

V_AUX= 12 V

0

T_J= 25C T_J= --40C

T_J= 125C 0 3 2 1 0

V_AUX(off1)

V_AUX(off2)

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UNDERVOLTAGE OVERVOLTAGE IAUX,AUXILIARYSUPPLYCURRENT(m

A) 10

1

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 7. Auxiliary Supply Current

vs. Junction Temperature 9

8 7 6 5 4 3 2

V_UVOV= 2.3 V, C_out1= C_out2= 100 pF V_AUX= 12 V

0

V_UVOV= 2.3 V, V_EA= 0 V

V_UVOV= 0 V

IAUX3,POWERSUPPLYCURRENT(mA ) 8.0

3.5

15 14 13 12 11 10

V_AUX, POWER SUPPLY VOLTAGE (V) Figure 8. Supply Current vs. Supply Voltage 7.5

7.0 6.5 6.0 5.5 5.0 4.5 4.0

3.0

20 V_in= 48 V

T_J= 25C f_OSC≈230 kHz C_out1= C_out2= 100 pF

T_J, JUNCTION TEMPERATURE (C) VUV/OV,LINEUNDER/OVERVOLTAGETHRESHOLDS(V)

3.2

2.2

--50 3.1 3.0 2.9 2.8 2.7 2.5 2.4 2.3

2.0 2.6

2.1

--25 0 25 50 75 100 125 150

Figure 9. Line Under/Overvoltage Thresholds vs. Junction Temperature

VUV/OV(H),UNDER/OVERVOLTAGEHYSTERESIS(mV) 150

50

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 10. Line Under/Overvoltage Hysteresis

130 120 110 100 90 80 70 60

UNDERVOLTAGE OVERVOLTAGE

t(UVOV),UVOVOFFSETCURRENT(

mA) 75

25 70 65 60 55 50 45 40 35 30

V_AUX= 12 V V_UVOV= 2.8 V

IFF(D),DISCHARGECURRENT(mA) 50

0 45 40 35 30 25 20 15 10 5

V_CC= 12 V V_SS= 0 V V_FF= 0.5 V

16 17 18 19

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NCP1562B

NCP1562A

VFF(peak),FFPEAKVOLTAGE(V) 3.5

2.5

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 13. FF Offset and SS Reset Voltages

vs. Junction Temperature

3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6

VILIM,CURRENTLIMITTHRESHOLDVOLTAGE(mV) 550

150 125 100 75 50 25 0 --25 --50

Figure 14. Feedforward Peak Voltage vs. Junction Temperature

500 450 400 350 300 250 200 150 Voffset(FF)/Vreset(SS),FFOFFSETAND SSRESETVOLTAGES(mV)

250

0--50 --25 0 25 50 75 100 125 150

T_J, JUNCTION TEMPERATURE (C) 225

200 175 150 125 100 75 50 25

FF--Offset

SS Reset

Figure 15. Current Limit Threshold Voltage vs. Junction Temperature

tILIM,CURRENTLIMITPROPAGATIONDELAY(ns) 150

50

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 16. Current Limit Propagation Delay

130 120 110 100 90 80 70 60

tLEB,LEBTIME(ns) 100

0

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 17. Leading Edge Blanking Time 90

80 70 60 50 40 30 20 10

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,VREFDISCHARGECURRENT(mA) 10

Figure 18. Cycle Skip Charge Current vs. Junction Temperature

9 8 7 6 5 4 3

2 V_CC= 12 V

V = 0 V

VCSKIP(peak),UPPERTHRESHOLD(V) 3.5

2.5

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) 3.4

3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6

UPPER THRESHOLD

VCSKIP(valley),LOWERTHRESHOLD(V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 LOWER THRESHOLD

VREF,REFERENCEVOLTAGE(V) 5.25

4.75

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 19. Cycle Skip Discharge Current

5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80

V_AUX= 12 V

V_REF= 0 mA V_REF= 5 mA ICSKIP(C),CYCLESKIPCHARGECURRENT(mA)

150

50

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) 140

130 120 110 100 90 80 70 60

V_CSKIP= 1.25 V

Figure 20. Cycle Skip Voltage Thresholds vs. Junction Temperature

,OSCILLATORFREQUENCY(kHz

) 750

Figure 21. Reference Voltage vs. Junction Temperature

V_AUX= 12 V R_T= 14 kΩ R_D= 69.8 kΩ 650

550 500 450 400 350 300 600

C_T= 150 pF

C_T= 220 pF

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) V_CSKIP= 1.25 V

ICSKIP(D),CYCLESKIPDISCHARGECURRENT(mA) 15 14 13 12 11 10 9 8 7 6 5

700

(13)

t_D(trail) t_D(lead)

t_D(trail) t_D(lead) t_D(trail)

t_D(lead)

D,DUTYCYCLE(%)

90

30 10

R_T, TIMING RESISTOR (kΩ) 85

75 70 65 60 55 50 45 40 80

50 70 90 110

V_AUX= 12 V T_J= 25C R_D= 69.8 kΩ C_T= 150 pF

C_T= 220 pF C_T= 470 pF

D,DUTYCYCLE(%)

90

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) Figure 24. Oscillator Frequency

vs. Timing Resistor

V_AUX= 12 V R_D= 69.8 kΩ 85

75 70 65 60 55 50 45 40 80

R_T= 15.8 kΩ, C_T= 220 pF R_T= 11.8 kΩ, C_T= 470 pF

R_T= 20 kΩ, C_T= 150 pF

ISS(C),CHARGECURRENT(mA) 15

150 125 100 75 50 25 0 --25 --50

T_J, JUNCTION TEMPERATURE (C) V_AUX= 12 V 14

12 11 10 9 8 7 6 5 13

DISCHARGE (V_UVOV= 0 V) CHARGE

ISS(D),DISCHARGECURRENT(mA)

tD,OVERLAPTIMEDELAY(ns) 500

80 0

R_D, DELAY RESISTOR (kΩ)

Figure 25. Duty Cycle vs. Timing Resistor

450

350 300 250 200 150 100 50 0 400

160 240 320 400

V_AUX= 12 V T_J= 25C LEADING

TRAILING

150 140 130 120 110 100 90 80 70 60 50

tD,OVERLAPTIMEDELAY(ns) 400 Figure 26. Duty Cycle

350

250 200 150 100 50 0 300

V_AUX= 12 V

150 125 100 75 50 25 0 --25 --50 fOSC,OSCILLATORFREQUENCY(kHz)

30 10

R_T, TIMING RESISTOR (kΩ) 800

700 600 500 400 300 200 100 900

50 70 90 110

V_AUX= 12 V T_J= 25C C_T= 150 pF

C_T= 220 pF

C_T= 470 pF

Figure 27. Soft--Start/Stop Charge and Discharge Currents vs. Junction Temperature

Figure 28. Overlap Time Delay vs. Delay Resistor

Figure 29. Overlap Time Delay vs. Junction Temperature

R_D= 200 kΩ

R_D= 20 kΩ R_D= 69.8 kΩ 0