High Speed Quad-ChannelDigital IsolatorNCID9401, NCID9411,NCID9400, NCID9410

High Speed Quad-Channel Digital Isolator

NCID9401, NCID9411, NCID9400, NCID9410

Description

The NCID9401, NCID9411, NCID9400 and NCID9410 are galvanically isolated high−speed quad−channel digital isolator with output enable. This device supports isolated communications thereby allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages.

It utilizes onsemi’s patented galvanic off−chip capacitor isolation technology and optimized IC design to achieve high insulation and high noise immunity, characterized by high common mode rejection and power supply rejection specifications. The thick ceramic substrate yields capacitors with ~25 times the thickness of thin film on−chip capacitors and coreless transformers. The result is a combination of the electrical performance benefits that digital isolators offer with the safety reliability of a >0.5 mm insulator barrier similar to what has historically been offered by optocouplers.

The device is housed in a 16−pin wide body small outline package.

Features

• Off−Chip Capacitive Isolation to Achieve Reliable High Voltage Insulation

♦

DTI (Distance Through Insulation): ≥ 0.5 mm

♦

Maximum Working Insulation Voltage: 2000 V

• Bi−directional Communication

• ^{100 kV/} m s Minimum Common Mode Rejection

• 8 mm Creepage and Clearance Distance to Achieve Reliable High Voltage Insulation

• Specifications Guaranteed Over 2.5 V to 5.5 V Supply Voltage and −40 ° C to 125 ° C Extended Temperature Range

• Over Temperature Detection

• Output Enable Function (Primary and Secondary side)

• NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable (Pending)

• Safety and Regulatory Approvals

♦

UL1577, 5000 VRMS for 1 Minute

♦

DIN EN/IEC 60747−17 (Pending)

• Isolated PWM Control

• Industrial Fieldbus Communications

• Microprocessor System Interface (SPI, I

C, etc.)

• Programmable Logic Control

SOIC16 W CASE 751EN

MARKING DIAGRAM

A = Assembly Location WL = Wafer Lot / Assembly Lot Y = Year

WW = Work Week xx = 00, 01, 10, 11

See detailed ordering and shipping information on page 13 of this data sheet.

ORDERING INFORMATION AWLYWW 94xx

ON

BLOCK DIAGRAM

Figure 1. Functional Block Diagram

ENCODER

DECODER SYNC

RX

RX

DES

SER DECODER

ENCODER SYNC

IO SWITCH VDD1

GND1 GND1

IO A

IOB

IOC

VDD2

GND2 GND2

IO A

IOB

IOC TX

TX DES

SER

IO SWITCH

IOD

EN1/NC

IOD

EN2/NC

PIN CONFIGURATION

Figure 2. Pin and Channel Configuration

1 16 VDD2

V_DD1

GND2 GND1

VOA VINA

VOB VINB

VOC VINC

VOD VIND

EN2 NC

GND2 GND1

ISOLATION

2 15

3 14

4 13

5 12

6 11

7 10

8 9

NCID9401 NCID9411

1 16 VDD2

V_DD1

GND2 GND1

VOA VINA

VOB VINB

VOC VINC

VIND VOD

EN2 EN1

GND2 GND1

ISOLATION

2 15

3 14

4 13

5 12

6 11

7 10

8 9

1 16 VDD2

V_DD1

GND2 GND1

VOA VINA

VOB VINB

VOC VINC

VOD VIND

NC NC

GND2 GND1

ISOLATION

2 15

3 14

4 13

5 12

6 11

7 10

8 9

NCID9400 NCID9410

1 16 VDD2

V_DD1

GND2 GND1

VOA VINA

VOB VINB

VOC VINC

VIND VOD

NC NC

GND2 GND1

ISOLATION

2 15

3 14

4 13

5 12

6 11

7 10

8 9

PIN DEFINITION Name

Pin No.

NCID9401

Pin No.

NCID9411

Pin No.

NCID9400

Pin No.

NCID9410 Description

V_DD1 1 1 1 1 Power Supply, Side 1

GND1 2 2 2 2 Ground Connection for VDD1

V_INA 3 3 3 3 Input, Channel A

V_INB 4 4 4 4 Input, Channel B

VINC 5 5 5 5 Input, Channel C

V_IND 6 11 6 11 Input, Channel D

EN1 − 7 − − Output Enable 1

NC 7 − 7 7 No Connect

GND1 8 8 8 8 Ground Connection for V_DD1

GND2 9 9 9 9 Ground Connection for V_DD2

NC − − 10 10 No Connect

EN2 10 10 − − Output Enable 2

V_OD 11 6 11 6 Output, Channel D

V_OC 12 12 12 12 Output, Channel C

V_OB 13 13 13 13 Output, Channel B

VOA 14 14 14 14 Output, Channel A

GND2 15 15 15 15 Ground Connection for VDD2

VDD2 16 16 16 16 Power Supply, Side 2

SPECIFICATIONS

TRUTH TABLE (Note 1)

V_INX EN_X V_DDI V_DDO V_OX Comment

H H/NC Power Up Power Up H Normal Operation

L H/NC Power Up Power Up L Normal Operation

X L Power Up Power Up Hi−Z

X H/NC Power Down Power Up L Default low; V_OX return to normal operation

when V_DDI change to Power Up

X H/NC Power Up Power Down Undetermined

(Note 2) VOX return to normal operation when VDDO

change to Power Up

1. VINX = Input signal of a given channel (A, B, C or D). EN_X = Enable pin for primary or secondary side (1 or 2). V_OX = Output signal of a given channel (A, B, C or D). V_DDI = Input−side V_DD. V_DDO = Output−side V_DD. X = Irrelevant. H = High level. L = Low level. NC = No Connection.

2. The outputs are in undetermined state when V_DDO < V_UVLO.

SAFETY AND INSULATION RATINGS

As per DIN EN/IEC 60747−17, this digital isolator is suitable for “safe electrical insulation” only within the safety limit data. Compliance with the safety ratings must be ensured by means of protective circuits.

Symbol Parameter Min Typ Max Unit

Installation Classifications per DIN VDE 0110/1.89

Table 1 Rated Mains Voltage < 150 VRMS − I–IV −

< 300 VRMS − I–IV −

< 450 VRMS − I–IV −

< 600 VRMS − I–IV −

< 1000 V_RMS − I–III −

Climatic Classification − 40/125/21 −

Pollution Degree (DIN VDE 0110/1.89) − 2 −

CTI Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1) 600 − −

VPR Input−to−Output Test Voltage, Method b, V_IORM × 1.875 = VPR, 100%

Production Test with t_m = 1 s, Partial Discharge < 5 pC 3750 − − V_peak Input−to−Output Test Voltage, Method a, V_IORM × 1.6 = VPR, Type

and Sample Test with tm = 10 s, Partial Discharge < 5 pC 3200 − − V_peak

V_IORM Maximum Working Insulation Voltage 2000 − − V_peak

VIOTM Highest Allowable Over Voltage 8000 − − Vpeak

E_CR External Creepage 8.0 − − mm

E_CL External Clearance 8.0 − − mm

DTI Insulation Thickness 0.50 − − mm

T_Case Safety Limit Values – Maximum Values in Failure; Case Temperature 150 − − °C

P_S,INPUT Safety Limit Values – Maximum Values in Failure; Input Power 100 − − mW

P_S,OUTPUT Safety Limit Values – Maximum Values in Failure; Output Power 600 − − mW

R_IO Insulation Resistance at TS, V_IO = 500 V 10⁹ − − W

ABSOLUTE MAXIMUM RATINGS (T_A = 25°C unless otherwise specified)

Symbol Parameter Value Unit

TSTG Storage Temperature −55 to +150 °C

T_OPR Operating Temperature −40 to +125 °C

T_J Junction Temperature −40 to +150 °C

T_SOL Lead Solder Temperature (Refer to Reflow Temperature Profile) 260 for 10 s °C

V_DD Supply Voltage (V_DDx) −0.5 to 6 V

V Voltage (V_INx, V_Ox, ENx) −0.5 to 6 V

I_O Average Output Current 10 mA

PD Power Dissipation 210 mW

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

RECOMMENDED OPERATING RANGES

Symbol Parameter Min Max Unit

T_A Ambient Operating Temperature −40 +125 °C

V_DD1 V_DD2 Supply Voltage (Notes 3, 4) 2.5 5.5 V

V_INH High Level Input Voltage 0.7 × VDDI V_DDI V

V_INL Low Level Input Voltage 0 0.1 × VDDI V

V_UVLO+ Supply Voltage UVLO Rising Threshold 2.2 − V

V_UVLO− Supply Voltage UVLO Falling Threshold 2.0 − V

UVLO_HYS Supply Voltage UVLO Hysteresis 0.1 − V

I_OH High Level Output Current −2 − mA

I_OL Low Level Output Current − 2 mA

DR Signaling Rate 0 10 Mbps

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

3. During power up or down, ensure that both the input and output supply voltages reach the proper recommended operating voltages to avoid any momentary instability at the output state.

4. For reliable operation at recommended operating conditions, V_DD supply pins require at least a pair of external bypass capacitors, placed within 2 mm from V_DD pins 1 and 16 and GND pins 2 and 15. Recommended values are 0.1mF and 1mF.

ISOLATION CHARACTERISTICS

Apply over all recommended conditions. All typical values are measured at T_A = 25°C.

Symbol Parameter Conditions Min Typ Max Unit

V_ISO Input−Output Isolation

Voltage T_A = 25°C, Relative Humidity < 50%, t = 1.0 minute, I_I−O v 10 mA, 50 Hz (Notes 5, 6, 7)

5000 − − V_RMS

R_ISO Isolation Resistance V_I−O = 500 V (Note 5) − 10¹¹ −

C_ISO Isolation Capacitance V_I−O = 0 V, Frequency = 1.0 MHz

(Note 5) − 1 − pF

5. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.

6. 5,000 VRMS for 1−minute duration is equivalent to 6,000 VRMS for 1−second duration.

7. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN EN/IEC 60747−17 Safety and Insulation Ratings Table on page 4.

ELECTRICAL CHARACTERISTICS

Apply over all recommended conditions, T_A =−40°C to +125°C, VDD1 = V_DD2 = 2.5 V to 5.5 V, unless otherwise specified. All typical values are measured at T_A = 25°C.

Symbol Parameter Conditions Min Typ Max Unit Figure

V_OH High Level Output

Voltage V_DD = 5 V, I_OH = −4 mA 4.4 4.8 − V 11

V_DD = 3.3 V, I_OH = −2 mA 2.9 3.2 V_DD = 2.5 V, I_OH = −1 mA 2.1 2.4 V_OL Low Level Output

Voltage V_DD = 5 V, I_OL = 4 mA − 0.1 0.4 V 12

V_DD = 3.3 V, I_OL = 2 mA V_DD = 2.5 V, I_OL = 1 mA V_INT+ Rising Input Voltage

Threshold − − 0.7 × VDDI V

VINT− Falling Input Voltage

Threshold 0.1 × VDDI − − V

V_INT(HYS) Input Threshold Voltage

Hysteresis 0.1 × VDDI 0.2 × VDDI − V

I_INH High Level Input Current V_IH = V_DDI − − 1 mA

IINL Low Level Input Current VIL = 0 V −1 − − mA

CMTI Common Mode Transient

Immunity VI = VDDI or 0 V,

VCM = 1500 V 100 150 − kV/ms 16

C_IN Input Capacitance V_IN = V_DDI/2 + 0.4 × sin (2pft),

f = 1 MHz, V_DD= 5 V − 2 − pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

SUPPLY CURRENT CHARACTERISTICS

Apply over all recommended conditions, TA =−40°C to +125°C unless otherwise specified. All typical values are measured at TA = 25°C.

Symbol Parameter Conditions Min Typ Max Unit Figure

I_DD1 DC Supply Current V_DD = 5 V, EN = 0/5 V,

V_IN = 0/5 V − 8.3 11.3 mA

I_DD2 9.3 12.3

I_DD1 V_DD = 3.3 V, EN = 0/3.3 V,

V_IN = 0/3.3 V 8.0 11

I_DD2 9.1 12

I_DD1 V_DD = 2.5 V, EN = 0/2.5 V,

V_IN = 0/2.5 V 7.9 10.8

I_DD2 9.0 11.8

I_DD1 AC Supply Current

1 Mbps V_DD = 5 V, EN = 5 V,

C_L = 15 pF,

VIN = 5 V Square Wave

− 8.4 11.3 mA 3, 4,

IDD2 9.5 12.3 5, 6

I_DD1 V_DD = 3.3 V, EN = 3.3 V,

C_L = 15 pF,

VIN = 3.3 V Square Wave

8.1 11

IDD2 9.2 12

I_DD1 V_DD = 2.5 V, EN = 2.5 V,

C_L = 15 pF,

VIN = 2.5 V Square Wave

8.0 10.8

IDD2 9.1 11.8

I_DD1 AC Supply Current

10 Mbps V_DD = 5 V, EN = 5 V,

C_L = 15 pF,

VIN = 5 V Square Wave

− 8.9 12.6 mA

IDD2 11.3 13.6

I_DD1 V_DD = 3.3 V, EN = 3.3 V,

C_L = 15 pF,

VIN = 3.3 V Square Wave

8.4 11.7

IDD2 10.2 12.7

I_DD1 V_DD = 2.5 V, EN = 2.5 V,

C_L = 15 pF,

V_IN = 2.5 V Square Wave

8.2 11.3

I_DD2 9.8 12.3

SWITCHING CHARACTERISTICS – NCID9401/NCID9400

Apply over all recommended conditions, T_A =−40°C to +125°C unless otherwise specified. All typical values are measured at TA = 25°C.

Symbol Parameter Ch Conditions Min Typ Max Unit Figure

t_PHL Propagation Delay to Logic Low

Output (Note 8) All VDD = 5 V, CL = 15 pF − 136 200 ns 8, 13

VDD = 3.3 V, CL = 15 pF VDD = 2.5 V, CL = 15 pF tPLH Propagation Delay to Logic High

Output (Note 9) All VDD = 5 V, CL = 15 pF − 137 200 ns

VDD = 3.3 V, CL = 15 pF VDD = 2.5 V, CL = 15 pF PWD Pulse Width Distortion

| t_PHL – t_PLH | (Note 10) All V_DD = 5 V, C_L = 15 pF − 33 80 ns V_DD = 3.3 V, C_L = 15 pF

V_DD = 2.5 V, C_L = 15 pF tPSK(PP) Propagation Delay Skew

(Part to Part) (Note 11) All V_DD = 5 V, C_L = 15 pF −80 − 80 ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF

t_R Output Rise Time (10% to 90%) All V_DD = 5 V, C_L = 15 pF − 3 − ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF

t_F Output Fall Time (90% to 10%) All V_DD = 5 V, C_L = 15 pF − 2 − ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF t_PZL High Impedance to Logic Low

Output Delay (Notes 12, 16) All VDD = 5 V, RL = 1 kW − 8.4 25 ns 14

V_DD = 3.3 V, R_L = 1 kW 9.9 VDD = 2.5 V, RL = 1 kW 12.3 t_PLZ Logic Low to High Impedance

Output Delay (Notes 13, 16) All VDD = 5 V, RL = 1 kW − 10.8 25 ns VDD = 3.3 V, RL = 1 kW 14.5

VDD = 2.5 V, RL = 1 kW 17.8 t_PZH High Impedance to Logic High

Output Delay (Notes 14, 16) All VDD = 5 V, RL = 1 kW − 0.53 1 ms 15

VDD = 3.3 V, RL = 1 kW 0.50 V_DD = 2.5 V, R_L = 1 kW 0.50 t_PHZ Logic High to High Impedance

Output Delay (Notes 15, 16) All V_DD = 5 V, R_L = 1 kW − 11.7 25 ns V_DD = 3.3 V, R_L = 1 kW 13.1

V_DD = 2.5 V, R_L = 1 kW 15.0

8. Propagation delay t_PHL is measured from the 50% level of the falling edge of the input pulse to the 50% level of the falling edge of the V_O signal.

9. Propagation delay t_PLH is measured from the 50% level of the rising edge of the input pulse to the 50% level of the rising edge of the V_O signal.

10.PWD is defined as | t_PHL – t_PLH | for any given device.

11. Part−to−part propagation delay skew is the difference between the measured propagation delay times of a specified channel of any two parts at identical operating conditions and equal load.

12.Enable delay t_PZL is measured from the 50% level of the rising edge of the EN pulse to the 50% of the falling edge of the V_O signal as it switches from high impedance state to low state.

13.Disable delay tPLZ is measured from the 50% level of the falling edge of the EN pulse to 0.5 V level of the rising edge of the VO signal as it switches from low state to high impedance state.

14.Enable delay tPZH is measured from the 50% level of the rising edge of the EN pulse to the 50% of the rising edge of the VO signal as it switches from high impedance state to high state.

15.Disable delay tPHZ is measured from the 50% level of the falling edge of the EN pulse to VOH − 0.5 V level of the falling edge of the VO signal as it switches from high state to high impedance state.

SWITCHING CHARACTERISTICS – NCID9411/NCID9410

Apply over all recommended conditions, T_A =−40°C to +125°C unless otherwise specified. All typical values are measured at TA = 25°C.

Symbol Parameter Ch Conditions Min Typ Max Unit Figure

t_PHL Propagation Delay to Logic

Low Output (Note 8) A, B, C V_DD = 5 V, CL = 15 pF − 115 170 ns 9, 10, 13 VDD = 3.3 V, CL = 15 pF

VDD = 2.5 V, CL = 15 pF

D VDD = 5 V, CL = 15 pF − 77 110 ns

VDD = 3.3 V, CL = 15 pF VDD = 2.5 V, CL = 15 pF tPLH Propagation Delay to Logic

High Output (Note 9) A,B,C V_DD = 5 V, C_L = 15 pF − 117 170 ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF

D V_DD = 5 V, C_L = 15 pF − 78 110 ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF PWD Pulse Width Distortion

| t_PHL – t_PLH | (Note 10) A,B,C V_DD = 5 V, C_L = 15 pF −70 26 70 ns V_DD = 3.3 V, C_L = 15 pF

V_DD = 2.5 V, C_L = 15 pF

D V_DD = 5 V, C_L = 15 pF −40 13 40 ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF t_PSK(PP) Propagation Delay Skew

(Part to Part) (Note 11) All V_DD = 5 V, C_L = 15 pF −70 − 70 ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF t_R Output Rise Time

(10% to 90%) All V_DD = 5 V, C_L = 15 pF − 3 − ns

V_DD = 3.3 V, C_L = 15 pF V_DD = 2.5 V, C_L = 15 pF t_F Output Fall Time

(90% to 10%) All VDD = 5 V, CL = 15 pF − 2 − ns

VDD = 3.3 V, CL = 15 pF VDD = 2.5 V, CL = 15 pF t_PZL High Impedance to Logic

Low Output Delay (Notes 12, 16)

All V_DD = 5 V, R_L = 1 kW − 8.5 25 ns 14

V_DD = 3.3 V, R_L = 1 kW 10.2 V_DD = 2.5 V, R_L = 1 kW 12.6 tPLZ Logic Low to High Impedance

Output Delay (Notes 13, 16) All V_DD = 5 V, R_L = 1 kW − 10.8 25 ns V_DD = 3.3 V, R_L = 1 kW 14.6

V_DD = 2.5 V, R_L = 1 kW 17.8 tPZH High Impedance to Logic High

Output Delay (Notes 14, 16) All V_DD = 5 V, R_L = 1 kW − 0.54 1 ms 15

V_DD = 3.3 V, R_L = 1 kW 0.50 V_DD = 2.5 V, R_L = 1 kW 0.50 t_PHZ Logic High to High Impedance

Output Delay (Notes 15, 16) All V_DD = 5 V, R_L = 1 kW − 11.6 25 ns V_DD = 3.3 V, R_L = 1 kW 12.9

V_DD = 2.5 V, R_L = 1 kW 14.6

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 3. NCID9401/NCID9400 Supply Current vs.

Data Rate (No Load)

Figure 4. NCID9401/NCID9400 Supply Current vs.

Data Rate (Load = 15 pF)

Figure 5. NCID9411/NCID9410 Supply Current vs.

Data Rate (No Load)

Figure 6. NCID9411/NCID9410 Supply Current vs.

Data Rate (Load = 15 pF)

Figure 7. Supply Voltage UVLO Threshold vs. Figure 8. NCID9401/NCID9400 Propagation Delay vs.

0 2 4 6 8 10

7 8 9 10 11 12

Data Rate (Mbps) IDD1, IDD2− Supply Current (mA)

TA = 25°C LOAD = No Load

I_DD2 V_DD = 5 V

I_DD2 V_DD = 3.3 V

IDD2 VDD = 2.5 V IDD1 VDD = 2.5 V IDD1 VDD = 3.3 V

IDD1 VDD = 5 V

0 2 4 6 8 10

7 8 9 10 11 12

Data Rate (Mbps) IDD1, IDD2− Supply Current (mA)

TA = 25°C LOAD = 15 pF

I_DD2 V_DD = 5 V

I_DD2 V_DD = 3.3 V

IDD2 VDD = 2.5 V

IDD1 VDD = 2.5 V IDD1 VDD = 3.3 V

IDD1 VDD = 5 V

0 2 4 6 8 10

7 8 9 10 11 12

Data Rate (Mbps) IDD1, IDD2− Supply Current (mA)

TA = 25°C LOAD = No Load

IDD2 VDD = 5 V I_DD2 V_DD = 3.3 V

IDD2 VDD = 2.5 V

IDD1 VDD = 2.5 V IDD1 VDD = 3.3 V

IDD1 VDD = 5 V

0 2 4 6 8 10

7 8 9 10 11 12

Data Rate (Mbps) IDD1, IDD2− Supply Current (mA)

T_A = 25°C LOAD = 15 pF

IDD2 VDD = 5 V IDD2 VDD = 3.3 V

IDD2 VDD = 2.5 V

I_DD1 V_DD = 2.5 V I_DD1 V_DD = 3.3 V

I_DD1 V_DD = 5 V

−40 −20 0 80 100 120

1.5 2.0 2.5 3.0

T_A − Ambient Temperature (5C) VUVLO− Supply Voltage Threshold (V)

20 40 60

VUVLO+

VUVLO−

−40 −20 0 80 100 120

120 130 140 150

T_A − Ambient Temperature (5C) tP− Propagation Delay (ns)

20 40 60

t_PHL t_PLH VDD = 2.5 V to 5 V Ch A/B/C/D

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 9. NCID9411/NCID9410 Channel A/B/C Propagation Delay vs. Ambient Temperature

Figure 10. NCID9411/NCID9410 Channel D Propagation Delay vs. Ambient Temperature

Figure 11. High Level Output Voltage vs. Current Figure 12. Low Level Output Voltage vs. Current

−40 −20 0 80 100 120

100 110 120 130

T_A − Ambient Temperature (5C) tP− Propagation Delay (ns)

20 40 60

t_PHL t_PLH VDD = 2.5 V to 5 V Ch A/B/C

105 115 125

VDD = 2.5 V to 5 V Ch D

−40 −20 0 80 100 120

60 70 80 90

T_A − Ambient Temperature (5C) tP− Propagation Delay (ns)

20 40 60

t_PHL tPLH

65 75 85

−10 −8 −6 0

0 2 4 6

I_OH − High Level Output Current (mA) VOH− High Level Output Voltage (V)

−4 −2

1 3

5 TA = 25°C

V_DD = 5 V

VDD = 3.3 V VDD = 2.5 V

0 2 4 10

0.0 0.4 0.8 1.0

I_OL − Low Level Output Current (mA) VOL− Low Level Output Voltage (V)

6 8

0.2 0.6

TA = 25°C

V_DD = 5 V

V_DD = 3.3 V VDD = 2.5 V

TEST CIRCUITS

ISOLATION

+

− +

−

+

−

Figure 13. V_IN to V_O Propagation Delay Test Circuit and Waveform

Figure 14. EN to Logic Low V_O Propagation Delay Test Circuit and Waveform

Figure 15. EN to Logic High V_O Propagation Delay Test Circuit and Waveform

Figure 16. Common Mode Transient Immunity Test Circuit

ISOLATION

0 S

1 2

V_DDI V_DDO

SCOPE

V_IN V_O

V_CM

S at 0, VO remain consistently low S at 1, VO remain consistently high S at 2, VO data same as V_IN data

ISOLATION

+

− +

−

+

−

1 kW 50% 0.5 V

V_DDI

V_IN

V_EN VI

V_O

CL R_L

V_DDO V_I

VO

t_PZH t_PHZ

50%

ISOLATION

+

− +

−

+

−

1 kW _50%

50% 0.5 V

V_DDI

V_IN

VEN

V_I

V_O

C_L R_L

V_DDO V_I

VO

t_PZL t_PLZ

50%

V_DDI

V_IN VEN

VI V_O

CL

V_DDO VI

V_O

tPLH t_PHL

tR tF

50% 10%

90%

APPLICATION INFORMATION

NCID9401, NCID9411, NCID9400 and NCID9410 are quad−channel digital isolators. The chip to chip galvanic isolation are provided by a pair of off−chip capacitors.

Digital circuits are used for processing signals through the 0.5 mm thick isolation barrier.

Pins are trimmed internally as input or output at IO Switch. Each direction of communication between two isolated circuits are achieved by implementing a pair of Serializer/Deserializer and Manchester Encoder/Decoder functional blocks as shown in Figure 17. The Serializer circuit converts the parallel data from the IO Switch into a serial (one bit) stream and the Manchester Encoder converts this data stream into coded data making it more robust, efficient and accurate for transmission. After encoding, all inputs signals are coded as V

T

and transmitted across the isolation barrier via Transceiver.

The off−chip ceramic capacitors that serve both as the isolation barrier and as the medium of transmission for signal switching using On−Off keying (OOK) technique are illustrated in the transceiver block diagram in Figure 18

and Figure 19. At the transmitter side, the V

T

input logic state is modulated with a high frequency carrier signal. The resulting signal is amplified and transmitted to the isolation barrier. The receiver side detects the barrier signal and demodulates it using an envelope detection technique and output V

R

.

The output signal of the transceiver V

R

will go to the Manchester Decoder. This decoder is used along with the receiver to recover the original data from the coded form and the Deserializer converts the serial stream back to the original, parallel data and redistributed back to the corresponding output pins. Both the Serializer/Deserializer and Manchester Encoder/Decoder are functional blocks on the transmitting and receiving chips.

For devices with EN, the output enable pin EN controls the impedance of the V

. When EN is at LOW, output V

is set to high impedance state. The V

will only follow the V

when EN is set to HIGH. V

is at default state LOW when the power supply at the transmitter side is turned off or the input V

is disconnected.

V_OR_X Serializer

VINA

Figure 17. Operational Block Diagram of Multi−Channels for Forward Direction

VINB

VINn

IO

Switch Manchester

Encoder

Transceiver

V_IT_X Manchester

Decoder Deserializer IO Switch

EN VOA V_OB

VOn

Figure 18. Block Diagram of Transceiver

OSC

ModulatorOOK RX

Amplifier ISOLATION

BARRIER

Envelope Detector VORX

TRANSMITTER RECEIVER

AmplifierTX VITX

OFF−CHIP CAPACITORS

Figure 19. On−Off Keying Modulation Signals

VITX

VORX ISOLATION BARRIER SIGNAL

Layout Recommendation

Layout of the digital circuits relies on good suppression of unwanted noise and electromagnetic interference. It is recommended to use 4−layer FR4 PCB, with ground plane below the components, power plane below the ground plane, signal lines and power fill on top, and signal lines and ground fill at the bottom as shown in Figure 20. The alternating polarities of the layers creates interplane capacitances that aids the bypass capacitors required for reliable operation at digital switching rates.

In the layout with digital isolators, it is required that the isolated circuits have separate ground and power planes. The section below the device should be clear with no power, ground or signal traces. Maintain a gap equal to or greater than the specified minimum creepage clearance of the device package.

It is highly advised to connect at least a pair of low ESR supply bypass capacitors, placed within 2 mm from the

power supply pins 1 and 16 and ground pins 2 and 15 as shown in Figure 21. Recommended values are 1 mF and 0.1 mF, respectively. Place them between the V

pins of the device and the via to the power planes, with the higher frequency, lower value capacitor closer to the device pins.

Directly connect the device ground pins 2, 8, 9 and 15 by via to their corresponding ground planes.

Over Temperature Detection

NCID9401, NCID9411, NCID9400 and NCID9410 have

built−in Over Temperature Detection (OTD) feature that

protects the IC from thermal damage. The output pins will

automatically switch to default state when the ambient

temperature exceeds the maximum junction temperature at

threshold of approximately 160°C. The device will return to

normal operation when the temperature decreases

approximately 20 ° C below the OTD threshold.

Figure 20. 4−Layer PCB for Digital Isolator

VDD1 Plane Signal Lines / VDD1 Fill

Signal Lines / GND1 Fill

GND2 Plane VDD2 Plane Signal Lines / VDD2 Fill

Signal Lines / GND2 Fill No Trace

GND1 Plane

Figure 21. Placement of Bypass Capacitors V_DD2 V_DD1

GND2 GND1

GND2 GND1

1 mF 0.1 mF 0.1 mF 1 mF

ORDERING INFORMATION

Part Number Grade Package Shipping^†

NCID9401 Industrial SOIC16 W 50 Units / Tube

NCID9401R2 Industrial SOIC16 W 750 Units / Tape & Reel

NCIV9401* Automotive SOIC16 W 50 Units / Tube

NCIV9401R2* Automotive SOIC16 W 750 Units / Tape & Reel

NCID9411 Industrial SOIC16 W 50 Units / Tube

NCID9411R2 Industrial SOIC16 W 750 Units / Tape & Reel

NCIV9411* Automotive SOIC16 W 50 Units / Tube

NCIV9411R2* Automotive SOIC16 W 750 Units / Tape & Reel

NCID9400 Industrial SOIC16 W 50 Units / Tube

NCID9400R2 Industrial SOIC16 W 750 Units / Tape & Reel

NCIV9400* Automotive SOIC16 W 50 Units / Tube

NCIV9400R2* Automotive SOIC16 W 750 Units / Tape & Reel

NCID9410 Industrial SOIC16 W 50 Units / Tube

NCID9410R2 Industrial SOIC16 W 750 Units / Tape & Reel

NCIV9410* Automotive SOIC16 W 50 Units / Tube

NCIV9410R2* Automotive SOIC16 W 750 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*NCIV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.

SOIC16 W CASE 751EN

ISSUE A

DATE 24 AUG 2021

XXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

GENERIC MARKING DIAGRAM*

AWLYWW XXXXXXXXXX XXXXXXXXXX

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

98AON13751G DOCUMENT NUMBER:

DESCRIPTION:

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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 SOIC16 W

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