NCN V/3 V SIMカード電源およびレベル・シフタ

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(1)NCN4555 1.8 V/3 V SIMカード電源およびレベル・シフタ NCN4555SIM部

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(4) ()路*+蔵LDO,DC−DC -%. NCN45551.8 V/03.0 V1SIM1 234 5*617- 8ISO7816−38 "" % $98規:GSM 11.11/0関連規:(11.12/011.18) 3G;- !要<(IMT−2000/3G UICC規:)=>?@A* STOPB34?@C電D#EFGH";起I ?@-FJKLMNO6P5*1電Q 電(SIM_VCC)1R1B(MOD_VCC)34?@選S * 特長.       . 1.8 V3.0 VIT1SIMUV LDO1.8 V/03.0 V50 mA超W電DX給Y能 Z[\1I/OB]+蔵^!&F^_` SIMB17kV超WESDa護bcd;7!)規e? ISO−7816fg=>?h@1BijESDa護 kl5MHz超1

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(6) $m!3x3 QFN−16nFop 鉛$K"7- 8*. 代表的アプリケーション.  2G2.5G/03Gqr電話4SIM" %$98   . )路識s;pt! 8 ""KG u v8PC 1.6 V to 5.5 V. 2.7 V to 5.5 V. 0.1mF 0.1mF GND 3 1 P3 P2 P1 P0. 2 14 13 15. 5. VDD STOP MOD_VCC RST CLK. SIM_VCC. SIM_RST SIM_CLK. I/O. SIM_I/O GND. SIM Card Detect GND. MARKING DIAGRAM 1 QFN−16 MN SUFFIX CASE 488AK. 1. 16 NCN 4555 ALYWG G. A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location). ORDERING INFORMATION Device. Package. Shipping†. NCN4555MNG. QFN−16 (Pb−Free). 123 Units / Rail. NCN4555MNR2G. QFN−16 (Pb−Free). 3000/Tape & Reel. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.. NCN4555. MPU or Microcontroller. VBB. http://onsemi.com. 7. 9. 1 2 3 4. 11. VCC GND RST CLK I/O C4 C8 DET. 8. 5 6 7 8. DET. 1mF. 10. GND. Figure 1. Typical Interface Application *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D..  Semiconductor Components Industries, LLC, 2011. September, 2011 − Rev. 3. 1. Publication Order Number: NCN4555JP/D.

(7) NCN4555. STOP. 1. MOD_VCC. 2. VDD NC. NC. I/O. RST CLK. 16. 15. 14. Exposed Pad (EP). 13 12. NC. 11. SIM_CLK. 3. 10. GND. 4. 9. SIM_RST. NCN4555. 5. 6. 7. 8. VBAT NC SIM_VCC SIM_I/O. Figure 2. QFN−16 Pinout (Top View). VBAT (2.7 V to 5.5 V) 5. STOP 1. 7 SIM_VCC. 50 mA LDO 1.8 V/3.0 V. MOD_VCC 2. GND. VDD (1.6 V to 5.5 V) 3 RST 14. 9. SIM_RST. GND CLK 13. 11 SIM_CLK. GND 18 kW I/O 15. GND 14 kW. I/O DATA. DATA. 8 SIM_I/O. I/O GND GND. Figure 3. NCN4555 Block Diagram. http://onsemi.com 2. 10 GND.

(8) NCN4555 PIN DESCRIPTIONS PIN. Name. Type. 1. STOP. INPUT. Power Down Mode pin: STOP = Low ³ Low current shutdown mode activated STOP = High ³ Normal Operation A Low level on this pin resets the SIM interface, switching off the SIM_VCC.. Description. 2. MOD_VCC. INPUT. The signal present on this pin programs the SIM_VCC value: MOD_VCC = Low ³ SIM_VCC = 1.8 V MOD_VCC = High ³ SIM_VCC = 3 V. 3. VDD. POWER. 4. NC. 5. VBAT. 6. NC. 7. SIM_VCC. POWER. This pin is connected to the SIM card power supply pin. An internal LDO converter is programmable by the external MPU to supply either 1.8 V or 3.0 V output voltage. An external 1.0 mF minimum ceramic capacitor recommended must be connected across SIM_VCC and GND. During a normal operation, the SIM_VCC voltage can be set to 1.8 V followed by a 3.0 V value, or can start directly to any of these two values.. 8. SIM_I/O. INPUT/ OUTPUT. This pin handles the connection to the serial I/O of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the micro controller. A 14 kW (typical) pullup resistor provides a High impedance state for the SIM card I/O link.. 9. SIM_RST. OUTPUT. This pin is connected to the RESET pin of the card connector. A level translator adapts the external Reset (RST) signal to the SIM card.. 10. GND. GROUND. This pin is the GROUND reference for the integrated circuit and associated signals. Care must be taken to avoid voltage spikes when the device operates in a normal operation.. 11. SIM_CLK. OUTPUT. This pin is connected to the CLOCK pin of the card connector. The CLOCK (CLK) signal comes from the external clock generator, the internal level shifter being used to adapt the voltage defined for the SIM_VCC.. 12. NC. 13. CLK. INPUT. The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values defined by the specification (typically 50%). The built−in level shifter translates the input signal to the external SIM card CLK input.. 14. RST. INPUT. The RESET signal present at this pin is connected to the SIM card through the internal level shifter which translates the level according to the SIM_VCC programmed value.. 15. I/O. INPUT/ OUTPUT. 16. NC. This pin is connected to the system controller power supply. It configures the level shifter input stage to accept the signals coming from the microprocessor. A 0.1 mF capacitor shall be used to bypass the power supply voltage. When VDD is below 1.1 V typical the SIM_VCC is disabled. The NCN4555 comes into a shutdown mode. No Connect. POWER. DC−DC converter supply input. The input voltage ranges from 2.7V up to 5.5V. This pin has to be bypass by a 0.1 mF capacitor. No Connect. No Connect. This pin is connected to an external microcontroller or cellular phone management unit. A bidirectional level translator adapts the serial I/O signal between the smart card and the external controller. A built−in constant 18 kW (typical) resistor provides a high impedance state when not activated. No Connect. http://onsemi.com 3.

(9) NCN4555 ATTRIBUTES Characteristics. Values. ESD protection HBM, SIM card pins (7, 8, 9, 10 & 11) (Note 1) HBM, All other pins (Note 1) MM, SIM card pins (7, 8, 9, 10 & 11) (Note 2) MM, All other pins (Note 2) CDM, SIM card pins (7, 8, 9, 10 & 11) (Note 3) CDM , All other pins (Note 3). > 7 kV > 2 kV > 600 V > 200 V > 2 kV > 600 V. Moisture sensitivity (Note 4) QFN−16. Level 1. Flammability Rating Oxygen Index: 28 to 34. UL 94 V−0 @ 0.125 in. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. 2. 3. 4.. Human Body Model, R = 1500 W, C = 100 pF. Machine Model. CDM, Charged Device Model. For additional information, see Application Note AND8003/D.. MAXIMUM RATINGS (Note 5) Rating LDO Power Supply Voltage Power Supply from Microcontroller Side. Symbol. Value. Unit. VBAT. −0.5  VBAT  6. V. VDD. −0.5  VDD  6. V. SIM_VCC. −0.5  SIM_VCC  6. V. Vin. −0.5  Vin VDD + 0.5 but < 6.0 5. V mA. −0.5  Vout  VDD + 0.5 but < 6.0 10. V mA. Iout. −0.5  Vout  SIM_VCC + 0.5 but < 6.0 15 (internally limited). V mA. QFN−16 Low Profile package Power Dissipation @ TA = + 85C Thermal Resistance Junction−to−Air. PD RqJA. 440 90. mW C/W. Operating Ambient Temperature Range. TA. −40 to +85. C. Operating Junction Temperature Range. TJ. −40 to +125. C. TJmax. +125. C. Tstg. −65 to + 150. C. External Card Power Supply Digital Input Pins. Iin Digital Output Pins. Vout Iout. SIM card Output Pins. Vout. Maximum Junction Temperature Storage Temperature Range. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 5. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25C. http://onsemi.com 4.

(10) NCN4555 POWER SUPPLY SECTION (−40C to +85C) Pin. Symbol. 5. VBAT. Power Supply. 5. I VBAT. Operating current – ICC = 0 mA (Note 6). 5. I VBAT_SD. Shutdown current – STOP= Low (Note 7). 3. VDD. Operating Voltage. 3. IVDD. Operating Current – fCLK = 1 MHz (Note 8). 3. IVDD_SD. 3. VDD. 7. SIM_VCC. 7. ISIM_VCC_SC. Rating. Min. Typ. 2.7 22. 1.6 7.0. Shutdown Current – STOP = Low Undervoltage Lockout. 0.6. MOD_VCC = High, VBAT = 3.0 V, ISIM_VCC = 50 mA MOD_VCC = High, VBAT = 3.3 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA MOD_VCC = Low, VBAT = 2.7 V to 5.5 V, ISIM_VCC = 0 mA to 50 mA. 2.8 1.7. 2.8 3.0 1.8. Short –Circuit Current – SIM_VCC shorted to ground , TA=25C. Max. Unit. 5.5. V. 30. mA. 3.0. mA. 5.5. V. 12. mA. 1.0. mA. 1.5. V. 3.2 1.9. V V V. 175. mA. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. As long as VBAT – VDD v 2.5 V. For VBAT – VDD > 2.5 V the maximum value increases up to 35 mA (typical being in the +25 mA range). 7. As long as VBAT – VDD v 2.5 V. 8. Guaranteed by design over the operating temperature range specified.. DIGITAL INPUT/OUTPUT SECTION CLOCK, RESET, I/O, STOP, MOD_VCC Pin. Symbol. 1,2, 13, 14, 15. Vin IIH & IIL. Rating. Min. Input Voltage Range (STOP, MOD_VCC, RST, CLK, I/O) Input Current (STOP, MOD_VCC, RST, CLK). Typ. Max. Unit. 0. VDD. V. −100. 100. nA. 13, 14. VIH VIL. High Level Input Voltage (RST, CLK) Low Level Input Voltage (RST, CLK). 0.7 * VDD (Note 9). VDD 0.4. V V. 1, 2. VIH. High Level Input Voltage (STOP, MOD_VCC). VDD. V. VIL. Low Level Input Voltage (STOP, MOD_VCC). 0.7 * VDD (Note 9) 0. 0.4. V. 0.7 * VDD 0 −20. VDD 0.4 20 1.0. V V mA mA. 24. kW. 15. VOH_I/O VOL_I/O IIH IIL. High Level Output Voltage (SIM_I/O = SIM_VCC, IOH_I/O = −20 mA) Low Level Output Voltage (SIM_I/O = 0 V, IOH_I/O = 200 mA) High Level Input Current (I/O) Low Level Input Current (I/O). 15. Rpu_I/O. I/0 Pullup Resistor. 12. 18. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. If 1.6 V  VDD  1.8 V then VIHmin = 1.26 V.. http://onsemi.com 5.

(11) NCN4555 SIM INTERFACE SECTION (Note 10) Pin. Symbol. 9. SIM_RST. Rating. Min. SIM_VCC = +3.0 V (MOD_VCC = High) Output RESET VOH @ Isim_rst = −20 mA Output RESET VOL @ Isim_rst = +200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = Low) Output RESET VOH @ Isim_rst = −20 mA Output RESET VOL @ Isim_rst = +200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF. 11. SIM_CLK. SIM_VCC = +3.0 V (MOD_VCC = High) Output Duty Cycle Max Output Frequency Output VOH @ Isim_clk = −20 mA Output VOL @ Isim_clk = +200 mA Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = Low) Output Duty Cycle Max Output Frequency Output VOH @ Isim_clk = −20 mA Output VOL @ Isim_clk = +200 mA Output SIM_CLK Rise Time @ Cout = 30 pF Output SIM_CLK Fall Time @ Cout = 30 pF. 8. SIM_I/O. SIM_VCC = +3.0 V (MOD_VCC = High) Output VOH @ ISIM_IO = −20 mA, VI/O = VDD Output VOL @ ISIM_IO = +1 mA, VI/O = 0 V SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF SIM_VCC = +1.8 V (MOD_VCC = High) Output VOH @ ISIM_IO = −20 mA, VI/O =VDD Output VOL @ ISIM_IO = +1.0 mA, VI/O = 0 V SIM_I/O Rise Time @ Cout = 30 pF SIM_I/O Fall Time @ Cout = 30 pF. 8. Rpu_SIM_I/O. Card I/O Pullup Resistor. Typ. Max. Unit. 0.9 * SIM_VCC 0. SIM_VCC 0.4 1 1. V V ms ms. 0.9 * SIM_VCC 0. SIM_VCC 0.4 1 1. V V ms ms. 40 5 0.9 * SIM_VCC 0. 60. % MHz V V ns ns. SIM_VCC 0.4 18 18. 40 5 0.9 * SIM_VCC 0. 60 SIM_VCC 0.4 18 18. % MHz V V ns ns. 0.8 * SIM_VCC 0. SIM_VCC 0.4 1 1. V V ms ms. 0.8 * SIM_VCC 0. SIM_VCC 0.3 1 1. V V ms ms. 18. kW. 10. 14. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. All the dynamic specifications (AC specifications) are guaranteed by design over the operating temperature range.. http://onsemi.com 6.

(12) NCN4555 TYPICAL CHARACTERISTICS 100. 100 VBAT = 5.5 V. 80 70 VBAT = 2.7 V. 60 50 −50. −30. −10. 10. 30. VBAT = 5.5 V. 90 IVCC_SC_3.0 V (mA). IVCC_SC_1.8 V (mA). 90. 50. 70. 80 70 60 50 −50. 90. VBAT = 3.3 V. −30. Figure 4. Short Circuit Current IVCC_SC vs Temperature at SIM_VCC = 1.8 V (MOD_VCC = LOW). VBAT = 3.3 V. IVCC_SC_1.8 V (mA). IVCC_SC_3.0 V (mA). 30. 50. 70. 90. 30. VBAT = 5.5 V 20. 15. 10 −50. 10. Figure 5. Short Circuit Current IVCC_SC vs Temperature at SIM_VCC = 3.0 V (MOD_VCC = HIGH). 30. 25. −10. TEMPERATURE (C). TEMPERATURE (C). −30. −10 10 30 50 TEMPERATURE (C). 70. 25. VBAT = 5.5 V. 20. 15. 10 −50. 90. VBAT = 2.7 V. Figure 6. IBAT vs temperature at 3.0 V. −30. −10. 10 30 50 TEMPERATURE (C). 70. Figure 7. IVBAT vs Temperature at 1.8 V. http://onsemi.com 7. 90.

(13) NCN4555 アプリケーション情報 e?z足1ALDOITa証 SIM_VCC1.0mF1- n8" ¡F " 7U¢?@(£続*61 VBAT0.1 mF1 ¡F " 7U( - n8*. カード電源コンバータ. NCN4555 %$98DC−DC -% 1.8 V3.0 V50 mA超W電DX給5 C

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(18) 8 "間¤¥Y能¦1電§] ¨?*RESET/0CLOCK !"#$%© [\Z[ª«¬®¯W@A* °[\I/O MCUSIM間1電§ Z[\自I±適²[³´X?* ^!&F^_`µW@& Jm2¶^!&F^ )路（Figure 8Q1/0Q2）P·遊¸量1高速¹ 電´X?立º»P.¼間PijISO7816fg 1範+¶.*. SIM_VCC. VBAT Ilim. Q1. R1 − +. CIN = 0.1 mF. COUT = 1.0 mF +. R2. VREF. STOP. MOD_VCC. GND. Figure 8. Simplified Block Diagram of the LDO Voltage Regulator VDD. SIM_VCC. Q1. Q2. 18 k 200 ns. 14 k. 200 ns. I/O. SIM_I/O. GND Q3 IO/CONTROL. GND. LOGIC. Figure 9. Basic I/O Line Interface http://onsemi.com 8.

(19) NCN4555 ESD保護回路. Figure 10示x=±¶½¾& % 1IT示?@A*k¿1200 ns（x=）1間立º»P.¼間1À5·遊¸量関連^! &F^_`1Á関Â?*61Ã間ÄPMOS 7- 8電PVgs8F#Å!yz¶1 & Jm2¶.Æ*Figure 10示/. 1À5PVgsthÇ§È]É1u#Å FP& Jm2¶.C BG8´X ?@ 7U¹電?@立º»P.¼間長 ?* 1È]Éª«¬ÊËÌÍP適4 #8JÍ1k適P*. NCN4555 SIM %$98h@1SIMB (SIM_IOSIM_CLKSIM_RSTSIM_VCC GND)]?@7kV超WHBM ESD電a護¯ W@A*ßâ1h@1B(

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(24) 設e?@ NCN4555#EFGH";6P 5*à[VDDP1.1 Vbx=~.C¶ 7- 8自I±#EFGH";. *. OUTPUT. VDD. ON. OFF INPUT 0.2 x VDD or 0.4 V. Figure 10. SIM_IO Typical Rise and Fall Times with Stray Capacitance > 30 pF (33 pF Capacitor Connected on the Board). 0.7 x VDD. Figure 11. Typical Schmitt Trigger Characteristics. http://onsemi.com 9.

(25) J1. GND. J2. GND. J3. GND. 10. 1. 1. GND. http://onsemi.com STOP J9 GND. S2. S1 NC NC. NC. NC. NC. NC. NC 12 11 10 9 8 7 6 5 4 3 2 1 CONTROL & I/O. 1. 2. 10 k. 10 k R3. R2. 1. 1. 1. D4 2 V1 VBAT. MBRA140T3. J10 GND. VDD. 2. 1. J11 GND. D1. R1. VBAT. D3. V2 VDD. C1. J6. 1. VDD IP10. 100 nF. 1. 2. 1. STOP MOD IP4 IP5. VBAT. 2.2 k. VDD. NC 13 CLK SIM_CLK 14 RST SIM_RST 15 I/O SIM_I/O 16 NC GND GND_EXP 1 STOP 2 MOD_VCC 4 NC NC 5 VBAT SIM_VCC. 3. C2 10 mF. 1. 7. 6. GND. SIM_VCC. GND. 10. IP9. NC. R6 POI2. GND. CON2. 1. SIM_I/O IP8. SIM_CLK 11 9 SIM_RST 8 SIM_I/O. 12. 1. SIM_CLK SIM_RST IP6 IP7. J8. J5. 1. CLK RST I/O IP1 IP2 IP3. MBRA140T3. MOD_VCC. J4 STOP. I/O. RST. CLK. GND. 8 NC 7. 2.2 k. R5. SENSE_SIM_VCC. GND. MOD_VCC. GND. GND. Figure 12. NCN4555 engineering test board schematic diagram. GND. Q1 2N2222. I/O 6 NC VDD 5 GND. C8. SIM_CARD VDD. 4 C4 3 CLK 2 RST 1 VCC. NCN4555.

(26) NCN4555. Top Layer. Bottom Layer. Figure 13. NCN4555 Printed Circuit Board Layout (Engineering board). http://onsemi.com 11.

(27) MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS. QFN16 3*3*0.75 MM, 0.5 P CASE 488AK−01 ISSUE O. DATE 13 SEP 2004. 1 SCALE 2:1 D. PIN 1 LOCATION. ÇÇ ÇÇ. 0.15 C. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM SPACING BETWEEN LEAD TIP AND FLAG.. A B. E. DIM A A1 A3 b D D2 E E2 e K L. TOP VIEW. 0.15 C (A3). 0.10 C. A 16 X. SEATING PLANE. 0.08 C SIDE VIEW. A1. C. 16X. L. 16. 1. 5. 8. 4. 16X. e. EXPOSED PAD. XXXX XXXX ALYW. 9. E2. K. 16 16X. XXXX A L Y W. 12. 1 13. b. 0.10 C A B 0.05 C. GENERIC MARKING DIAGRAM*. ÇÇ ÇÇ ÇÇ. D2 NOTE 5. MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 −−− 0.30 0.50. BOTTOM VIEW. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present.. NOTE 3. DOCUMENT NUMBER: DESCRIPTION:. 98AON19612D. = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.. QFN16, 3*3*0.75 MM, 0.5 PITCH. PAGE 1 OF 1. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019. www.onsemi.com.

(28) onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: [email protected] onsemi Website: www.onsemi.com. ◊. TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910. Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative.

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