NCP1565 Highly Integrated Dual-Mode Active Clamp PWM Controller

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Highly Integrated

Dual-Mode Active Clamp PWM Controller

The NCP1565 is a highly integrated dual−mode active−clamp PWM controller targeting next−generation high−density, high−performance and small to medium power level isolated dc−dc converters for use in telecom and datacom industries. It can be configured in either voltage mode control with input voltage feed−forward or peak current mode control. Peak current mode control may be implemented with input voltage feed forward as well. Adjustable adaptive overlap time optimizes system efficiency based on input voltage and load conditions.

This controller integrates all the necessary control and protection functions to implement an isolated active clamp forward or asymmetric half−bridge converter. It integrates a high−voltage startup bias regulator. The NCP1565 has a line undervoltage detector, cycle−by−cycle current limiting, line voltage dependent maximum duty ratio limit, and programmable overtemperature protection using an external thermistor. It also includes a dual−function FLT/SD pin used for communicating the presence of a fault but also for shutting down the controller.

General Features

•

Support Voltage Mode Control and Peak Current Mode Control

•

Line Feedforward

•

Adaptive Overlap time Control for Improved Efficiency

•

Integrated 120 V High Voltage Startup Circuit

•

Programmable Line Undervoltage Lockout (UVLO) with Adjustable Hysteresis

•

Cycle by Cycle Peak Current Limiting

•

Overcurrent Protection Based on Average Current

•

Short Circuit Protection

•

Programmable Duty Ratio Clamp

•

Programmable Soft−Start

•

Programmable Shutdown and Restart Delays

•

Programmable External Overtemperature Protection Using Thermistor

•

FLT/SD pin Used for Fault reporting and Shutdown Input

•

Programmable Oscillator with 1.5 MHz Maximum Frequency

•

5 V/2% Voltage Reference

•

Main Switch Drive Capability of −2 A/3 A

•

Active Clamp Switch Drive Capability of −2 A/1 A

•

^VCC Range: from 6.5 V to 20 V

•

These Devices are Pb−Free, Halogen Free/BFR Free and RoHS Compliant

Typical Applications

•

High Efficiency Isolated dc−dc Converters

•

Server Power Supplies

•

24 V and 48 V Telecom systems

•

42 V Automotive Applications

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MARKING DIAGRAM

QFN24 MN SUFFIX CASE 485CW

See detailed ordering, marking and shipping information on page 30 of this data sheet.

ORDERING INFORMATION A = Assembly Location L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package 1565 ALYWG

G 1

(Note: Microdot may be in either location)

VSCLAMP NC VIN NC NC UVLOOTPREFCSNC

RES

COMP

RAMP SS DLMT DT RT AGND

REFA

OUTA PGND OUTM VCC

FLT/SD 1

2 3 4 5 6

18 17 16 15 14 13

7 8 9 10 11 12

24 23 22 21 20 19

PIN CONNECTIONS

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Figure 1. Typical Application Circuit in Voltage Mode Control

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Figure 2. Typical Application Circuit in Current Mode Control

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Figure 3. Functional Block Diagram

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DETAILED PIN DESCRIPTION

Pin Number Name Function

1 RAMP PWM modulator ramp. In voltage mode an external R−C circuit from V_in sets the PWM Ramp slope to implement feedforward. In current mode control, the resistor of the external R−C circuit connects to REF for ramp compensation.

2 SS

Soft−start control. A 20 mA current source charges the external capacitor connected to this pin. Duty ratio is limited during startup by comparing the voltage on this pin to a level−shifted VSCLAMP signal.

Under steady state conditions, the SS voltage is approximately 4.5 V. Once a fault is detected the SS capacitor is discharged and the controller is disabled.

3 DLMT Maximum duty ratio limit. A resistor between this pin and AGND sets the maximum duty ratio of the controller.

4 DT Dead time control. An external resistor between this pin and AGND sets the overlap time delay between OUTM and OUTA.

5 RT Oscillator frequency setting pin. The total external resistance connected between the RT and AGND pins sets the internal oscillator frequency.

6 AGND

Analog circuit ground reference. All control and timing components that connect to AGND should have the shortest loop possible to this pin to improve noise immunity. It should be tied to PGND at the return of the power stage.

7 COMP

Input to the pulse width modulator. An external optocoupler connected between the REF and COMP pin sources current into an internal NPN current mirror. The maximum duty ratio is achieved when no current is sourced by the optocoupler. The duty cycle reduces to zero once the source current exceeds 850 mA. The internal current mirror improves the frequency response by reducing the ac voltage across the optocoupler transistor.

8 RES

Restart time control. A capacitor between this pin and AGND set the shutdown delay and hiccup mode restart delay time. If a restart fault is detected, a pull−up current source, I_RES(SRC1), typically 20 mA is enabled. If the RES pin voltage, V_RES, exceeds the restart threshold, V_RES(TH), typically 1 V, the controller enters restart mode. I_RES(SRC1) is disabled once in restart mode and a second pull up current source, I_RES(SRC2), typically 5 mA enabled. I_RES(SRC2) is disabled once V_RES reaches V_RES(peak), typically 4 V. A pull−down current source, I_RES(SNK), typically 5 mA, is enabled until VRES falls below VRES(valley) typically 2 V. The controller restarts after 32 V_RES charge/discharge cycles.

9 NC No connect.

10 CS

Current sense input. The current sense signal is used for current−mode control, adaptive dead time control, cycle−by−cycle current limiting, over−current protection and short circuit protection, etc.

If the CS voltage exceeds the cycle by cycle current limit threshold, V_ILIM, typically 0.45 V, the drive pulse is terminated. Internal leading edge blanking prevents triggering of the cycle by cycle current limit during normal operation. A short circuit condition exists if V_CS exceeds the short−circuit threshold, V_ILIM(SC), typically set to 0.7 V, during two consecutive clock pulses.

11 REF Precision 5 V reference. Maximum output current is 12 mA. It is required to bypass the reference with a capacitor. The recommended capacitance ranges between 0.1 to 0.47 mF.

12 OTP Over−temperature protection. A voltage divider containing a NTC connects to this pin.

13 VCC

Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source, I_start, supplies current from V_in to this pin. Once V_CC reaches V_CC(on), typically 9.5 V, the startup current source is disabled. The current source is enabled once V_CC falls below V_CC(off1), typically 9.4 V, while faults are present. Once faults are removed and the controller is operating, the startup current source turn−on threshold is reduced to V_CC(off2), typically 7.5 V..

14 OUTM Main switch gate control. OUTM can source 2 A and sink 3 A.

15 PGND Ground connection for OUTM and OUTA. Tie to the power stage return with a short loop.

16 OUTA Active clamp switch gate control. OUTA has an adjustable leading and trailing edge overlap delay against OUTM. OUTA can source 2 A and sink 1 A.

17 FLT/SD Fault report and shutdown control. This is a dual−function bi−directional pin. This pin is an open−collector output with a 10 kW internal pull−up resistance connected to REF.

18 REFA Internally connected to REF.

19 UVLO

Input voltage undervoltage detector. The input voltage is scaled down and sampled by means of a resistor divider. The controller enters standby mode once the UVLO voltage, V_UVLO, exceeds the standby threshold, V_STBY, typically 0.4 V. The controller enters shutdown mode if V_UVLO falls below V_STBY by the shutdown hysteresis level. The controller is enabled once V_UVLO exceeds the enable threshold, V_enable, typically 1.25 V. Hysteresis is provided by an internal pull−down current source, I_UVLO, typically 20 mA. The current source is disabled once the controller is enabled.

20 NC No connect (creepage distance).

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DETAILED PIN DESCRIPTION

Pin Number Name Function

22 V_in

High voltage startup circuit input. Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant current source supplies current from this pin to the capacitor connected to the VCC pin, eliminating the need for a startup resistor. The minimum charge current is 40 mA. The operating voltage range of the startup circuit is 13 V to 120 V.

24 VSCLAMP

Volt−second clamp. An external R−C divider from the input line generates a voltage ramp. This ramp is compared to a voltage reference, V_SLIMIT, typically 1.5 V. The OUTM pulse is terminated once the ramp voltage exceeds V_SLIMIT, thus limiting the maximum volt−second product of the main transformer. In voltage mode, VSCLAMP and RAMP pins can be tied together to share one external R−C circuit.

MAXIMUM RATINGS (Notes 1 through 3)

Rating Symbol Value Unit

High Voltage Startup Circuit Input Voltage V_in −0.3 to 120 V

High Voltage Startup Circuit Input Current I_in 70 mA

UVLO Input Voltage V_UVLO −0.3 to V_CC V

OTP Input Voltage V_OTP −0.3 to 7 V

Ramp Input Voltage V_Ramp −0.3 to 7 V

Ramp Peak Input Current I_Ramp 1 A

VSClamp Input Voltage V_SCLAMP −0.3 to 7 V

VSClamp Input Current I_SCLAMP 0.5 mA

RT Input Voltage V_RT −0.3 to 7 V

RT Input Current I_RT 2 mA

COMP Input Voltage V_COMP −0.3 to 5.5 V

COMP Input Current I_COMP 1 mA

Reference Input Voltage V_REF −0.3 to 5.5 V

Reference Input Current I_REF 20 mA

Supply Input Voltage V_CC(MAX) −0.3 to 20 V

Supply Input Current I_CC(MAX) 70 mA

Main Driver Maximum Voltage V_OUTM −0.3 to V_CC V

Main Driver Maximum Current I_OUTM(SRC)

I_OUTM(SNK)

2 3

A

Active Clamp Driver Maximum Voltage V_OUTA −0.3 to V_CC V

Active Clamp Driver Maximum Current I_OUTA(SRC)

I_OUTA(SNK)

2 1

A

Current Sense Input Voltage V_CS −0.3 to 5.5 V

Current Sense Peak Input Current I_CS 0.5 A

Soft−Start Input Voltage V_SS −0.3 to 5.5 V

Restart Input Voltage V_RES −0.3 to 5.5 V

Restart Peak Input Current I_RES 0.1 A

FLT/SD Input Voltage V_FLT/SD −0.3 to 7 V

FLT/SD Peak Input Current I_FLT/SD 0.1 A

Deadtime Input Voltage V_DT −0.3 to 5.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.

2. As specified for a JEDEC EIA/JESD 51.3 conductivity test. Test conditions were under natural convection of zero air flow.

3. V_in is the exception.

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MAXIMUM RATINGS (Notes 1 through 3)

Rating Symbol Value Unit

Maximum Duty Ratio Control Input Voltage V_DLMT −0.3 to 5.5 V

Maximum Duty Ratio Control Input Current I_DLMT 2 mA

Maximum Operating Junction Temperature T_J −40 to 150 °C

Storage Temperature Range T_STG −60 to 150 °C

Lead Temperature (Soldering, 10 s) T_L(MAX) 300 °C

Moisture Sensitivity Level MSL 1 −

Power Dissipation (T_A = 25°C, 1 Oz Cu (35 mm), 0.155 Sq Inch (100 mm²) Printed Circuit Copper Clad)

MNTXG Suffix, Plastic Package (QFN−24)

P_D

760

mW

Thermal Resistance, Junction−to−Ambient 1 Oz Cu (35 mm) 2−Layer 100 mm² Printed Circuit Copper Clad (Note 3)

R_θ_JA

131

°C/W

Thermal Resistance, Junction−to−Ambient 2 Oz Cu (70 mm) 2−Layer 100 mm² Printed Circuit Copper Clad (Note 3)

R_θJA

115

°C/W

ESD Capability

Human Body Model per JEDEC Standard JESD22−A114F.

Machine Model per JEDEC Standard JESD22−A115C.

Charge Device Model per JEDEC Standard JESD22−C101E.

> 2000

> 200

> 1500

V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78.

2. As specified for a JEDEC EIA/JESD 51.3 conductivity test. Test conditions were under natural convection of zero air flow.

3. V_in is the exception.

ELECTRICAL CHARACTERISTICS: (C_REF = 0.1 mF, V_in = 48 V, V_UVLO = 2 V, V_CC = 10 V, V_CS = 0.25 V, R_DLMT = 49.9 kW, R_DT = 100 kW, R_T = 100 kW, for typical values T_J = 25°C, for min/max values, T_J is − 40°C to 125°C, unless otherwise noted)

Characteristics Conditions Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS

Supply Voltage Upper Regulation Level Lower Regulation While Disabled Lower Regulation While Enabled Minimum Operating Voltage Reset Voltage

V_CC increasing V_CC decreasing V_CC decreasing V_CC decreasing V_CC decreasing

V_CC(on) V_CC(off1) V_CC(off2) V_CC(MIN) V_CC(reset)

9.1 9.0 7.3 6.2 6.1

9.5 9.4 7.5 6.5 6.4

9.9 9.8 7.7 6.8 6.7

V

Startup Delay Delay from V_CC(on) to Enable tdelay(start) 30 − 125 ms

Delay in turning start−up source off V_CC > V_CC(off2) t_Vcc(off2) 3 10 ms

Delay in turning start−up source on V_CC < V_CC(off2) t_Vcc(on2) 15 30 ms

Startup Current V_CC = V_CC(on) − 0.2 V, V_in = 48 V I_start 40 55 − mA

Startup Circuit Off−State Leakage Current

V_in = 120 V I_Vin(off) − − 100 mA

Minimum Startup Voltage I_start = 15 mA, V_CC = V_CC(on) − 0.2 V V_in(MIN) − − 15 V

Supply Current Disabled mode current Standby

No Switching Operating Current

UVLO below 0.4 V V_CC = 10 V, V_UVLO = 1 V V_CC = 10 V, I_COMP = 850 mA f = 200 kHz, C_OUTM = C_OUTA = open

I_CC1 I_CC2 I_CC3 I_CC4

−

2 2 4 5

mA

REFERENCE

Reference Voltage I_REF = 0 mA V_REF 4.9 5.0 5.1 V

Load Regulation I_REF = 0 to 10 mA VREF(load−reg) 4.85 5.00 5.15 V

Step Load Response I_REF = 5 to 10 mA, di/dt = 100 mA/ms VREF(step−reg) 4.85 5.00 5.15 V

Source Current V_REF = 4.75 V I_REF(MAX) 12 − − mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Guaranteed by Design. Not Tested.

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REFERENCE

Minimum Capacitance (Note 4) C_REF(range) 0.1 − − mF

Reference Undervoltage Threshold V_REF increasing V_REF(UVLO) 4.5 4.75 V

Reference Undervoltage Hysteresis V_REF decreasing V_REF(HYS) 200 mV

LINE VOLTAGE UVLO

Standby Threshold V_UVLO increasing V_STBY 0.35 0.40 0.45 V

Standby Hysteresis V_UVLO decreasing V_STBY(HYS) 0.05 0.10 0.15 V

Enable Threshold V_UVLO increasing V_enable 1.23 1.25 1.27 V

Disable Filter Delay V_UVLO = V_enable − 400 mV tenable(delay2) 0.5 − 1 ms

Pull−Down Current in Standby Mode V_UVLO = V_enable - 0.1 V V_SHDN < V_UVLO < V_enable

I_STBY 18 20 22 mA

Pull−Down Current Enable Threshold I_STBY(THD) − V_CC(off2) − V

Pull−Down Resistor while ISTBY is Disabled

V_UVLO = 1.25 V R_UVLO 22.4 32.0 41.6 kW

MAIN GATE DRIVE

Rise Time (10−90%) from 10% to 90% of V_OUTM, C_OUTM = 2.2 nF t_OUTM(rise) − 8.8 17.6 ns

Fall Time (90−10%) 90% to 10% of V_OUTM, C_OUTM = 2.2 nF t_OUTM(fall) − 6.0 12 ns

Current Capability Source Sink

V_OUTM = 4 V

V_OUTM = 4 V, V_CC = 7.5 V, I_COMP = 850 mA

I_OUTM(SRC) I_OUTM(SNK)

2 3

−

− A

High State Voltage Offset V_CC − V_OUTM, V_CC = 8 V, C_OUTM = 2.2 nF VOUTM(offset) − − 0.2 V

Low Stage Voltage V_UVLO = 1 V V_OUTM(low) − − 0.2 V

ACTIVE CLAMP GATE DRIVE

Rise Time (10−90%) from 10 to 90% of V_OUTA, C_OUTA = 2.2 nF t_OUTM(rise) − 8.8 17.6 ns

Fall Time (90−10%) 90 to 10% of V_OUTA, C_OUTA = 2.2 nF t_OUTM(fall) − 17.6 35.2 ns

Current Capability Source Sink

V_OUTA = 4 V V_OUTA = 4 V, V_CC = 7.5 V

I_OUTA(SRC) I_OUTA(SNK)

2 1

−

− A

High State Voltage Offset V_CC − V_OUTA, V_CC = 8 V, C_OUTA = 2.2 nF VOUTA(offset) − − 0.2 V

Low Stage Voltage V_UVLO = 1 V V_OUTA(low) − − 0.2 V

CURRENT SENSE

Average Current Limit Threshold V_ILIM(ave) 288 300 312 mV

Average Current Limit Leading Edge Blanking Duration (Note 4)

tILIMAVE(LEB) 23 30 37 ns

Average Current Limit Propagation Delay (Note 4)

tILIMAVE(delay) − 40 − ns

Cycle by Cycle Current Limit Threshold

V_ILIM 432 450 468 mV

Cycle by Cycle Current Limit Leading Edge Blanking Duration

t_ILIM(LEB) 42 55 68 ns

Cycle by Cycle Current Limit Propagation Delay

Step V_CS to 0.7 V to OUTM falling edge, dV/dt = 20 V/ms

tILIM(delay) − 40 56 ns

Short Circuit Current Limit Threshold V_ILIM(SC) 672 700 728 mV

Short Circuit Current Limit Leading Edge Blanking Duration

tILIMSC(LEB) 23 30 37 ns

Short−Circuit Current Limit Propagation Delay

Step V_CS to 0.9 V to OUTM falling edge, dV/dt = 10 V/ms

tILIMSC(delay) − 40 56 ns

Short Circuit Counter Step V_CS to V_ILIM(SC) + 0.2 V n_ILIMSC − 2 − −

Discharge Switch On Resistance V_SCLAMP = 2 V, V_CS = 100 mV RCSswitch(on) − − 35 W

5. Guaranteed by Design.

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OVERTEMPERATURE PROTECTION (OTP)

Overtemperature Detect Threshold V_OTP increasing V_OTP(TH) 1.23 1.25 1.27 V

Overtemperature Detect Delay V_OTP = V_OTP(TH) − 20 mV t_OTP(delay) 10 20 30 ms

Pull−up Current in OTP Mode V_OTP = V_OTP(TH) + 0.1 V I_OTP 18 20 22 mA

SOFT−START

Soft−Start Charge Current V_SS = 1.5 V to 3 V I_SS 18 20 22 mA

Soft−Start Onset Threshold V_SS(offset) 1.35 V

Clamp Voltage V_SS(clamp) 0.85 V

Discharge Switch On Resistance V_SS = 100 mV RSSswitch(on) − − 30 W

Disable Threshold V_SS decreasing VSS(disable) 0.4 0.5 0.6 V

RESTART

Restart Delay Threshold V_RES increasing V_RES(TH) 0.96 1.00 1.04 V

Peak Voltage V_CS > V_ILIMAVE, V_RES increasing V_RES(peak) 3.8 4.0 4.2 V

Valley Voltage V_CS > V_ILIMAVE, V_RES decreasing VRES(valley) 1.9 2.0 2.1 V

Discharge Current V_CS < V_ILIMAVE, V_RES = 100 mV I_RES(SNK) 4 5 6 mA

Charge Current V_CS > V_ILIMAVE, V_RES = VRES(valley) − 50 mV V_CS > V_ILIMAVE, V_RES = VRES(valley) + 50 mV

I_RES(SRC1) I_RES(SRC2)

18 4

20 5

22

6 mA

Restart Counter V_OTP > V_OTP(TH) n_RES 32

Discharge Voltage V_RES(DIS) 50 100 150 mV

Discharge Switch On Resistance V_RES = 200 mV RESswitch(on) − − 110 W

FAULT REPORT and REMOTE SHUTDOWN

Enable Threshold V_FLT/SD = increasing VFLT(enable) 1.37 1.45 1.53 V

Fault Threshold V_FLT/SD = decreasing VfaultFLT/SD 1.23 1.25 1.27 V

Internal Pull−Up Resistor V_FLT/SD = 3 V R_FAULT/SD 8.5 10.0 11.5 kW

Discharge Switch On Resistance V_FLT/SD = 100 V RFAULTswitch(on) − − 120 W

OSCILLATOR

Operating Frequency Range (Note 5) f_range 100 − 1500 kHz

Oscillator Frequency t_D1≈ 100 ns t_D1≈ 75 ns

R_T = 49.9 kW, R_DT = 69.8 kW, R_DLMT = 26.7 kW

R_T = 16.2 kW, R_DT = 52.3 kW, R_DLMT = 9.09 kW f_OSC1 f_OSC2

180 540

200 600

220 660

kHz

MAXIMUM DUTY RATIO

Maximum Duty Ratio F_sw = 200 kHz F_sw = 600 kHz

Internal spec is ± 3%, V_UVLO = 1.4 V R_T = 49.9 kW, R_DT = 69.8 kW, R_DLMT = 41.2 kW R_T = 49.9 kW, R_DT = 69.8 kW, R_DLMT = 34.0 kW R_T = 49.9 kW, R_DT = 69.8 kW, R_DLMT = 26.7 kW R_T = 16.2 kW, R_DT = 52.3 kW, R_DLMT = 14.0 kW R_T = 16.2 kW, R_DT = 52.3 kW, R_DLMT = 11.5 kW R_T = 16.2 kW, R_DT = 52.3 kW, R_DLMT = 9.09 kW

D_(MAX1a) D_(MAX2a) D_(MAX3a) D_(MAX1b) D_(MAX2b) D_(MAX3b)

76.5 62.8 48.8 76.2 62.1 47.8

80.5 66.1 50.3 80.2 65.4 49.3

84.5 69.4 53.8 84.2 68.7 52.8

%

Minimum Duty Ratio I_COMP = 850 mA D_(MIN) − − 0 %

VOLT−SECOND CLAMP

Volt Second Limit Voltage Threshold I_COMP = 0 mA V_SLIMIT 1.44 1.50 1.56 V

Volt−Second Propagation Delay Step V_SCLAMP to 2 V to OUTM falling edge, dV/dt = 10 V/ms t_VSCLAMP 40 60 ns

VSCLAMP Switch On Resistance V_SCLAMP = 100 mV RVSCLAMPswitch(on) − − 45 W

VSCLAMP Input Leakage Current V_SCLAMP = 1.4 V IVSCLAMP(leak) − − 100 nA

OVERLAP TIME DELAY

Overlap Delay Range (Note 5) Include UVLO Adjustment. But not CS. t_D(range) 20 − 500 ns

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OVERLAP TIME DELAY

Overlap Delay from OUTA to OUTM rising Edges

R_DT = 52.3 kW, V_UVLO = 2.5 V, V_CS = 0.4 V R_DT = 52.3 kW, VUVLO = 2.5 V, V_CS = 0.05 V

R_DT = 69.8 kW, VUVLO = 2.5 V, V_CS = 0.4 V R_DT = 69.8 kW, V_UVLO = 1.5 V, V_CS = 0.05 V

R_DT = 274 kW, V_UVLO = 3 V, V_CS = 0.4 V R_DT = 274 kW, V_UVLO = 3 V, V_CS = 0.05 V

t_D1a t_D1b t_D1c t_D1d t_D1e t_D1f

47.3 56.8 63.1 107.1 206.5 259.9

63 95 84 179 275 433

78.8 132.6 105.2 250 344.2 606.4

ns

Overlap Delay from OUTM to OUTA Falling Edges

R_DT = 52.3 kW, V_UVLO = 2.5 V, V_CS = 0.4 V R_DT = 52.3 kW, V_UVLO = 2.5 V, V_CS = 0.05 V

R_DT = 69.8 kW, V_UVLO = 2.5 V, V_CS = 0.4 V R_DT = 69.8 kW, V_UVLO = 1.5 V, V_CS = 0.05 V

R_DT = 274 kW, V_UVLO = 3 V, V_CS = 0.4 V R_DT = 274 kW, V_UVLO = 3 V, V_CS = 0.05 V

t_D2a t_D2b t_D2c t_D2d t_D2e t_D2f

31.2 37.5 41.6 70.7 136.3 171.5

42 63 56 118 182 286

52 87.5 69.4 165 227.2 400.2

ns

Ratio from t_D1 to t_D2 − 0.66 −

RAMP

PWM Propagation Delay Step V_RAMP to 2 V to OUTM falling edge, dV/dt = 10 V/ms

t_PWM 40 60 ns

PWM Offset Voltage VPWM(offset) 1.35 V

Discharge Switch On Resistance V_RAMP = 100 mV RAMPswitch(on) − − 25 W

RAMP Input Leakage Current V_RAMP = 1.8 V I_RAMP(leak) − − 100 nA

THERMAL SHUTDOWN

Thermal Shutdown Temperature increasing T_SHDN 150 165 − °C

Thermal Shutdown Hysteresis Temperature decreasing T_SHDN(HYS) − 20 − °C

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TYPICAL OPERATING CHARACTERISTICS

T_J, JUNCTION TEMPERATURE (°C) Figure 4. Turn−on Voltage Variation vs.

Junction Temperature

VCC(on) (V)

9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 5. Turn−off Voltage 1 Variation vs.

VCC(off1) (V)

9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 6. Turn−off Voltage 2 Variation vs.

VCC(off2) (V)

7.7

−50 −30 −10 10 30 50 70 90 110 130

7.65 7.6 7.55 7.5 7.45 7.4 7.35 7.3

T_J, JUNCTION TEMPERATURE (°C) Figure 7. Minimum Operating Voltage

Variation vs. Junction Temperature

VCC(min) (V)

6.8

−50 −30 −10 10 30 50 70 90 110 130

6.7 6.6 6.5 6.4 6.3 6.2

T_J, JUNCTION TEMPERATURE (°C) Figure 8. Reset Voltage Variation vs. Junction

Temperature

VCC(reset) (V)

6.7

−50 −30 −10 10 30 50 70 90 110 130

6.6 6.5 6.4 6.3 6.2 6.1

T_J, JUNCTION TEMPERATURE (°C) Figure 9. Start−up Current Variation vs.

Junction Temperature ISTART (V)

−40

−50 −30 −10 10 30 50 70 90 110 130

−45

−50

−55

−60

−65

−70

−75

−80

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T_J, JUNCTION TEMPERATURE (°C) Figure 10. Minimum Startup Voltage on the HV Pin Variation vs. Junction Temperature

VIN(min) (V)

15.0

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 11. Operating Current in Disabled

Mode vs. Junction Temperature

ICC1(UVLO=0V) (mA)

1.9

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 12. Operating Current in Standby

Mode vs. Junction Temperature

ICC2(VUVLO=1V) (mA)

1.9

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 13. Operating Current in Active Mode

but Without Switching vs. Junction Temperature

ICC3(Icomp=850mA) (mA)

3.9

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 14. Operating Current While Switching

Without Load on Driver Outputs vs. Junction Temperature

ICC4(200kHz

No Load)

(mA)

5.0

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 15. Fault Pin Activation Level vs.

Junction Temperature VFAULT (FLT/SD)

1.270

−50 −30 −10 10 30 50 70 90 110 130

14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0

1.7 1.5 1.3 1.1 0.9 0.7 0.5

1.7 1.5 1.3 1.1 0.9 0.7

3.7 3.5 3.3 3.1 2.9 2.7 2.5

4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2

1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230

(13)

T_J, JUNCTION TEMPERATURE (°C) Figure 16. Reference Voltage Variation vs.

Junction Temperature VREF (V)

5.10

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 17. Standby Threshold Variation vs.

Junction Temperature VStby (V)

0.45

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 18. Enable Voltage Variation vs.

VENABLE (V)

1.270

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 19. Average Current Limit Threshold

Variation vs. Junction Temperature

VILIMAVE (mV)

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 20. Cycle by Cycle Current Limit

Threshold Variation vs. Junction Temperature

VILIM (mV) 467

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 21. Short−Circuit Current Limit

Threshold Variation vs. Junction Temperature

VILIMSC (mV)

617

−50 −30 −10 10 30 50 70 90 110 130

308 5.08

5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 4.90

0.44 0.43 0.42 0.41 0.40 0.39 0.38 0.37 0.36 0.35

1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230

303

298 293 288

462 457 452 447 442 437 432

612 607 602 597 592 587 582

(14)

T_J, JUNCTION TEMPERATURE (°C) Figure 22. OTP Threshold Variation vs.

Junction Temperature VOTP(TH) (V)

1.270

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 23. OTP Current Variation vs. Junction

Temperature IOTP (mA)

22.0

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 24. Oscillator Frequency Variation vs.

Junction Temperature (F_SW = 200 kHz)

FOSC1 (kHz)

220

−50 −30 −10 10 30 50 70 90 110 130

FOSC2 (kHz)

−50 −30 −10 10 30 50 70 90 110 130

Junction Temperature (F_SW = 1.5 MHz)

FOSC3 (kHz)

1700

−50 −30 −10 10 30 50 70 90 110 130

T_J, JUNCTION TEMPERATURE (°C) Figure 27. Maximum Duty Ratio Variation vs.

DMAX1a(200kHz) (%)

84.5

−50 −30 −10 10 30 50 70 90 110 130

660 1.265

1.260 1.255 1.250 1.245 1.240 1.235 1.230

21.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0

215 210 205 200 195 190 185 180

640 620 600 580 560 540

1650 1600 1550 1500 1450 1400 1350

83.5 82.5 81.5 80.5 79.5 78.5 77.5 76.5