High-Density Ac-Dc Power Supplies using Active-Clamp Flyback Topology

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Public Information © onsemi 2022 Public Information © onsemi 2022

High-Density Ac-Dc Power Supplies using Active-Clamp Flyback Topology

Ajay Hari, Bryan McCoy

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Agenda

• Introduction to active-clamp flyback operation (ACF)

• ACF light-load efficiency challenge

• Introduction to the NCP1568 – Ac-Dc ACF PWM IC.

• Light load and standby solution

• Design equations for transformer selection of the ACF

• Primary and secondary component selection considerations

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Introduction to

Active-Clamp Flyback Operation (ACF)

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Active-Clamp Flyback

Vin

Clamp Capacitor

Main Switch

Load

R

D

Vin

Clamp Capacitor

Active Clamp Switch

Main Switch

Load

v The clamp diode in a standard flyback converter is replaced by a switch hence the name Active-Clamp Flyback or ACF.

Standard Flyback Converter w. RCD clamp Active-Clamp Converter

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Traditional Flyback Converter

q V_clamp is generally 50% to 100% greater than the reflected output voltage:

(N_p/N_s*V_out)

q The leakage rapidly resets but delays the secondary current settling

q The leakage energy and a small part of the magnetizing energy are dissipated

leak ,

C

L leak L pk

C

E k L I

k

= +

× 1 2

2

( )

( ) ( )

. .

P

Q os c out f c

S P

clamp c out f

S

V k N V V with k

N

V k N V V

N

- = × + £ £

= + × +

0 5 1 0

1

Vin

Clamp Capacitor

Main Switch

Load

R D

5

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Active Clamp Flyback Converter

q The clamp voltage is nearly (N_p/N_s*V_out)

q The AC switch allows a bi-directional circulation of the leakage current q The leakage energy is circulated and a large part is provided to the load q ZVS possible with smooth current and voltage settling

Vin

Clamp Capacitor

Active Clamp Switch

Load

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Why Active-Clamp Flyback?

v Zero-Volt Switching of the FETs with Fixed-Switching Frequency

v Results in high switching frequency, improves efficiency and EMI.

v Soft Increase in Secondary Current v Good for EMI

v Clean Drain Waveforms Without Any Ringing

v Better efficiency as the leakage energy is recycled.

v Better EMI

v Single-Ended Topology

v Relatively simple design of magnetics compared to LLC.

v Single switch/diode in the secondary.

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Energy-Storage Mode

Lmag

Im(on)

Reverse Biased

Iout Vin

Lleak

V_out = V_in N_S N_P

D 1−D

v The energy-storage mode is similar to that of a classical flyback

converter: when the main FET is on, energy is stored in the transformer.

v ACF works in continuous conduction mode. Its input-to-output relationship is given by:

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Lmag Iout

Vin

Lleak

Cclamp

Body Diode

Vsw

SW

Tcharge

Transition from Energy-Storage Mode to Power-Delivery Mode

T_charge= C_lump (V_in+V_clamp ) I_m(peak)

V_clamp= V_in D 1-D

vWhen FET turns off, the lump capacitor on the SW node is linearly charged at a rate given by T_charge

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Power-Delivery Mode

Lmag

Vin

Lleak

Cclamp

Isec

v In this mode, L_leak resonates with

clamp capacitor (C_clamp). The resonant frequency is given by:

F_res= 1

2π L_leakC_clamp

I_res=I_mcos

( )

ωt

v The primary resonant current is given by:

v The magnetizing current during the (1- D) phase is given by:

I_mag=V_clamp T_off vThe difference between the primary resonant current L

and the magnetizing current flows in the secondary

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Transition from Power-Delivery Mode to Energy-Storage Mode

vWhen the clamp FET turns off, L_leak resonates with C_clamp. For the main FET to get ZVS, following condition has to be satisfied

Lmag

Vin

Lleak

C_clamp

Isec

Clump

V_sw

L_leakI_pri² >C_lumpV_SW²

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Leakage Inductance Needed for ZVS

0 2 4 6 8 10 12 14

100 150 200 250 300 350 400

Leakage Inductance (µH)

Input Voltage (V)

vFor universal design, leakage inductance needed to get ZVS increases in a parabolic fashion.

vIncreasing leakage & tightly controlling the spread add cost

vAdditional resonant inductor is an alternative, but inductor adds cost & volume

v Assuming C_lump = 220 pF, constant I_peak = 1 A, 85 V to 265 V rms (universal input)

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ZVS Phenomenon – 1

vDuring T_dis1 (shaded region), v L_leak resonates with C_clamp.

vThe time it takes for the resonance between leakage inductance and lump capacitance to reach its valley point is 1/4^th of a resonant period. Therefore:

T_dis1= π

2 L_leakC_lump

V_valley=I_mag(peak) L_leak C_lump Imag

I_sec

0 A Vsw

Tdis1

Tdis2

I_valley

Vvalley

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ZVS Phenomenon – 2

vDuring T_dis2 (shaded region), negative magnetizing current starts to discharge the clamp capacitance

vThe time it takes to discharge the lump capacitance is given by:

Imag

Isec

0 A Vsw

Tdis1

Tdis2

Ivalley

Vvalley

T_dis2=C_lump V_sw-V_valley I_valley

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Fixed-Frequency Operation

Load I_mag Frequency

0A

0A Fixed frequency Operation

vMagnetizing current in ACF is in CCM.

vAs the load current decreases, the valley point of the magnetizing

current decreases.

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Variable-Frequency Operation

Load Frequency

0A

0A Variable frequency Operation

I_mag

vAs the load current decreases, increasing the frequency minimizes I_mag and reduces the conduction losses.

vIdeally, the valley of the magnetizing

current needs to be maintained constant for ZVS.

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Light-Load Efficiency

&

Standby Power Challenge

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Light-Load Efficiency Requirements

• European Code of Conduct, Ver. 5, Tier 2 poses stringent efficiency standards at light- load condition

vFor a 60-W design, 4-point average (25%, 50%, 75%, and 100% average) efficiency needs to be > 88% for full load and 78% for 10% load.

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Standby Power Standard

v US DoE standards are equally stringent

v Most of the brand name OEMs require to pass stringent Tier-2 standard

DoE: Department of Energy

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ACF Specific Light-Load Challenges

vMagnetizing current is in CCM.

vFrequency modulation results in high-frequency operation at light load vClassical frequency foldback is not possible to implement when

magnetizing current is in CCM

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DCM Operation

L_mag

Iout Vin

Isec L_leak

OFF

Cclamp Main Gate

Imag

V_sw

vHolding active-clamp FET off, DCM operation can be implemented in ACF.

vThis allows magnetizing current to enter DCM: frequency foldback can be implemented

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Introduction to NCP1568

Ac-Dc PWM Controller for ACF

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Introduction to NCP1568

1 2

4 5 6 7 8

16 15 14

12 11 10 9 HV

FLT RT

CS DTH

ADRV SW

VCC LDRV GND FB

NC

ATH 3 NC

13 NC NC NCP1568

Control Scheme

• Adaptive ZVS frequency modulation allows variable V_out operation

• Integrated adaptive dead-time

• Peak-current-mode control DCM & Light-Load Operation

• Optional transition to DCM mode

• Frequency foldback with 31-kHz minimum frequency clamp

• Quiet skip eliminates audible noise

• Standby power < 30 mW HV Startup

• 700-V HV startup JFET

• Integrated sensing of HV SW node for optimum ZVS

• Brownout and X2 discharge inbuilt.

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Frequency Movement vs. Load

NCP1568

Active Clamp Mode

Transition Mode

DCM Mode Frequency Foldback F

F/2

25 kHz Clamp Frequency

FB α Iload

V_DTH Fmax=4.2*F

Skip

V_ATH

v NCP1568 features a combination of nonlinear & linear foldback schemes

v The lower the frequency at light load, the higher the efficiency

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Clamp Capacitor Challenge

L_mag

Iout Vin

I_sec L_leak

OFF

C_clamp R_clamp

vV

_{CLAMP_DCM}

>V

_{CLAMP_ACF}

v Leakage energy is not recycled in DCM and is dissipated in the clamp resistor (R

_Clamp

)

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Transition from DCM to ACF

vActive-clamp FET can be soft-started to discharge the clamp capacitor slowly.

vLeading-edge modulation of active-clamp FET

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DCM Operation Determination

v NCP1568 can be configured to operate in pure ACF mode and pure DCM mode.

v Efficiency can be plotted in both ACF and DCM to determine optimal transition

points.

v NCP1568 uses the feedback information to transition from ACF to DCM or vice- versa.

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Key Components Selection

Transformer Design & Key Equations

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Design Specifications

Description Min Typ Max Unit

Input Voltage 85 265 V rms

Line Frequency 47 63 Hz

Min Output Voltage 4.75 5 5.25 V

Max Output Voltage 19 20 21 V

Output Current 0 3.0 A

Target Full Efficiency @ 115, 230 V rms 93 %

Frequency ACF 100 400 kHz

Max Power 60 W

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Turns Ratio Selection

v Turns ratio can be calculated by the following formula assuming D_max=0.5.

N_PS= D_maxV_in(min) 1-D_max

( )

^V^out(max)

vTurns ratio should be calculated at the lowest input voltage while delivering maximum power

vFor this design, rounded turns ratio is 6.

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Minimum On-Time

T_min1= N_PS V_out(max) N_PS V_out(max) + V_in(max)

( )

^F^max

T_min2= N_PS V_out(min) N_PS V_out(min) + V_in(max)

( )

^F^min

v Minimum on-time needs to be calculated at worst case duty ratio to ensure that the controller can deliver the pulses

v NCP1568 has a minimum on-time of 200 ns. The calculated on-times of the above equations are 600 ns and 700 ns respectively.

v If the min on-time is < 200 ns, the turns ratio needs to be adjusted and the process iterated

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Valley Current for ZVS

C_lump=C_o(er)Q1+C_o(er)Q2+ C_o(er)Q3 N_PS²

vIn order to determine the inductance value, valley current is needed.

vTo calculate the valley current, the capacitance lumped at the SW node can be expressed as follows:

Main FET

Output capacitance Active Clamp FET Output

capacitance

Synchronous Rectifier FET

vThe above capacitances can be approximated from the FET datasheet.

vConsidering an ac-dc power supply, a 600-V FET for primary and a 120-V type for secondary have been selected resulting in a C of 220 pF

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Inductance Calculation

L_mag= V_in(min) D_min

2 F_SW(min) I_out(max) 1-D_min

( )

^N^PS ⁻^I^valley

⎛

⎝⎜⎜ ⎞

⎠⎟⎟

vInductance can be calculated as follows:

D_min= V_out(min) N_PS

V_out(min) N_PS+V_in(min) vWhere D_min is the minimum duty cycle given by:

v For this design, the above formula results in a magnetizing inductance of 120 µH

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Inductance vs. Required Valley Current for ZVS

80 100 120 140 160 180 200

0 0,1 0,2 0,3 0,4 0,5 0,6

Inductance (µH)

Required Valley Current (A)

v As the required valley current for ZVS decreases, the inductance falls.

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Core Selection

RM8LP_Loss=P_LossV × Volume_RM8LP

v Assuming a 200-mT B_max operating at 400 kHz results in a core loss of 1.8 W.

vA RM8LP core has been selected for this low-profile and high-density

design.

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Primary and Secondary Turns

N_P=

L_mag I_out(max) 1-D_min

( )

^N^PS ⁻^I^valley

⎛

⎝⎜⎜ ⎞

⎠⎟⎟

ΔB A_e N_S = N_P

N_PS

vThe primary and secondary turns can be calculated from the following formulae:

vThis results in a primary turns of 23.

vSince turns ratio is 6, 24 turns are selected for primary turns and 4 for secondary turns

vA flux density, ∆B, of 0.2 T & A_e of 65 mm² have been assumed for this design.

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Clamp Capacitor Selection

vClamp capacitor should be selected at worst-case off-time i.e., lowest

frequency and minimum D

vClamp capacitor should be selected such that it resonates 1/4^th of the

resonant period at worse case off-time.

vCeramic capacitors are selected for clamp capacitors. Standard derating should be followed (voltage and rms current).

vThe above equation results in 330 nF.

vAfter derating, a 660 nF is selected

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RMS Current Formulae

vThe primary and secondary FET selection criterion is no different than with standard flybacks.

vThe active-clamp FET voltage rating is same as main FET.

vThe clamp and secondary FETs see different current waveforms than standard flyback. Their formulae are noted below

I_AC(RMS) = I_PK × 1−D_min

6 ^I^sec(RMS) ⁼

2P_out

V_out × 2 1

(

−D_min

)

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60-W UHD-Board Performance

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Simplified Schematic

v Secondary side is similar to any standard flyback topology.

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Frequency Modulation w. Load

vAs the load current decreases, the negative current is minimized & kept constant leading to low conduction losses

2.25 A 1.7 A 1 A

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Fixed Frequency vs. Frequency Modulation

v 115 V rms, 1.5-A load v Fixed F_sw of 231 kHz v 115 V rms, 1.5-A load

v Frequency modulation, F_sw = 260 kHz

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Frequency Movement w. V

_out

& V

_in

Frequency movement is similar to QR flyback switching in 1^st valley

90 V rms 265 V rms

5 V 9 V 15 V 12 V 20 V

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Frequency vs. Load Current

Active- Clamp

Mode

0 50 100 150 200 250 300 350 400 450

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 2,4 2,6 2,8 3

Switching Frequency (kHz)

Load Current (A)

115 Vac Switching Frequency vs. Load Frequency

20V 15V 12V 9V 5V

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DCM SW waveforms

90 V rms

5 V 9 V 15 V 12 V 20 V

265 V rms

5 V 9 V 15 V 12 V 20 V

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NCP1568 USB PD 65-W UHD Demonstration Board

Featured Devices: NCP1568 ACF Controller

NCP51530 Half-Bridge Driver NCP4305 SR Controller

Full Load Efficiency: 93.4% @ 115 V rms (20 V/3.0 A) 93.6% @ 230 V rms (20 V/3.0 A) Transformer Type: RM8 LP

Power Density: 30 W/in³ or 1.7 W/cm³ Board Dimensions: 1.66” x 1.78” x 0.70” or

4.2 cm x 4.5 cm x 1.7 cm

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UHD Board Performance

vAchieving a full-load efficiency of 93.5% at a 60-W output vPrimary FETs running at 83 °C

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NCP1568 Demonstration Board Efficiency

80 82 84 86 88 90 92 94

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Efficiency (%)

Output Voltage (V)

4 Point Average Efficiency vs.

Output Voltage

230 VAC 115 VAC Limit

rms rms

70 72 74 76 78 80 82 84 86 88

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Efficiency (%)

Output Voltage (V)

10% Load Efficiency vs.

Output Voltage

115 VAC 230 VAC Limit

rms rms

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Key Takeaways

vACF results in ZVS for both main and active-clamp FETs.

vHigh-frequency operation while achieving high efficiency is possible.

vDCM transition is needed to pass stringent regulatory standards.

vElimination of heat sinks is possible with ACF topology.

vPower density while employing ACF is 2 to 3 times that of a standard ac-dc supplies vIndustry standard super-junction FETs yield excellent results up to 400 kHz.

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