C139 2005 12 ATS 最近の更新履歴 Hideo Fujiwara

IEEE the 14th Asian Test Symposium (ATS'05), pp. 126-131, Dec. 2005.

weighted scan enable signals control points

1

G R

test

2

k SC

T P

w

SC

SC

1 test

w2 wk MUX

P

S

M

R S I PIs

POs

observation points combinational circuits

Procedure select−weight−for−test−signals()

{

Assign the same values to the test signals as the ordinary test−per−

scan BIST scheme to all scan chains. That is, all test signals are

assigned as 1 in a sequence of scan shift cycles, and 0 for the

following capture cycle.

while the scan chain set is not empty, do

{

select a scan chain from the scan chain set

, and delete

from select the best weight from the weight set {0.5, 0.625,

0.75,0.875} that makes the cost function as stated in Equation (1)

minimum. If no weight can be selected for a scan chain,

set that test signal like the conventional test−per−scan scheme.

The selected weights and the testability estimation procedure is

adopted to evaluate the cost function.

}

}

phase shifter

0.625 0.875

0.75 _0.5

to the scan enable signals of the scan chains

D Q D Q

PPO₁

a m₁

Sin p

m_k ^k

m_k−1 ^a

PPO_k−1

D Q

b_k b_k−1

PPI_k−1 k−1

b1

a₁

PPI1 ^PPOk

S

PPI_k out test

5

5 5 99.87

99.25 96.92 99.95 97.58 97.65 100 99.30

MTS[18] TTS[10]

5 circuits

s1269 s1423 s1512 s3271 s3330 s3384 s4863 s5378

1417 1904 1834 3859 4136 4619 5123 6002

AO(%)

12.46 area

(PS) area (orig.)

CPU (second)

97.29

97.73 97.47 5

5 5 FC(%) FC(%)

STS

WTS STS _{ntp ntp ntp}

98.99 98.30 96.28 98.25 91.51 96.36 97.54 98.18 98.95

96.86 99.57 94.33 97.62 99.25 98.93

with test points

99.31 99.25 96.28 99.91 94.41 97.87 99.29 98.89 9

9 9 9 9 9 9 9

10.56 15.32 7.80 10.18 10.41 9.06 6.88

WTS MTS[18]

98.99

5 97.88

98.40 5 97.65 no test point( FC )

(connect) area

FC(%)

98.33

99.57 98.25 0.10

0.28 0.22 1.35 1.16 1.62 1.41 2.23 168

192 272 292 412 472 456 404

s9234 10207 320 9 3.22 12.43 91.88 90.70 89.71 88.02 20 93.65 20 93.61 20 92.50

s13207.1 17687 972 9 5.55 48.64 98.55 97.31 98.10 97.31

s15850 19643 564 9 2.92 43.16 95.01 93.86 93.85 93.64 15 97.32 15 96.51 15 96.19 s15850.1 19011 1012 9 5.37 56.86 95.42 94.12 94.01 93.48 15 97.51 15 96.58 15 96.28 s38417 48824 1480 9 3.05 573.0 97.27 97.06 97.26 95.85 15 99.07 15 98.86 15 98.05 s38584 47584 1216 9 2.57 472.2 96.33 95.91 95.88 95.46 13 97.34 13 97.12 13 96.83

b14 21323 9 2.07 25.3 92.12 91.49 91.62 89.93

b20 43003 9 1.48 161.1 95.41 94.00 94.70 93.28

b21 43811 9 1.45 162.4 93.39 93.01 94.26 91.83

93.54 94.80 94.37 94.99 347.9 1.25 9 63957 b22

average 96.72 95.91 96.08 94.88 97.63 97.08 96.54

432 628 628 628

96

86 88 90 92 94 98 FC(%)

100k 200k 300k 400k 500k

100k

100k 200k

200k 300k

300k 400k

400k 500k

500k 100k 200k 300k 400k 500k

# of clock cycles # of clock cycles

# of clock cycles # of clock cycles

WTS

STS TTS

MTS

96 94

88 86 90 92 FC(%)

FC(%) FC(%)

90 92 94 96 98

b20 s38584

s3330 s15850.1

WTS STS

MTS TTS

WTS STS

MTS TTS

86 90 92 94 96

88

WTS

STS TTS

MTS