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(57) ¤ 32 ` ºXQ 1 ® A ` RC . ¾½32 .546 ¸ 7 ȯ®03@ °× vF¬½` RC *9c§<k Q RC È ° ®áÉ b y ß %® U ® Q ÏsÐ %® UÓ® àWõGºl]2Ä ¤l{ 9.9% ; ¡ltCª ^ t9Q RC 6.3% °T®áÉ àJõ * 'ORQWylß Q Ï\Ð r´p2¤ÀÈàJõJ[s]0` Ä ¤W{ ; ¡Wtjª 6.1% 4.0% ¬ < Q '1<1>(? @1>1? 8(9 :1;s` = I Q '1<:1> ;1?A1@ B1C H D EF :1 + H Ñ VJG`Ùlw Ú 15500036 21 ½ O IJ COE; ×%Ð CØ21 © ¡ltjª ` KL *. Ü. 8. M. N. O. P. [1] R. Balasubramonian, et al., “Reduing the Complexity of the Register File in Dynamic Sperscalar Processors,” MICRO-34, pp.237248, Dec. 2001. [2] D. Burger, et al., “The SimpleScalar Tool Set, Version 2.0,” Technical Report CS-TR-97-1342, Jun. 1997. [3] J. A. Butts, et al., “Characterizing and Predicting Value Degree of Use,” MICRO-35, pp.15-26, Nov. 2002. [4] J. A. Butts, et al., “Use-Based Register Caching with Decoupled ndexing,” ISCA-31, pp.302-313, Mar. 2004. [5] J. L. Cruz, et al., “Multipule-Banked Register File Architectures,” ISCA, pp.316-325, Jun. 2000. [6] R. Gonzalez, et al., “A Content Aware Integer Register File Organization,” ISCA-31, pp.314324, Mar. 2004. [7] MIPS Technologies, Inc., “Combining Branch Predictors,” WRL Technical Note TN-36, Digital Equipment Corporation, June 1993. [8] S. Vajapeyam, et al., “Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences,” ISCA-24, pp.1-12, Jun. 1997. [9] R. Yung, et al., “Caching Processor General Registers,” ICCD’95, pp.307-312, October 1995.. -6-E −12−.
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