rms 5 kV 4.5-A/9-A IsolatedDual Channel Gate DriverNCP51560

5 kV _rms 4.5-A/9-A Isolated Dual Channel Gate Driver NCP51560

The NCP51560 are isolated dual−channel gate drivers with 4.5−A/9−A source and sink peak current respectively. They are designed for fast switching to drive power MOSFETs, and SiC MOSFET power switches. The NCP51560 offers short and matched propagation delays.

Two independent and 5 kV_rms internal galvanic isolation from input to each output and internal functional isolation between the two output drivers allows a working voltage of up to 1500 V_DC. This driver can be used in any possible configurations of two low side, two high−side switches or a half−bridge driver with programmable dead time.

An ENA/DIS pin shutdowns both outputs simultaneously when set low or high for ENABLE or DISABLE mode respectively.

The NCP51560 offers other important protection functions such as independent under−voltage lockout for both gate drivers and a Dead Time adjustment function

Features

•

Flexible: Dual Low−Side, Dual High−Side or Half−Bridge Gate Driver

•

4.5 A Peak Source, 9 A Peak Sink Output Current Capability

•

Independent UVLO Protections for Both Output Drivers

•

Output Supply Voltage from 6.5 V to 30 V with 5−V and 8−V for MOSFET, 13−V and 17−V UVLO for SiC, Thresholds.

•

Common Mode Transient Immunity CMTI > 200 V/ns

•

Propagation Delay Typical 38 ns with

♦ 5 ns Max Delay Matching per Channel

♦ 5 ns Max Pulse−Width Distortion

•

User Programmable Input Logic

♦ DISABLE Mode

•

User Programmable Dead−Time

•

Isolation & Safety

♦ 5 kVrms Isolation for 1 Minute (per UL1577 Requirements)

♦ 8000 VPK Reinforced Isolation Voltage (per VDE0884−11 Requirements)

♦ CQC Certification per GB4943.1−2011

♦ SGS FIMO Certification per IEC 62386−1

•

These are Pb−Free Devices Typical Applications

•

Motor Drives

•

Isolated Converters in DC−DC and AC−DC Power Supply

•

Server, Telecom, and Industrial Infrastructures

VDD

8 7 6 5 4 3 2 1

SOIC−16 WB CASE 751G−03

PIN ASSIGNMENT

See detailed ordering and shipping information on page 29 of this data sheet.

ORDERING INFORMATION NCP51560 = Specific Device Code

X = A or B or C or D for UVLO Option Y = A or B for ENABLE/DISABLE A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package 16

1

NCP51560 XY

AWLYYWWG

NCP51560

9 10 11 12 13 14 15 16 INA

INB

ENA/DIS

VSSB NC NC OUTA

OUTB VSSA

DT GND

NC VDD

MARKING DIAGRAM

VCCB

VCCA

TYPICAL APPLICATION CIRCUIT

Figure 1. Application Schematic PWMB

ENA PWMA

CONTROLLER GND

To Load HV Rail

16 15 14 13 12 11 10 9 INA

INB

ENA/DIS DT VDD

GND

NC

VDD VSSB

NC NC VCCA OUTA

VCCB OUTB VDD VSSA

VDD

VCC

ENA

GND To Load

HV Rail

16 15 14 13 12 11 10 9 INA

INB

ENA/DIS DT VDD

GND

NC

VDD VSSB

NC NC VCCA OUTA

VCCB OUTB VDD VSSA

VDD

VCC

PWMB PWMA

8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

CONTROLLER

(a) High and Low Side MOSFET Gate Drive for ENABLE Version

(b) High and Low Side MOSFET Gate Drive for DISABLE Version

FUNCTIONAL BLOCK DIAGRAM

INA

INB

Figure 2. Simplified Block Diagram

GND

VCCB VDD

NC

DT OUTB NC ENA/DIS

VDD UVLO

VSSB VCCA

OUTA

VSSA

NC Functional

Isolation LOGIC

DEADTIME CONTROL

Input to Output Isolation

Tx

Tx Rx

Rx INB

INA INA

INB LOGIC

LOGIC UVLO

UVLO INA

(PWM)

INB (NC)

GND

VCCB VDD

NC

DT OUTB ENA/DIS

VDD UVLO

VSSB VCCA

OUTA

VSSA

NC Functional

Isolation LOGIC

DEAD CONTROLTIME

Input to Output Isolation

Tx

Tx Rx

Rx INB

INA

INA

INB LOGIC

LOGIC UVLO

UVLO VDD

(a) For Only ENABLE (NCP51560xA) Version

(b) For Only DISABLE (NCP51560xB) Version

NC

FUNCTIONAL TABLE

INPUT UVLO GATE DRIVE OUTPUT

ENA/DIS (Note 3)

INA INB

Input Side (V_DD)

Output Side

OUTA OUTB

ENABLE DISABLE

Channel A (V_CCA)

Channel B (V_CCB)

X X X X Active X X L L

X X X X X Active Active L L

H L X L Inactive Active Inactive L L

H L X H Inactive Active Inactive L H

H L L X Inactive Inactive Active L L

H L H X Inactive Inactive Active H L

L H X X Inactive Inactive Inactive L L

H L L L Inactive Inactive Inactive L L

H L L H Inactive Inactive Inactive L H

H L H H Inactive Inactive Inactive L (Note 4) L (Note 4)

Inactive Inactive Inactive H (Note 5) H (Note 5) 1. “L” means that LOW, “H” means that HIGH and X: Any Status

2. Inactive means that VDD, VCCA, and VCCB are above UVLO threshold voltage (Normal operation) Active means that UVLO disables the gate driver output stage.

3. Disables both gate drive output when the ENA/DIS pin is LOW in ENABLE version, which is default is HIGH, if this pin is open.

Enables both gate drive output when the ENA/DIS pin is LOW in DISABLE version, which is default is LOW, if this pin is open.

4. DT pin is left open or programmed with RDT. 5. DT pin pulled to V_DD.

PIN CONNECTIONS

Figure 3. Pin Connections – SOIC−16 WB (Top View) VDD

8 7 6 5 4 3 2 1

9 10 11 12 13 14 15 16 INA

INB

ENA/DIS

VSSB NC NC OUTA

OUTB VSSA

DT GND

NC VDD

V_CCA

V_CCB

PIN DESCRIPTION

Pin No. Symbol I/O Description

1 INA Input Logic Input for Channel A with internal pull−down resistor to GND 2 INB Input Logic Input for Channel B with internal pull−down resistor to GND.

3, 8 VDD Power Input−side Supply Voltage.

It is recommended to place a bypass capacitor from V_DD to GND.

4 GND Power Ground Input−side. (all signals on input−side are referenced to this pin)

5 ENA/DIS Input Logic Input High Enables Both Output Channels with Internal pull−up resistor for an ENABLE version. Conversely, Logic Input High disables Both Output Channels with Internal pull−down resistor for the DISABLE version.

6 DT Input Input for programmable Dead−Time

It provides three kind of operating modes according to the DT pin voltage as below.

Mode−A: Cross−conduction both channel outputs is not allowed even though dead−time is less than maximum 20 ns when the DT pin is floating (Open).

Mode−B: Dead−time is adjusted according to an external resistance (RDT).

t_DT (in ns)= 10 x R_DT (in kW)

Recommended dead−time resistor (RDT) values are between 1 kW and 300 kW.

MODE−C: Cross−conduction both channel outputs is allowed when the DT pin pulled to V_DD.

7 NC − No Connection; Keep pin floating.

9 VSSB Power Ground for Channel B

10 OUTB Output Output for Channel B

11 V_CCB Power Supply Voltage for Output Channel B.

It is recommended to place a bypass capacitor from V_CCB to VSSB.

12, 13 NC − No Connection; Keep pin floating

14 VSSA Power Ground for Channel A

15 OUTA Output Output of Channel A

16 VCCA Power Supply Voltage for Output Channel A.

It is recommended to place a bypass capacitor from VCCA to VSSA.

SAFETY AND INSULATION RATINGS

Symbol Parameter Min. Typ. Max. Unit

Installation Classifications per DIN VDE 0110/1.89

Table 1 Rated Mains Voltage < 150 VRMS − I−IV − −

< 300 VRMS I−IV − −

< 450 VRMS I−IV − −

< 600 VRMS I−IV − −

< 1000 VRMS I−III − −

CTI

Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1) 600 − − −

Climatic Classification 40/125/21 − −

Pollution Degree (DIN VDE 0110/1.89) 2 − −

VPR Input*to*Output Test Voltage, Method b, V^IORM × 1.875 = V^PR, 100%

Production Test with tm = 1 s, Partial Discharge < 5 pC 2250 − − V_PK

VIORM Maximum Repetitive Peak Isolation Voltage 1200 − − V_PK

VIOWM Maximum Working Isolation Voltage 1200 − − V_DC

VIOTM Maximum Transient Isolation Voltage 8000 − − V_PK

ECR External Creepage 8.0 − − mm

ECL External Clearance 8.0 − − mm

DTI Insulation Thickness 17.3 − − mm

RIO Insulation Resistance at T_S, VIO = 500 V 10⁹ − − Ω

UL1577

VISO Withstand

isolation voltage VTEST = VISO = 5000 VRMS, t = 60 sec. (qualification),

V_TEST = 1.2×VISO = 6000 V_RMS, t = 1 sec (100% production) 5000 − − V_RMS

SAFETY LIMITING VALUE

Symbol Parameter Test Condition Side Min. Typ. Max. Unit

I_S Safety output supply current

R_θJA = 81 °C/W, VCCA = VCCB = 12 V, T_A = 25°C, TJ = 150°C

See Figure 4

DRIVER A,

DRIVER B − − 61 mA

R_θJA = 81 °C/W, VCCA = VCCB = 25 V, TA = 25°C, TJ = 150°C

See Figure 4

DRIVER A, DRIVER B

− − 29 mA

P_S Safety supply power R_θJA = 81 °C/W, TA = 25°C, TJ = 150°C See Figure 5

INPUT − − 60 mW

DRIVER A − − 720

DRIVER A − − 720

TOTAL − − 1500

TS Safety temperature − − 150 °C

MAXIMUM RATINGS

Symbol Parameter Min Max Unit

V_DD to GND Power Supply Voltage – Input Side (Note 7) −0.3 5.5 V

VCCA – VSSA, VCCB – VSSB Power Supply Voltage – Driver Side (Note 8) −0.3 33 V OUTA to VSSA, OUTB to VSSB Driver Output Voltage (Note 8) −0.3 V_CCA + 0.3,

VCCB + 0.3 V OUTA to VSSA, OUTB to VSSB,

Transient for 200 ns (Note 9) −2 V_CCA + 0.3,

V_CCB + 0.3 V

INA and INB Input Signal Voltages (Note 7) −5 20 V

ENA/DIS Input Signal Voltages (Note 7) −0.3 5.5 V

ENA/DIS Transient for 50ns (Note

9) −5 5.5 V

DT Dead Time Control (Note 7) −0.3 V_DD + 0.3 V

VSSA−VSSB, VSSB−VSSA Channel to Channel Voltage 1500 − V

T_J Junction Temperature −40 +150 °C

T_S Storage Temperature −65 +150 °C

Electrostatic Discharge Capability

HBM (Note 10) Human Body Model − ±2 kV

CDM (Note 10) Charged Device Model − ±1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

6. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters.

7. All voltage values are given with respect to GND pin.

8. All voltage values are given with respect to VSSA or VSSB pin.

9. This parameter verified by design and bench test, not tested in production.

10.This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101) Latch up Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78F.

RECOMMENDED OPERATING CONDITIONS

Symbol Rating Min Max Unit

VDD Power Supply Voltage – Input Side 3.0 5.0 V

VCCA, VCCB Power Supply Voltage – Driver Side 5−V UVLO Version 6.5 30 V

8−V UVLO Version 9.5 30 V

13−V UVLO Version 14.5 30 V

17−V UVLO Version 18.5 30 V

V_IN Logic Input Voltage at Pins INA, and INB 0 18 V

V_ENA/DIS Logic Input Voltage at Pin ENA/DIS 0 5.0 V

T_A Ambient Temperature −40 +125 _C

T_J Junction Temperature −40 +125 _C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

THERMAL CHARACTERISTICS

Symbol Rating Condition Value Unit

R_qJA Thermal Characteristics, (Note 12) Thermal Resistance Junction−Air 16−SOIC−WB

100 mm², 1 oz Copper, 1 Surface Layer (1S0P) 100 mm², 2 oz Copper, 1 Surface Layer (1S0P)

120 81

°C/W

R_qJC Thermal Resistance Junction−Case 100 mm², 1 oz Copper, 1 Surface Layer (1S0P) 38 °C/W

YJT Thermal Resistance Junction−to−Top 18 °C/W

YJB Thermal Resistance Junction−to−Board 55 °C/W

P_D Power Dissipation (Note 12)

16−SOIC−WB 100 mm², 1 oz Copper, 1 Surface Layer (1S0P)

100 mm², 2 oz Copper, 1 Surface Layer (1S0P)

0.8 1.5

W 11. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

12.JEDEC standard: JESD51−2, and JESD51−3.

ISOLATION CHARACTERISTICS

Symbol Parameter Condition Min Typ Max Unit

VISO,INPUT TO OUTPUT

Input to Output Isolation Voltage TA = 25°C, Relative Humidity < 50%, t = 1.0 minute, I_I*O 10 A, 50 Hz (Notes 13, 14, 15)

5000 − − V_RMS

VISO,OUTA TO OUTB

OUTA to OUTB Isolation Voltage 1500 − − V_DC

R_ISO Isolation Resistance V_{I_O} = 500 V (Note 13) 10¹¹ − − Ω

13.Device is considered a two*terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together for input to output isolation test, and pins 9 to 11 are shorted together and pins 14 to 16 are shorted together for between channel isolation test.

14.5,000 V_RMS for 1*minute duration is equivalent to 6,000 VRMS for 1*second duration for input to output isolation test, and Impulse Test > 10 ms; sample tested for between channel isolation test.

15.The input*output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input*output continuous voltage rating. For the continuous working voltage rating, refer to equipment*level safety specification or DIN VDE V 0884*11 Safety and Insulation Ratings Table

ELECTRICAL CHARACTERISTICS (VDD = 5 V, VCCA = VCCB = 12 V, or 20 V (Note 17)and VSSA= VSSB, for typical values TJ = TA = 25°C, for min/max values TJ = −40°C to +125°C, unless otherwise specified. (Note 16)

Symbol Parameter Condition Min Typ Max Unit

PRIMARY POWER SUPPLY SECTION (V_DD)

I_QVDD V_DD Quiescent Current VINA= VINB = 0 V, VENABLE = VDD

or V_DISABLE = 0 V 500 780 1000 mA

V_INA= V_INB = 5 V, V_ENABLE = 0 V

or V_DISABLE = V_DD 500 820 1000 mA

VINA = VINB = 5 V, VENABLE = VDD

or V_DISABLE = 0 V 7 12 16 mA

I_VDD V_DD Operating Current f_IN = 500 kHz, 50% duty cycle,

COUT = 100 pF 5.0 7.15 9.0 mA

V_DDUV+ V_DD Supply Under−Voltage Positive−Going

Threshold V_DD = Sweep 2.7 2.8 2.9 V

V_DDUV− V_DD Supply Under−Voltage Negative−Going

Threshold V_DD = Sweep 2.6 2.7 2.8 V

V_DDHYS V_DD Supply Under−Voltage Lockout Hysteresis V_DD = Sweep − 0.1 − V

SECONDARY POWER SUPPLY SECTION (V_CCA AND V_CCB) I_QVCCA

IQVCCB

V_CCA and V_CCB Quiescent Current V_INA = V_INB = 0 V, per channel 200 280 500 mA V_INA = V_INB = 5 V, per channel 300 410 600 mA I_VCCA

IVCCB

V_CCA and V_CCB Operating Current Current per channel (f_IN = 500 kHz,

50% duty cycle), COUT = 100 pF 2.0 3.0 5.5 mA VCCA and VCCB UVLO THRESHOLD (5−V UVLO VERSION)

V_CCAUV+

V_CCBUV+ V_CCA and V_CCB Supply Under−Voltage

Positive−Going Threshold 5.7 6.0 6.3 V

VCCAUV−

V_CCBUV− VCCA and VCCB Supply Under−Voltage

Negative−Going Threshold 5.4 5.7 6.0 V

VCCHYS Under−Voltage Lockout Hysteresis − 0.3 − V

t_UVFLT Under−Voltage Debounce Time (Note 18) − − 10 ms

VCCA and VCCB UVLO THRESHOLD (8−V UVLO VERSION) V_CCAUV+

V_CCBUV+ V_CCA and V_CCB Supply Under−Voltage

Positive−Going Threshold 8.3 8.7 9.2 V

V_CCAUV−

V_CCBUV− V_CCA and V_CCB Supply Under−Voltage

Negative−Going Threshold 7.8 8.2 8.7 V

V_CCHYS Under−Voltage Lockout Hysteresis − 0.5 − V

t_UVFLT Under−Voltage Debounce Time (Note 18) − − 10 ms

VCCA and VCCB UVLO THRESHOLD (13−V UVLO VERSION) VCCAUV+

V_CCBUV+ VCCA and VCCB Supply Under−Voltage

Positive−Going Threshold 12 13 14 V

V_CCAUV−

VCCBUV−

V_CCA and V_CCB Supply Under−Voltage

Negative−Going Threshold 11 12 13 V

V_CCHYS Under−Voltage Lockout Hysteresis − 1 − V

t_UVFLT Under−Voltage Debounce Time (Note 18) − − 10 ms

VCCA and VCCB UVLO THRESHOLD (17−V UVLO VERSION) V_CCAUV+

V_CCBUV+ V_CCA and V_CCB Supply Under−Voltage

Positive−Going Threshold 16 17 18 V

V_CCAUV−

V_CCBUV− V_CCA and V_CCB Supply Under−Voltage

Negative−Going Threshold 15 16 17 V

VCCHYS Under−Voltage Lockout Hysteresis − 1 − V

t_UVFLT Under−Voltage Debounce Time (Note 18) − − 10 ms

LOGIC INPUT SECTION (INA, AND INB)

V_INH High Level Input Voltage 1.4 1.6 1.8 V

VINL Low Level Input Voltage 0.9 1.1 1.3 V

ELECTRICAL CHARACTERISTICS (VDD = 5 V, VCCA = VCCB = 12 V, or 20 V (Note 17)and VSSA= VSSB, for typical values TJ = TA = 25°C, for min/max values TJ = −40°C to +125°C, unless otherwise specified. (Note 16) (continued)

Symbol Parameter Condition Min Typ Max Unit

LOGIC INPUT SECTION (INA, AND INB)

VINHYS Input Logic Hysteresis − 0.5 − V

I_IN+ High Level Logic Input Bias Current V_IN = 5 V 20 25 33 mA

IIN− Low Level Logic Input Bias Current VIN = 0 V − − 1.0 mA

R_IN Logic Input Pull−Down Resistance 150 200 250 kW

LOGIC INPUT SECTION (for ENABLE Version only)

V_ENAH Enable High Voltage 1.4 1.6 1.8 V

VENAL Enable Low Voltage 0.9 1.1 1.3 V

V_ENAHYS Enable Logic Hysteresis − 0.5 − V

LOGIC INPUT SECTION (for DISABLE Version only)

V_DISH Disable High Voltage 1.4 1.6 1.8 V

VDISL Disable Low Voltage 0.9 1.1 1.3 V

V_DISHYS Disable Logic Hysteresis − 0.5 − V

DEAD−TIME AND OVERLAP SECTION

t_DT,MIN Minimum Dead−Time DT pin is left open 0 10 29 ns

t_DT Dead−Time R_DT = 20 kW 145 200 255 ns

R_DT = 100 kW 800 1000 1200 ns

DtDT Dead−Time Mismatch between OUTB → OUTA

and OUTA → OUTB R_DT = 20 kW −30 − 30 ns

R_DT = 100 kW −150 − 150 ns

V_DT,SHORT DT Threshold Voltage for OUTA & OUTB

Overlap 0.85x

VDD

0.9xV_DD 0.95x VDD

V GATE DRIVE SECTION

I_OUTA+,

I_OUTB+ OUTA and OUTB Source Peak Current

(Note 18) V_INA = V_INB = 5 V, PW ≤ 5 ms 2.6 4.5 − A

I_OUTA−,

I_OUTB− OUTA and OUTB Sink Peak Current (Note 18) V_INA = V_INB = 0 V, PW ≤ 5 ms 7.0 9.0 − A

ROH Output Resistance at High State IOUTH = 100 mA − 1.4 2.7 W

R_OL Output Resistance at Low State I_OUTL = 100 mA − 0.5 1.0 W

VOHA, VOHB High Level Output Voltage (VCCX − VOUTX) IOUT = 100 mA − − 270 mV V_OLA, V_OLB Low Level Output Voltage (V_OUTX − V_SSX) I_OUT = 100 mA − − 100 mV DYNAMIC ELECTRICAL CHARACTERISTICS

tPDON Turn−On Propagation Delay from INx to OUTx VCCA = V_CCB = 12 V, C_LOAD = 0 nF 24 38 57 ns V_CCA = V_CCB = 20 V, C_LOAD = 0 nF 27 41 60 ns t_PDOFF Turn−Off Propagation Delay from INx to OUTx V_CCA = V_CCB = 12 V, C_LOAD = 0 nF 24 38 57 ns V_CCA = V_CCB = 20 V, C_LOAD = 0 nF 27 41 60 ns

t_PWD Pulse Width Distortion (t_PDON – t_PDOFF) −5 − 5 ns

t_DM Propagation Delay Mismatching between

Channels INA and INB shorted,

fIN = 100 kHz −5 − 5 ns

tVPOR to OUT Power−up Delay from the V_POR to Output

(Note 18) See the Figure 52 − 18 − ms

tR Turn−On Rise Time V_CCA = V_CCB = 12 V,

C_LOAD = 1.8 nF − 9 16 ns

V_CCA = V_CCB = 20 V,

C_LOAD = 1.8 nF − 11 19 ns

tF Turn−Off Fall Time V_CCA = V_CCB = 12 V,

CLOAD = 1.8 nF − 8 16 ns

V_CCA = V_CCB = 20 V,

C_LOAD = 1.8 nF − 10 19 ns

ELECTRICAL CHARACTERISTICS (VDD = 5 V, VCCA = VCCB = 12 V, or 20 V (Note 17)and VSSA= VSSB, for typical values TJ = TA = 25°C, for min/max values TJ = −40°C to +125°C, unless otherwise specified. (Note 16) (continued)

Symbol Parameter Condition Min Typ Max Unit

DYNAMIC ELECTRICAL CHARACTERISTICS TENABLE,OUT,

TDISABLE,OUT

ENABLE or DISABLE to OUTx Turn−On/Off

Propagation Delay VCCA = VCCB = 12 V 24 38 57 ns

V_CCA = V_CCB = 20 V 27 41 60 ns

t_PW Minimum Input Pulse Width that Change

Output State C_LOAD = 0 nF − 15 30 ns

CMTI Common Mode Transient Immunity

(Note 18) Slew rate of GND versus VSSA

and VSSB. INA and INB both are tied to V_DD or GND. V_CM = 1500 V

200 − − V/ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

16.Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T_J = T_A = 25°C.

17.V_CCA = V_CCB = 12 V is used for the test condition of 8−V UVLO, V_CCA = V_CCB = 20 V is used for 17−V UVLO.

18.These parameters are verified by bench test only and not tested in production.

INSULATION CHARACTERISTICS CURVES

Figure 4. Thermal Derating Curve for Safety−related Limiting Current (Current in Each Channel with

Both Channels Running Simultaneously)

Figure 5. Thermal Derating Curve for Safety−related Limiting Power

TYPICAL CHARACTERISTIC

Figure 6. Quiescent V_DD Supply Current vs. Temperature (V_DD = 5 V, INA = INB = 0 V, ENA/DIS = 5 V or,

INA = INB = 5 V, ENA/DIS = 0 V and No Load)

Figure 7. Quiescent V_DD Supply Current vs.

Temperature (V_DD = 5 V,

INA = INB = ENA/DIS = 5 V and No Load)

Figure 8. V_DD Operating Current vs.

Temperature (V_DD = 5 V, No Load, and Switching Frequency = 500 kHz)

Figure 9. V_DD Operating Current vs.

Temperature (V_DD = 5 V, No Load, and Different Switching Frequency)

Figure 10. Per Channel V_DD Operating Current vs.

Temperature (V_DD = 5 V, No Load, and Different Switching Frequency

Figure 11. Per Channel Quiescent V_CC Supply Current vs. Temperature (INA = INB = 0 V or 5 V, ENA/DIS = 5 V

and No Load

TYPICAL CHARACTERISTIC (Continued)

Figure 12. Per Channel V_CC Operating Current vs. Temperature (No Load and

Switching Frequency = 500 kHz

Figure 13. Per Channel Operating Current vs.

Frequency (No Load, V_CCA = V_CCB = 12 V, or 25 V)

Figure 14. Per Channel Operating Current vs.

Frequency (C_LOAD = 1 nF, V_CCA = V_CCB = 12 V, or 25 V) Figure 15. Per Channel Operating Current vs.

Frequency (C_LOAD = 1.8 nF, V_CCA = V_CCB = 12 V, or 25 V)

Figure 16. Per Channel V_CC Quiescent Current vs.

V_CC Supply Voltage (INA = INB = 0 V, ENA = 5 V) Figure 17. Per Channel V_CC Quiescent Current vs.

V_CC Supply Voltage (INA = INB = 5 V, ENA = 5 V)

TYPICAL CHARACTERISTIC (Continued)

Figure 18. V_DD UVLO Threshold vs. Temperature Figure 19. V_DD UVLO Hysteresis vs. Temperature

Figure 20. V_CC 5−V UVLO Threshold vs. Temperature Figure 21. V_CC 5−V UVLO Hysteresis vs. Temperature

Figure 22. V_CC 8−V UVLO Threshold vs. Temperature Figure 23. V_CC 8−V UVLO Hysteresis vs. Temperature

TYPICAL CHARACTERISTIC (Continued)

Figure 24. V_CC 13−V UVLO Threshold vs. Temperature Figure 25. V_CC 13−V UVLO Hysteresis vs. Temperature

Figure 26. V_CC 17−V UVLO Threshold vs. Temperature Figure 27. V_CC 17−V UVLO Hysteresis vs. Temperature

Figure 28. Output Current vs. V_CC Supply Voltage Figure 29. ENA/DIS Delay Time vs. Temperature

Figure 30. Input Logic Threshold vs. Temperature (INA, and INB)

Figure 31. Input Logic Hysteresis vs. Temperature (INA, and INB)

Figure 32. ENA/DIS Threshold vs. Temperature

(ENABLE, and DISABLE) Figure 33. ENA/DIS Hysteresis vs. Temperature (ENABLE, and DISABLE)

Figure 34. Rise/Fall Time vs. Temperature (C_LOAD = 1.8 nF)

Figure 35. Rise/Fall Time vs. Temperature (V_CC = V_CCB = 12 V, and Different Load)

TYPICAL CHARACTERISTIC (Continued)

Figure 36. Dead Time vs. Temperature

(R_DT = Open) Figure 37. Dead Time vs. Temperature (R_DT = 100kW)

Figure 38. Dead Time Mismatching vs. Temperature Figure 39. Dead Time vs. R_DT

Figure 40. Turn−on Propagation Delay vs.

Temperature Figure 41. Turn−off Propagation Delay vs.

Temperature

TYPICAL CHARACTERISTIC (Continued)

Figure 42. Pulse Width Distortion vs. Temperature Figure 43. Propagation Delay Matching vs.

Temperature

Figure 44. Turn−on Propagation Delay vs. V_CC

Supply Voltage Figure 45. Turn−off Propagation Delay vs. V_CC Supply Voltage

PARAMETER MEASUREMENT DEFINITION Switching Time Definitions

Figure 46 shows the switching time definitions of the turn−on (tPDON) and turn−off (tPDOFF) propagation delay time among the driver’s two input signals INA, INB and two

output signals OUTA, OUTB. The typical values of the propagation delay (t_PDON, T_PDOFF), pulse width distortion (t_PWD) and delay matching between channels times are specified in the electrical characteristics table.

Figure 46. Switching Time Definitions VINH

90%

VINL

tPDON

10% 10%

90%

OUTA (OUTB) INA (INB)

tR tF

tPDOFF

Enable and Disable Function

Figure 47 shows the response time according to an ENABLE or the DISABLE operating modes. If the ENA/DIS pin voltage goes to LOW state, i.e. VENA ≤ 1.1 V shuts down both outputs simultaneously and Pull the ENA/DIS pin HIGH (or left open), i.e. V_ENA ≥ 1.6 V to

operate normally in an ENABLE mode as shown in Figure 47 (a). Conversely, if the ENA/DIS pin voltage goes to HIGH state, i.e. V_DIS ≥ 1.6 V shuts down both outputs simultaneously and Pull the ENA/DIS pin LOW (or left open), i.e. VDIS≤ 1.1 V operate normally in the DISABLE mode as shown in Figure 47 (b).

Figure 47. Timing Chart of Enable and Disable Function (OUTB)OUTA

(DISABLE) (INB)INA

DISABLE high response time 90%

10%

V_INH VDISH

DISABLE low response time (OUTB)OUTA

(ENABLE) (INB)INA

ENABLE low response time 90%

10%

V_ENAH VENAL

ENABLE high response time

(a) ENABLE Version

(b) DISABLE Version ENA/DIS

ENA/DIS

Programmable Dead−Time

Dead time is automatically inserted whenever the dead time of the external two input signals (between INA and INB signals) is shorter than internal setting dead times (DT1 and

DT2). Otherwise, if the external input signal dead times are larger than internal dead− time, the dead time is not modified by the gate driver and internal dead−time definition as shown in Figure 48.

Figure 48. Internal Dead−Time Definitions OUTA

INA

90%

10%

90%

10%

INB

OUTB

DT1 DT2

Figure 49 shows the definition of internal dead time and shoot−through prevention when input signals applied at same time.

Figure 49. Internal Dead−Time Definitions

INA INB

OUTA OUTB

Case − A

Shoot−Through Prevention DT

DT

Case−B Case−C Case−C Case−E

DT DT DT DT DT DT DT DT

Dead − Time

Shoot−Through Prevention Gate Driver Output OFF VDT

Timer_Cap TRIG_INA TRIG_INB

Case – A : Control signal edges overlapped, but inside the dead−time (Dead−Time) Case – B : Control signal edges overlapped, but outside the dead−time (Shoot−Through) Case – C : Control signal edges synchronous (Dead−Time)

Case – D : Control signal edges not overlapped, but inside the dead−time (Dead−Time ) Case – E : Control signal edges not overlapped, but outside the dead−time (Direct Drive)

DEVICE INFORMATION Input to Output Operation Definitions

The NCP51560 provides important protection functions such as independent under−voltage lockout for both gate driver; enable or disable function and dead−time control function. Figure 50 shows an overall input to output timing diagram when shutdown mode via ENA/DIS pin in the

CASE−A, and Under−Voltage Lockout protection on the primary− and secondary−sides power supplies events in the CASE−B. The gate driver output (OUTA and OUTB) were turn−off when cross−conduction event at the dead time control mode in the CASE−C.

Figure 50. Overall Operating Waveforms Definitions at the Dead−Time Control Mode A

INA

VDD

UVLO OUTA

VDDUV−

INB

ENA/DIS

OUTB

Shutdown

B

DT DT Shoot−Through

Prevention C

(VCCA, VCCB)

VDDUV+

(ENABLE)

ENA/DIS (DISABLE)

Shutdown

Input and Output Logic Table

Table 1 shows an input to output logic table according to the dead time control modes and an enable or the disable operation mode.

Table 1. INPUT AND OUTPUT LOGIC TABLE

INPUT OUTPUT

NOTE

INA INB

ENA/DIS

OUTA OUTB

ENABLE DISABLE

L L H or Left open L or Left open L L Programmable dead time control with RDT.

L H H or Left open L or Left open L H

H L H or Left open L or Left open H L

H H H or Left open L or Left open L L DT pin is left open Or programmed with R_DT.

H H H or Left open L or Left open H H DT pin pulled to V_DD.

Left open Left open H or Left open L or Left open L L

X X L H L L

19.“X” means L, H or left open.

PROTECTION FUNCTION

The NCP51560 provides the protection features include enable or disable function, Cross Conduction Protection, and Under−Voltage Lockout (UVLO) of power supplies on primary−side (V_DD), and secondary−side both channels (V_CCA, and V_CCB).

Under−Voltage Lockout Protection V_DD and V_CCx The NCP51560 provides the Under−Voltage Lockout (UVLO) protection function for VDD in primary−side and both gate drive output for VCCA and VCCB in secondary−side as shown in Figure 51.

The gate driver is running when the VDD supply voltage is greater than the specified under−voltage lockout threshold voltage (e.g. typically 2.8 V) and ENA/DIS pin is HIGH or LOW states for an ENABLE (e.g. NCP51560xA) or the DISABLE (e.g. NCP51560xB) mode respectively.

In addition, both gate output drivers have independent under voltage lockout protection (UVLO) function and each

channel supply voltages in secondary−side (e.g. VCCA, and VCCB) need to be greater than specified UVLO threshold level in secondary−side to let the output operate per input signal. The typical VCCx UVLO threshold voltage levels for each option are per below Table 2.

Table 2. V_CCx UVLO OPTION TABLE

Option V_CC UVLO Level Unit

5−V 6.0 V

8−V 8.7 V

13−V 13 V

17−V 17 V

UVLO protection has an hysteresis to provide immunity to short VCC drops that can occur.

Figure 51. Timing Chart Under−Voltage Lockout Protection

Power−Up VCC UVLO Delay to OUTPUT

To provide a variety of Under−Voltage Lockout (UVLO) thresholds NCP51560 has a power−up delay time during initial V_CCX start−up or after POR event.

Before the gate driver is ready to deliver a proper output state, there is a power−up delay time from the V_CC

power−on reset (POR) threshold to output and it is defined as tVPOR to OUT. (e.g. typically 18 ms). Figure 52 shows the power−up UVLO delay time diagram for V_CC.

Figure 52. Timing VCC Power−Up UVLO Delay Time Cross−Conduction Prevention and Allowed

Overlapped Operation

The cross conduction prevents both high− and low−side switches from conducting at the same time when the dead time (DT) control mode is in half−bridge type, as shown in Figure 53.

For full topologies flexibility, cross conduction can be allowed both high− and low−side switches conduct at the same time when the DT pin is pulled to V_DD for example, as shown in Figure 54.

Figure 53. Concept of Shoot−Through Prevention Figure 54. Concept of Allowed the Shoot−Through

OUTB OUTA

After DT Shoot−Through

Prevent INA

INB

Example A

Example B Shoot−Through

Prevent

DT DT

DT DT

Always LOW

Shoot−Through Prevent

OUTB OUTA INA INB

OUTB OUTA

Allowed Overlap Operation INA

INB

Example A

Example B (a) In case of Shoot−Through OUTB

OUTA INA INB

Allowed Overlap Operation

(b) In case of Shoot−Through less than DT longer than DT (a) In case of Shoot−Through (b) In case of Shoot−Through

less than DT longer than DT

(a) In case of Shoot−Through (b) In case of Shoot−Through less than DT longer than DT (a) In case of Shoot−Through (b) In case of Shoot−Through

less than DT longer than DT