NTB45N06L, NTBV45N06L MOSFET – Power, N-Channel, Logic Level, D

MOSFET – Power,

N-Channel, Logic Level, D ² PAK

45 A, 60 V, 28 m W

Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits.

Features

• Higher Current Rating

• ^{Lower R}

• ^{Lower V}

• Lower Capacitances

• Lower Total Gate Charge

• ^{Tighter V}

Specification

• Lower Diode Reverse Recovery Time

• Lower Reverse Recovery Stored Charge

• AEC−Q101 Qualified and PPAP Capable − NTBV45N06L

• These Devices are Pb−Free and are RoHS Compliant

• Power Supplies

• ^Converters

• Power Motor Controls

• Bridge Circuits

45 AMPERES, 60 VOLTS R

= 28 mW

N−Channel D

S G

http://onsemi.com

MARKING DIAGRAM

& PIN ASSIGNMENT1

NTx 45N06LG AYWW

1

Gate 3

Source 4

Drain

2 Drain

1 2

3

4

D²PAK CASE 418B

STYLE 2

MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−to−Source Voltage VDSS 60 Vdc

Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc

Gate−to−Source Voltage

− Continuous

− Non−Repetitive (tpv10 ms) VGS

VGS

"15

"20

Vdc

Drain Current

− Continuous @ TA = 25°C

− Continuous @ TA = 100°C

− Single Pulse (t_pv10 ms)

ID

ID

IDM

45 30 150

Adc Apk Total Power Dissipation @ T_A = 25°C

Derate above 25°C

Total Power Dissipation @ T_A = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2)

P_D 125

0.83 3.2 2.4

W W/°CW

W

Operating and Storage Temperature Range TJ, Tstg −55 to +175 °C

Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (V_DD = 50 Vdc, V_GS = 5.0 Vdc, L = 0.3 mH

IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 W)

EAS 240 mJ

Thermal Resistance

− Junction−to−Case

− Junction−to−Ambient (Note 1)

− Junction−to−Ambient (Note 2)

R_qJC R_qJA R_qJA

1.2 46.8 63.2

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds T_L 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in²).

2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in²).

ORDERING INFORMATION

Device Package Shipping^†

NTB45N06LG D²PAK

(Pb−Free) 50 Units / Rail

NTB45N06LT4G D²PAK

(Pb−Free) 800 / Tape & Reel

NTBV45N06LT4G D²PAK

(Pb−Free) 800 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

ELECTRICAL CHARACTERISTICS(T_J = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Note 3) (V_GS = 0 Vdc, I_D = 250 mAdc)

Temperature Coefficient (Positive)

V_(BR)DSS 60

− 67

67.2 −

−

Vdc mV/°C Zero Gate Voltage Drain Current

(V_DS = 60 Vdc, V_GS = 0 Vdc)

(V_DS = 60 Vdc, V_GS = 0 Vdc, T_J = 150°C)

IDSS

−

− −

− 1.0

10

mAdc

Gate−Body Leakage Current (V_GS = ±15 Vdc, VDS = 0 Vdc) I_GSS − − ±100 nAdc ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage (Note 4) (V_DS = V_GS, I_D = 250 mAdc)

Threshold Temperature Coefficient (Negative)

V_GS(th)

1.0

− 1.8

4.7 2.0

−

Vdc mV/°C Static Drain−to−Source On−Resistance (Note 4)

(V_GS = 5.0 Vdc, I_D = 22.5 Adc) R_DS(on)

− 23 28 mW

Static Drain−to−Source On−Voltage (Note 4) (V_GS = 5.0 Vdc, I_D = 45 Adc)

(V_GS = 5.0 Vdc, I_D = 22.5 Adc, T_J = 150°C)

V_DS(on)

−

− 1.03

0.93 1.51

−

Vdc

Forward Transconductance (Note 4) (VDS = 8.0 Vdc, ID = 12 Adc) gFS − 22.8 − mhos DYNAMIC CHARACTERISTICS

Input Capacitance

(V_DS = 25 Vdc, V_GS = 0 Vdc, f = 1.0 MHz)

Ciss − 1212 1700 pF

Output Capacitance Coss − 352 480

Transfer Capacitance Crss − 90 180

SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time

(V_DD = 30 Vdc, I_D = 45 Adc, V_GS = 5.0 Vdc, R_G = 9.1 W) (Note 4)

t_d(on) − 13 30 ns

Rise Time t_r − 341 680

Turn−Off Delay Time t_d(off) − 36 75

Fall Time t_f − 158 320

Gate Charge

(V_DS = 48 Vdc, I_D = 45 Adc, VGS = 5.0 Vdc) (Note 4)

Q_T − 23 32 nC

Q₁ − 4.6 −

Q₂ − 14.1 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (IS = 45 Adc, VGS = 0 Vdc) (Note 4)

(I_S = 45 Adc, V_GS = 0 Vdc, T_J = 150°C) VSD −

− 1.01

0.92 1.15

− Vdc

Reverse Recovery Time

(I_S = 45 Adc, V_GS = 0 Vdc, dI_S/dt = 100 A/ms) (Note 4)

t_rr − 56 − ns

t_a − 30 −

tb − 26 −

Reverse Recovery Stored Charge QRR − 0.09 − mC

2 1.8

1.4 1.6

1.2

1 100

1000 10000 0

50

4 20

2 1

V_DS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

0

V_GS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

ID, DRAIN CURRENT (AMPS)

0 0.038 0.034 0.03

40 30 20 0.026

0.022 0.018 0.014

10 50 80

Figure 3. On−Resistance vs. Gate−to−Source Voltage

I_D, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance vs. Drain Current and Gate Voltage

I_D, DRAIN CURRENT (AMPS) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) IDSS, LEAKAGE (nA)

80

1.8 2.6 3.4 4.2 5 5.8

0 10 20 30 40 50 80

3 10

30 40

V_GS = 8 V V_GS = 7 V

V_GS = 6 V V_GS = 5.5 V

V_GS = 5 V

V_GS = 4 V

V_GS = 3.5 V

V_DS > = 10 V

TJ = 25°C

T_J = −55°C T_J = 100°C

V_GS = 10 V V_GS = 5 V V_GS = 5 V

VGS = 0 V ID = 22.5 A

VGS = 5 V 60

70

50

20

0 80

10 30 40 60 70

0.042 0.046

0.038 0.034 0.03 0.026 0.022 0.018 0.042 0.046

60 70

0.8

V_GS = 4.5 V

V_GS = 9 V VGS = 10 V

T_J = 25°C

T_J = −55°C T_J = 100°C

60 70

T_J = 150°C

T_J = 100°C T_J = 125°C

0

ID = 45 A T_J = 25°C

V_GS Q2

Q1

QT

VGS

1000

100

10 1000

100

10

6 5 4 3 2 1 0

280

200 48 40 32 24

0 10

3600

2800

10 2400

2000

15

5 20

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

1600 1200 800 400

0 5

Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and

Drain−to−Source Voltage vs. Total Charge VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 9. Resistive Switching Time Variation vs. Gate Resistance

R_G, GATE RESISTANCE (W)

Figure 10. Diode Forward Voltage vs. Current VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS)

t, TIME (ns) −TO−SOURCE

25 0 4 8 12 16 20 24

1 10 100 0.6 0.64 0.68 0.72 0.76 0.88 0.92 1

V_GS = 0 V

V_DS = 0 V T_J = 25°C

C_rss C_iss

Coss

C_rss

16 8

0.8 0.84 Ciss

V_GS = 15 V SINGLE PULSE T_C = 25°C

V_DS = 30 V I_D = 45 A V_GS = 5 V

V_GS = 0 V T_J = 25°C

I_D = 45 A

10 ms 1 ms dc

t_r

t_d(off)

t_d(on) t_f VDS

3200

0.96

120 160 240 4000

0.00001 0.0001 0.001 0.01 0.1 1 10 1

0.1

0.01

r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)

t, TIME (s)

Figure 13. Thermal Response Normalized to R_qJC at Steady State

10

0.01

ANCE (NORMALIZED)

1

0.1

Normalized to R_qJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in², 3 x 3 inch FR4 board

D²PAK 3 CASE 418B−04

ISSUE L

DATE 17 FEB 2015 SCALE 1:1

STYLE 1:

PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

STYLE 2:

PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN

STYLE 3:

PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE SEATING

PLANE

S

G

D

−T−

0.13 (0.005)M T

2 3

1 4

3 PL

K

J H

EV C

A

DIM MININCHESMAX MILLIMETERSMIN MAX A 0.340 0.380 8.64 9.65 B 0.380 0.405 9.65 10.29 C 0.160 0.190 4.06 4.83 D 0.020 0.035 0.51 0.89 E 0.045 0.055 1.14 1.40

G 0.100 BSC 2.54 BSC

H 0.080 0.110 2.03 2.79 J 0.018 0.025 0.46 0.64 K 0.090 0.110 2.29 2.79

S 0.575 0.625 14.60 15.88 V 0.045 0.055 1.14 1.40

−B−

B M

STYLE 4:

PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

W

W

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04.

F 0.310 0.350 7.87 8.89

L 0.052 0.072 1.32 1.83 M 0.280 0.320 7.11 8.13

N 0.197 REF 5.00 REF

P 0.079 REF 2.00 REF

R 0.039 REF 0.99 REF

M

L

F

M

L

F

M

L

F VARIABLE

CONFIGURATION

ZONE R N P

U

VIEW W−W VIEW W−W VIEW W−W

1 2 3

STYLE 5:

PIN 1. CATHODE 2. ANODE 3. CATHODE 4. ANODE

MARKING INFORMATION AND FOOTPRINT ON PAGE 2

STYLE 6:

PIN 1. NO CONNECT 2. CATHODE 3. ANODE 4. CATHODE

xx xxxxxxxxx AWLYWWG

GENERIC MARKING DIAGRAM*

xx = Specific Device Code A = Assembly Location WL = Wafer Lot

Y = Year

WW = Work Week G = Pb−Free Package AKA = Polarity Indicator

IC Standard

xxxxxxxxG AYWW

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

ISSUE L

DATE 17 FEB 2015

8.38

5.080

DIMENSIONS: MILLIMETERS

PITCH

2X

16.155

1.016^2X

10.49

3.504 Rectifier

AYWW xxxxxxxxG AKA