LDO Regulator, Low Noise (8 mVRMS

38 V, 150 mA

NCP731

The NCP731 device is based on unique combination of features – very low noise, low quiescent current, fast transient response and high input and output voltage ranges. The NCP731 is CMOS LDO regulator designed for up to 38 V input voltage and 150 mA output current. Very low noise (8 m V

) makes this device an ideal solution for application where clean voltage rails are critical for system performance (power operational amplifiers, analog−to−digital / digital−to−analog converters and other precision analog circuitry).

Internal short circuit and over temperature protections saves the device against overload conditions.

Features

• Operating Input Voltage Range: 2.7 V to 38 V

• Output Voltage Adjustable Range: 1.2 V to 35 V

• Fixed Output Voltage Versions: 3.3 V and 5.0 V (other voltage versions on request)

• Very Low Noise: 8 m V

(10 Hz to 100 kHz)

• Low Quiescent Current: 48 m A typ.

• Low Shutdown Current: 100 nA typ.

• Low Dropout: 290 mV typ. at 150 mA

• Output Voltage Accuracy ± 0.6% (25 ° C)

• Programmable Soft Start Circuit

• Stable with Small 1 m F Ceramic Capacitors

• Over−Current and Thermal Shutdown Protections

• Available in Micro−8 EP Package

• Device is Pb−Free and RoHS Compliant

• Supply Rails for OpAmps, ADCs, DACs and other Precision Analog Circuitry and Audio

• Post DC−DC Converter Regulation and Ripple Filtering

• Test and Measurement

• Industrial Instrumentation

• ^Metering

• Battery Powered Devices

MSOP8 EP 3x3 CASE 846AT

MARKING DIAGRAM

See detailed ordering and shipping information on page 14 of this data sheet.

ORDERING INFORMATION XXXX = Specific Device Code A = Assembly Location Y = Year

W = Work Week ZZ = Assembly Lot Code

XXXXXX AYWZZ

Figure 1. Adjustable Output Voltage Application

1.2 V NCP731A

ADJ

IN OUT

GND NC SS

EN OFF NC

ON

ADJ/FF

CFF 10 nF (optional)

COUT 1 mF

VIN = 6 − 38 V VOUT = 5 V

C_SS 10 nF (optional) CIN

1 mF R1

85.5 k

R₂ 27 k

Notes:

Blue objects are valid for ADJ version only Green objects are valid for FIX version only Black objects are common for all version Figure 2. Fixed Output Voltage Application

NCP731A FIX−5.0V

IN OUT

GND NC SS

EN OFF NC

ON

ADJ/FF

CFF 10 nF (optional)

COUT 1 mF

V_IN = 6 − 38 V V_OUT = 5 V

C_SS 10 nF (optional) CIN 1 mF

ADJ/FF

Figure 3. Internal Block Diagram

Notes:

Blue objects are valid for ADJ version only Green objects are valid for FIX version only The rest valid for both versions

Figure 4. Pin Assignments EA

IN

EN

OUT

GND

0.9 V

THERMAL SHUTDOWN

V−REFERENCE

&

SOFT−START

EN_Int EN Comp.

SS

2.6 V UVLO_Int

UVLO Comp.

ADJ/FF

NC NC

TSD_Int LOGIC

UVLO_Int

OUT

NC GND

IN NC SS EN 1

2 3 4

8 7 6 5 EP Micro−8 EP

(GND)

VREF 1.2 V

VFB = 1.2 V

R_ADJ2 R_ADJ1

IOUT Sense VINT

ISS

PIN DESCRIPTION

Pin Number Pin Name Description

8 IN Power supply input pin.

4 GND Ground pin.

1 OUT LDO output pin.

5 EN Enable input pin (high = enable, low = disable). If this pin is not needed it should be conned to IN pin.

No internal pull−up or pull−down circuit is present.

2 ADJ/FF ADJ version – pin is ADJ

• Adjust input pin. Could be connected directly or by the resistor divider to the output pin.

FIX versions – pin is FF

• Feed forward capacitor pin. Could be connected by C_FF capacitor to OUT pin for better dynamic performance & lower noise or left unconnected.

3, 7 NC Not internally connected. Could be left unconnected or connected to GND.

6 SS Soft−start input pin. Connect a C_SS capacitor to set soft−start time. Could be left floating if not used.

EP EPAD Exposed pad, must be connected to GND.

OUT Voltage ADJ Version and

FIX Versions with V_OUT−NOM > 6.0 V V_OUT −0.3 to [(VIN + 0.3) or 40;

whichever is lower] V FIX Versions with V_OUT−NOM≤6.0 V −0.3 to [(V_IN + 0.3) or 7;

whichever is lower]

EN Voltage V_EN −0.3 to (V_IN + 0.3) V

ADJ/FF Voltage V_ADJ −0.3 to 5.5 V

SS Voltage V_SS −0.3 to 5.5 V

Output Current I_OUT Internally limited mA

Maximum Junction Temperature T_J(MAX) 150 °C

Storage Temperature T_STG −55 to 150 °C

ESD Capability, Human Body Model (Note 2) ESD_HBM 2000 V

ESD Capability, Charged Device Model (Note 2) ESD_CDM 1000 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.

2. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per ANSI/ESDA/JEDEC JS-001, EIA/JESD22-A114 ESD Charged Device Model tested per ANSI/ESDA/JEDEC JS-002, EIA/JESD22-C101

Table 2. THERMAL CHARACTERISTICS (Note 3)

Characteristic Symbol Value Unit

Thermal Resistance, Junction-to-Air R_qJA 44 °C/W

Thermal Resistance, Junction-to-Case (top) R_qJCt 99 °C/W

Thermal Resistance, Junction-to-Case (bottom) R_qJCb 19 °C/W

Thermal Characterization Parameter, Junction-to-Case (top) YJCt 12 °C/W

Thermal Characterization Parameter, Junction-to-Board [FEM] YJB 16 °C/W

3. Measured according to JEDEC board specification (board 2S2P, Cu layer thickness 1 oz, Cu area 645mm², no airflow). Detailed description of the board can be found in JESD51−7.

Table 3. ELECTRICAL CHARACTERISTICS V_IN = V_OUT−NOM + 1 V and V_IN ≥ 2.7 V, VEN = 1.2 V, I_OUT = 1 mA, C_IN = C_OUT = 1.0mF (Note 4), CSS = 0 nF, CFF = 0 nF, TJ = −40°C to 125°C, ADJ tied to OUT, unless otherwise specified.

Parameter Test Conditions Symbol Min Typ Max Unit

Recommended Input Voltage VIN 2.7 − 38 V

Output Voltage Accuracy (Note 5) T_J = +25°C VOUT −0.6 − 0.6 %

V_IN = V_OUT−NOM + 1 V to 38 V I_OUT = 0.1 mA to 150 mA T_J = −40°C to +85°C

−1.0 − 1.0

VIN = VOUT−NOM + 1 V to 38 V I_OUT = 0.1 mA to 150 mA T_J = −40°C to +125°C

−1.5 − 1.5

Output Voltage Range (Note 6) VOUT−ADJ VADJ − 35 V

ADJ Reference Voltage (Note 6) V_ADJ − 1.2 − V

ADJ Input Current (Note 6) V_ADJ = 1.2 V I_ADJ −0.05 0.01 0.05 mA

Quiescent Current VIN = VOUT−NOM + 1 V to 38 V, IOUT = 0 mA IQ − 48 100 mA

Ground Current I_OUT = 150 mA I_GND − 400 − mA

Shutdown Current VEN = 0 V, VIN = 38 V ISHDN − 0.07 1.0 mA

Output Current Limit V_OUT = V_OUT−NOM − 100 mV I_OLIM 210 295 450 mA

Short Circuit Current V_OUT = 0 V I_OSC 210 365 450 mA

Dropout Voltage (Note 7) I_OUT = 150 mA VDO − 230 480 mV

Power Supply Ripple Rejection V_IN = V_OUT−NOM + 2 V

IOUT = 10 mA 10 Hz PSRR − 80 − dB

10 kHz − 70 −

100 kHz − 42 −

1 MHz − 48 −

Output Noise Voltage f = 10 Hz to 100 kHz, ADJ version, VOUT = VADJ

VN − 8.1 − mV^RMS

f = 10 Hz to 100 kHz, ADJ version, VOUT = 3.3 V, CFF = 10 nF, R1 = 47.3 kW, R₂ = 27 kW

V_N − 15 −

f = 10 Hz to 100 kHz, ADJ version, VOUT = 5 V, CFF = 10 nF, R1 = 85.5 kW, R₂ = 27 kW

V_N − 20 −

EN Threshold V_EN rising V_EN−TH 0.7 0.9 1.1 V

EN Hysteresis V_EN falling V_EN−HY 0.02 0.1 0.2 V

EN Input Current V_EN = 30 V, V_IN = 30 V IEN −1 0.15 1 mA

Internal UVLO Threshold V_IN voltage rising V_UVLO−TH 2.43 2.55 2.69 V

Internal UVLO Hysteresis VIN voltage falling VUVLO−HY 0.01 0.04 0.07 V

SS Charging Current V_SS = 0 V I_SS − 910 − nA

SS High Voltage SS pin floating V_SS−HI − 2.4 − V

SS Time (Note 8) C_SS = 10 nF t_SS−10nF − 14 − ms

C_SS not connected t_SS−0nF − 0.5 −

Thermal Shutdown Temperature Temperature rising from TJ = +25°C TTSD − 170 − °C

Thermal Shutdown Hysteresis Temperature falling from TSD T_TSDH − 10 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Effective capacitance, including the effect of DC bias, tolerance and temperature. See the Application Information section for more information.

5. Output voltage accuracy of ADJ version is guaranteed when ADJ pin is connected to OUT pin. The V_OUT−NOM is then equal to V_ADJ. 6. Applicable only to ADJ version.

7. Dropout voltage is measured when the output voltage falls 100 mV below the nominal output voltage. ADJ version is measured with ADJ pin connected to resistor divider which sets VOUT to 5.0 V. Limits are valid for all voltage versions.

8. Startup time is the time from EN assertion to point when output voltage is equal to 95% of V_OUT−NOM.

Figure 5. Output Voltage vs. Temperature Figure 6. Load Regulations

Figure 7. Ground Current vs. Load Figure 8. Quiescent Current vs. Temperature

Figure 9. Shutdown Current vs. Temperature Figure 10. ADJ Input Current vs. Temperature T_J, JUNCTION TEMPERATURE (°C)

VOUT, OUTPUT VOLTAGE (V)

I_OUT, OUTPUT CURRENT (mA)

IOUT, LOAD CURRENT (mA) IGND, GROUND CURRENT (mA)

TJ, JUNCTION TEMPERATURE (°C) IQ, QUIESCENT CURRENT (mA)

−40 −20 0 20 40 60 80 100 120 140 VIN = 38 V IOUT = 0 mA

−40 −20 0 20 40 60 80 100 120 140 T_J, JUNCTION TEMPERATURE (°C)

ISHDN, SHUTDOWN CURRENT (mA)

T_J, JUNCTION TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120 140 ADJ appl.

2.0%

1.5%

1.0%

0.5%

0.0%

−0.5%

−1.0%

−1.5%

−2.0%

−40 −20 0 20 40 60 80 100 120 140

−0.3%

−0.2%

−0.1%

0.0%

0.1%

0.2%

0.3%

0 50 100 150

T_A = 125°C TA = 25°C T_A = −40°C

DVOUT, OUTPUT VOLTAGE CHANGE (%)

0 50 100 150 200 250 300 350

0.01 0.1 1 10 100 0

10 20 30 40 50 60 70 80 90 100

110 High Limit

VIN = 38 V VEN = 0 V 0.0

0.2 0.4 0.6 0.8 1.0 1.2

High Limit

IADJ, INPUT CURRRENT (nA)

−60

−50

−40

−30

−20

−10 0 10 20 30 40 50

60 High Limit

Low Limit

TYPICAL CHARACTERISTICS

V_IN = V_OUT−NOM + 1 V and V_IN ≥ 2.7 V, VEN = 1.2 V, I_OUT = 1 mA, C_IN = C_OUT = 1.0 mF (effective), CSS = 10 nF, C_FF = 10 nF, R_ADJ1 = 85.5 kW, RADJ2 = 27 kW (RADJx applicable to ADJ application only), T_J = −40°C to 125°C, all output voltage versions, unless

otherwise specified.

Figure 11. Enable Threshold Voltage vs.

Temperature Figure 12. Enable Hysteresis vs. Temperature

Figure 13. Enable Input Current vs.

Temperature

Figure 14. Dropout Voltage vs. Temperature

Figure 15. Dropout Voltage vs. I_OUT Figure 16. Maximum Output Current vs.

Temperature T_J, JUNCTION TEMPERATURE (°C)

VEN−TH, THRESHOLD VOLTAGE (V)

T_J, JUNCTION TEMPERATURE (°C)

T_J, JUNCTION TEMPERATURE (°C) IEN, EN INPUT CURRENT (mA)

T_J, JUNCTION TEMPERATURE (°C) VDROP, DROPOUT VOLTAGE (mV)

−40 −20 0 20 40 60 80 100 120 140 All V_OUT versions

V_OUT = V_OUT−NOM − 100 mV I_OUT = 150 mA

I_OUT, OUTPUT CURRENT (mA) VDO, DROPOUT VOLTAGE (mV)

T_J, JUNCTION TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120 140

−40 −20 0 20 40 60 80 100 120 140 VOUT = 1.2 V V_OUT = 3.3 V

VOUT = 5.0 V

VEN−HY, EN HYSTERESIS (mV)

High Limit

High Limit

IOUT, OUTPUT CURRENT (mA)

High Limit

Low Limit

−40 −20 0 20 40 60 80 100 120 140

−40 −20 0 20 40 60 80 100 120 140 0.65

0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10

1.15 High Limit

Low Limit

0 20 40 60 80 100 120 140 160 180 200 220

VEN rising VEN falling

High Limit

Low Limit VOUT = 3.3 V V_OUT = 5.0 V

V_OUT = 1.2 V

−1.25

−1.00

−0.75

−0.50

−0.25 0.00 0.25 0.50 0.75 1.00 1.25

VIN = 30 V V_EN = 30 V High Limit

Low Limit

150 200 250 300 350 400 450 500

All V_OUT versions

V_OUT = V_OUT−NOM − 100 mV

0 50 100 150 200 250 300 350 400 450 500

0 20 40 60 80 100 120 140 160

−40°C 0°C 25°C55°C 85°C100°C 125°C

150 200 250 300 350 400 450 500

VOUT−FORCED − 0 V Short Circuit

Current Limit V_OUT−FORCED = V_NOM − 0.1 V

FREQUENCY (Hz) FREQUENCY (Hz)

NOISE (mV√(Hz))

FREQUENCY (Hz)

NOISE (mV√(Hz))

FREQUENCY (Hz)

FREQUENCY (Hz)

NOISE (mV√(Hz))

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

1

0.1

0.01

0.001

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

1

0.1

0.01

0.001

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

1

0.1

0.01

0.001

Figure 17. V_OUT Noise Density vs. V_OUT Figure 18. V_OUT Noise Density vs. V_IN

Figure 19. V_OUT Noise Density vs. C_OUT Figure 20. V_OUT Noise Density vs. I_OUT

Figure 21. V_OUT Noise Density vs. Part−type

and I_OUT Figure 22. V_OUT Noise Density vs. C_FF

TYPICAL CHARACTERISTICS

V_IN = V_OUT−NOM + 1 V and V_IN ≥ 2.7 V, VEN = 1.2 V, I_OUT = 1 mA, C_IN = C_OUT = 1.0 mF (effective), CSS = 10 nF, C_FF = 10 nF, R_ADJ1 = 85.5 kW, RADJ2 = 27 kW (RADJx applicable to ADJ application only), T_J = −40°C to 125°C, all output voltage versions, unless

otherwise specified.

Figure 23. V_OUT Noise Density vs. Part−type

and C_FF Figure 24. PSRR vs. Part−type

Figure 25. PSRR vs. C_OUT (6.0 V, 150 mA) Figure 26. PSRR vs. C_OUT (7.5 V, 50 mA)

Figure 27. PSRR vs. C_OUT Package Size Figure 28. PSRR vs. C_FF FREQUENCY (Hz)

PSRR (dB)

FREQUENCY (Hz)

PSRR (dB) PSRR (dB)

FREQUENCY (Hz)

FREQUENCY (Hz)

PSRR (dB) PSRR (dB)

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M

110

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

100 90 80 70 60 50 40 30 20 10 0

110 100 90 80 70 60 50 40 30 20 10 0

110 100 90 80 70 60 50 40 30 20 10 0 110

100 90 80 70 60 50 40 30 20 10 0

110 100 90 80 70 60 50 40 30 20 10 0

ADJ−5V FIX−5V

V_OUT = 5 V IOUT = 150 mA C_OUT = 10 mF

ADJ appl.

VIN = 6 V VOUT = 5 V IOUT = 150 mA

Co = 1 mF−0805 Co = 2.2 mF−0805 Co = 4.7 mF−1206 Co = 10 mF−1206 Co = 22 mF−1206 Co = 100 mF−1210

Co = 1 mF−0805 Co = 2.2 mF−0805 Co = 4.7 mF−1206 Co = 10 mF−1210

ADJ appl.

V_IN = 7.5 V V_OUT = 5 V I_OUT = 50 mA

Co = 10 mF−0603 Co = 10 mF−0805 Co = 10 mF−1206 Co = 10 mF−1210

FIX appl.

VOUT = 5 V IOUT = 150 mA

Cff = 0n Cff = 100p Cff = 1n Cff = 3n3 Cff = 10n Cff = 100n

ADJ appl.

VIN = 6 V V_OUT = 5 V COUT = 1 mF IOUT = 50 mA

Figure 29. PSRR vs. V_IN (50 mA, 1 mF) Figure 30. PSRR vs. V_IN (150 mA, 1 mF)

Figure 31. PSRR vs. V_IN (50 mA, 10 mF) Figure 32. PSRR vs. V_IN (150 mA, 10 mF)

Figure 33. Load Transient Response (ADJ−5V, V_IN = 6.0 V, C_OUT = 1 mF)

Figure 34. Load Transient Response (ADJ−5V, V_IN = 35.0 V, C_OUT = 1 mF) FREQUENCY (Hz)

NOISE (mV√(Hz))

FREQUENCY (Hz)

PSRR (dB)

FREQUENCY (Hz)

PSRR (dB) PSRR (dB)

FREQUENCY (Hz)

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

110

10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M

100 90 80 70 60 50 40 30 20 10 0

110 100 90 80 70 60 50 40 30 20 10 0 110

100 90 80 70 60 50 40 30 20 10 0

ADJ appl.

V_IN = 5 V V_OUT = 10 V I_OUT = 150 mA 110

100 90 80 70 60 50 40 30 20 10 0

Vi = 6.0 V Vi = 7.5 V Vi = 9.0 V Vi = 12.0 V

ADJ appl VOUT = 5 V C_OUT = 1 mF I_OUT = 50 mA

Vi = 6.0 V Vi = 7.5 V Vi = 9.0 V Vi = 12.0 V

ADJ appl VOUT = 5 V C_OUT = 1 mF I_OUT = 150 mA

ADJ appl VOUT = 5 V C_OUT = 10 mF I_OUT = 150 mA

Vi = 6.0 V Vi = 6.5 V Vi = 7.0 V Vi = 7.5 V Vi = 9.0 V Vi = 12.0 V Vi = 24.0 V

Vi = 6.0 V Vi = 6.5 V Vi = 7.0 V Vi = 7.5 V Vi = 9.0 V Vi = 12.0 V

C1: VIN 1V/div C2: V_out(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−27mV

+15mV 1mA

IOUT

VOUT

VIN

6.0V

5.0V

C1: VIN 5V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−26mV

+15mV 1mA

IOUT

VOUT

VIN

35.0V

5.0V

ADJ−5V appl.

C_OUT = 1 mF ADJ−5V appl.

COUT = 1 mF

10ms/div 10ms/div

TYPICAL CHARACTERISTICS

V_IN = V_OUT−NOM + 1 V and V_IN ≥ 2.7 V, VEN = 1.2 V, I_OUT = 1 mA, C_IN = C_OUT = 1.0 mF (effective), CSS = 10 nF, C_FF = 10 nF, R_ADJ1 = 85.5 kW, RADJ2 = 27 kW (RADJx applicable to ADJ application only), T_J = −40°C to 125°C, all output voltage versions, unless

otherwise specified.

Figure 35. Load Transient Response

(ADJ−5V, V_IN = 6.0 V, C_OUT = 10 mF) Figure 36. Load Transient Response (ADJ−5V, V_IN = 6.0 V, C_OUT = 100 mF)

C1: VIN 1V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−24mV

+13mV 1mA

IOUT

VOUT

VIN

6.0V

C1: VIN 1.0V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−14mV

+9mV 1mA

IOUT

VOUT

VIN

6.0V

C1: VIN 1V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−29mV

+16mV 0mA

IOUT

VOUT

VIN

6.0V

C1: VIN 1V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−32mV

+19mV

0mA IOUT

VOUT

VIN

5.5V

Worst case conditions:

− IOUTstarts from 0mA

− VINis minimal (near dropout)

− COUTis minimal

C1: VIN 1V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−32mV

+16mV 0mA

IOUT

VOUT

VIN

6.0V

C1: VIN 1V/div C2: VOUT(ac) 20mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

1mA IOUT

VOUT

VIN

6.0V

5.0V 5.0V

5.0V 5.0V

5.0V

5.0V

−32mV@CFF=100p

−26mV@CFF=1nF−100nF

−100mV@CFF=NA

Figure 37. Load Transient Response (V_IN = 6.0 V, I_OUT = 0 − 150 mA)

Figure 38. Load Trans. Response

(V_IN = 5.5 V, I_OUT = 0 − 150 mA ~ Worst Conditions)

Figure 39. Load Transient Response

(FIX−5V, V_IN = 6.0 V, C_OUT = 1 mF) Figure 40. Load Transient Response (ADJ−5V, C_FF = variable) ADJ−5V appl.

C_OUT = 10 mF

20ms/div

ADJ−5V appl.

C_OUT = 100 mF

100ms/div

ADJ−5V appl.

C_OUT = 1 mF

10ms/div

ADJ−5V appl.

C_OUT = 1 mF

10ms/div

FIX−5V appl.

C_OUT = 1 mF C_FF = 10 nF 10ms/div

ADJ−5V appl.

C_OUT = 1 mF

10ms/div

C1: VIN 1V/div C2: VOUT(ac) 10mV/div C4: IOUT 100mA/div

150mA tR=tF=1μs

−32mV

+16mV

0mA IOUT

VOUT

VIN

4.3V

3.3V

C1: VIN 1V/div C2: VOUT(ac) 2mV/div

+6.0mV +5.6mV

VOUT

VIN

6.5V

5.0V

5.5V tR=tF=1μs

−6.0mV

−3.8mV

C1: VIN 1V/div C2: VOUT(ac) 2mV/div

+4.6mV +4.6mV

VOUT

VIN

7.0V

5.0V

6.0V tR=tF=1μs

−3.8mV

−1.8mV

C1: VIN 1V/div C2: VOUT(ac) 2mV/div

+1.4mV +1.6mV VOUT

VIN

8.0V

5.0V

7.0V tR=tF=1μs

−1.6mV −0.8mV

C1: VIN 10V/div C2: VOUT(ac) 5mV/div

+7.0mV +6.5mV

VOUT

VIN

30.0V

5.0V 6.0V

−5.0mV −2.0mV

−7.0mV tR=tF=12μs (2V/μs)

C1: VIN 10V/div C2: VOUT 1V/div C4: IOUT 200mA/div

0mA IOUT

VOUT

VIN

5.0V 38V

Short applied, the peak is caused by COUTdischarging Output current limited by LDO

Short released

Figure 41. Load Transient Response (FIX−3.3V, V_IN = 4.3 V, C_OUT = 1 mF)

Figure 42. Line Transient Response (V_OUT = 5.0 V, V_IN = 5.5 – 6.5 V)

Figure 43. Line Transient Response (V_OUT = 5.0 V, V_IN = 6.0 – 7.0 V)

Figure 44. Line Transient Response (V_OUT = 5.0 V, V_IN = 7.0 − 8.0 V)

Figure 45. Line Transient Response

(V_OUT = 5.0 V, V_IN = 6.0 – 30.0 V) Figure 46. Short Circuit (1 ms) FIX−3.3V appl.

C_OUT = 1 mF

10ms/div

FIX−5V appl.

RLOAD = 100 W

5ms/div

FIX−5V appl.

R_LOAD = 100 W

5ms/div

FIX−5V appl.

R_LOAD = 100 W

5ms/div

ADJ−5V appl.

1ms/div 5ms/div

FIX−5V appl.

R_LOAD = 100 W

TYPICAL CHARACTERISTICS

V_IN = V_OUT−NOM + 1 V and V_IN ≥ 2.7 V, VEN = 1.2 V, I_OUT = 1 mA, C_IN = C_OUT = 1.0 mF (effective), CSS = 10 nF, C_FF = 10 nF, R_ADJ1 = 85.5 kW, RADJ2 = 27 kW (RADJx applicable to ADJ application only), T_J = −40°C to 125°C, all output voltage versions, unless

otherwise specified.

Figure 47. Short Circuit (250 ms) Figure 48. Startup by V_IN (ADJ−5V, C_SS = 0 nF)

Figure 49. Startup by V_IN (ADJ−5V, C_SS = 1 nF) Figure 50. Startup by V_IN (ADJ−5V, C_SS = 10 nF)

Figure 51. Startup by V_IN (ADJ−5V, C_SS = 100 nF) Figure 52. Startup by V_IN (FIX−5 V, C_SS = 0 nF) ADJ−5V appl.

2ms/div 5ms/div

2ms/div 50ms/div

Short applied, the peak is caused by COUTdischarging

0mA IOUT

VOUT

5.0V

Output current limited by LDO

Short released

Thermal shutdown cycling

VIN

38V

C1: VIN=VEN 5V/div C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

C1: VIN=VEN 5V/div C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

C1: VIN=VEN 5V/div C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

C1: VIN=VEN 5V/div C2: VOUT 2V/div C3: VFF 1V/div C4: VSS 1V/div C4: VSS 1V/div

ADJ−5V appl.

R_LOAD = 500 W C_SS = 0 nF

ADJ−5V appl.

R_LOAD = 500 W C_SS = 1 nF

ADJ−5V appl.

R_LOAD = 500 W C_SS = 10 nF

ADJ−5V appl.

RLOAD = 500 W CSS = 100 nF

FIX−5V appl.

RLOAD = 500 W CSS = 0 nF C1: VIN 10V/div

C2: VOUT 1V/div C4: IOUT 200mA/div

50ms/div ^{C1: VIN=VEN 5V/div} C2: VOUT 2V/div C3: VADJ 1V/div

500ms/div

Figure 53. Startup by V_IN (FIX−5V, C_SS = 10 nF)

Figure 54. Startup/Shutdown by V_IN (Slow Rising Edge)

Figure 55. Startup/Shutdown by V_EN (Fast Rising Edge)

Figure 56. Startup/Shutdown by V_EN (Slow Rising Edge)

FIX3.3V appl.

C_OUT = 1 mF

10 ms/div 5 ms/div

FIX5V appl.

R_LOAD = 100 W

5 ms/div 5 ms/div

C1: VIN=VEN 5V/div C2: VOUT 2V/div C3: VFF 1V/div C4: VSS 1V/div

C1: VEN 2V/div C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

C1: VEN 1V/div C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

~160μs

VEN−TH~ 0.9V

VADJcopies VSSuntil reaches regulation level (1.2V)

VOUTfollows VFBwith gain given by RADJ1, RADJ2

VEN−TH– VEN−HY~ 0.8V C1: VIN=VEN 2V/div

C2: VOUT 2V/div C3: VADJ 1V/div C4: VSS 1V/div

VUVLO−TH~ 2.4V

VADJcopies VSSuntil reaches regulation level (1.2V)

VOUTfollows VFBwith gain given by RADJ1, RADJ2

VUVLO−TH– VUVLO−HY~ 2.35V

20ms/div

FIX−5V appl.

R_LOAD = 500 W C_SS = 10 nF

ADJ−5V appl.

RLOAD = 500 W CSS = 10 nF CFF = 10 nF

10ms/div

ADJ−5V appl.

R_LOAD = 500 W C_SS = 0 nF CFF = 0 nF

ADJ−5V appl.

RLOAD = 500 W CSS = 10 nF C_FF = 10 nF

200ms/div 10ms/div

ORDERING INFORMATION

Part Number Marking Voltage Option (V_OUT−NOM) Package Shipping^†

NCP731ADN330R2G 731A33 FIX, 3.3 V

MSOP8 EP

(Pb−Free) 3000 / Tape & Reel

NCP731ADN500R2G 731A50 FIX, 5.0 V

NCP731ADNADJR2G 731AAD ADJ, 1.2 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

DATE 01 OCT 2020

XXXX = Specific Device Code A = Assembly Location Y = Year

W = Work Week ZZ = Assembly Lot Code

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

GENERIC MARKING DIAGRAM*

XXXXXX AYWZZ

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

98AON25934H DOCUMENT NUMBER:

DESCRIPTION:

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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 MSOP8 EP 3x3

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