A-7-6 Investigation Study of Inner-cell Bit-Parallel Multiplier over GF(2m) Using Secure Adiabatic Logic Style

(1)

Title

A-7-6 Investigation Study of Inner-cell Bit-Parallel Multiplier

over GF(2m) Using Secure Adiabatic Logic Style( 本文(Fulltext)

)

Author(s)

MONTEIRO, Cancio; TAKAHASHI, Yasuhiro; SEKINE,

_Toshikazu

Citation

[電子情報通信学会ソサイエティ大会講演論文集] vol.[2012]

_{p.[116]-[116]}

Issue Date

2012-08-28

Rights

copyright 2012 IEICE

Version

出版社版 (publisher version) postprint

URL

http://hdl.handle.net/20.500.12099/53117

(2)

Institute of Electronics, Information, and Communication Engineers

NII-Electronic Library Service Institute ofElectionics, InEoimation, and CommunicationEngineeis

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A-7-6

Investigation

Study

of

over

CF(2M)

Using

Cancio

Monteiroi

Inner-cell

Bit-Parallel

Multiplier

Secure

Adiabatic

Logic

Style

Yhsuhiro

Takahashi2

Tbshikazu

Sekine2

Graduate

School

of

Engineering,

Gifu

UniversityiFaculty

of

Engineering,

Gifu

University2

Abstract

This

paper

investigates

the

logic

security of

inner

cell

bit-parallel

multiplier ever GF{2M) using secure logicstyles. We

evaluate the

logic

ability forresistance _againstDPA attack

from

the viewpeintof instarrtaneoussupply current regarding tothe

possible

input

transitions.

The

investigationresults using our

proposed

logic

has

itsability forDPA attack compare to other

investigated

adiabatic

logic,

and is more _power eMcient in

com-parisentewell-known conyentional secure TDPL logicstyle.

1 Introduction

Differential

power

anaiysis

(DPA)

attacks are

the

most

_popular

t)rpe

of

_power

analysis attacks to re

veal

the

secret

information

in

cryptosystem, such as smart card.

A

DPA

attack seeks

to

crack

the

secret

kay

of a smart card

by

statistically analyzing

_pffwer

fiuctuations

that

occurs while

the

device

encrypts and

decrypts

large

blocks

of

data.

Apart

from

DPA

at-tack,

electromagnetic radiation

ai;tack

(DEMA)

and other side-channel attacks on cryptographic

hardware

has

been

ext;ensively studied.

DEMA

attack

described

that,

current

flow

during

the

switching of the

CMOS

gates

causes a variation of

the

electro-magnetic

field

surrounding

the

chip

that

can

be

monitored

by

induc-tive

_probes

which ame

_particularly

sensitive

to

the

re

lated

impulse.

Hence,

we are encouraged

to

design

a robust secure

logic

for

those

aforementioned attacks

for

application

in

advanced encryption standards

(AES)

hardware

aJchitecture

targeted

for

smart card.

Ar.ti-21i-21cC,-bJ]B-IJ. ff-IJ-/]C/4./JS ts)A-.b,tt A/Att) B[,.1,i.l) )ch-]JtSt/'t,J)t-ts./ i.l)dHLOS-LJ)At,.u.

Fig.

1 Investigation

of

inner

cell

(a)

A-cell

circuit,

(b)

B-cell

circuit.

Thble

1 Simulation

and calcu]ation results

for

B-ce11

circuit and

bit-ptirallel

cellular multiplier over

aF(24),

tb) GF(2

₎

using A-oe11

t

y

m

ptse Emtn J 337･15 311･64 310･28 3957･84 Etna= es 628.92 18.25 350.74 4112.35 E fJ 506.78 382.02 333.86 4042.54 aE fJ 95.42 31.02 11.1540.77 o50.6S25,4911.543.76 NSD18.83.123.32LOI CF(2'uslngB-cell EminJ345.7D318.1232.01892.S7 ETTza=f842.gD427.27435.56053.52 E fJ 592.63 396.04 392.11 3943.42 oE 142.56 34.25 32.21 44.47 NED 58.98 25.55 21.48 3.96 NSD o 24.06 8.658.471.12

2 Simulation

and results

XNle

investigate

our

_proposed

logic

[1]

with ether

previously

published

secure

logic

styles

[2]-[4]

in

bit-parallel

cellular multiplies over

GF(2M)

using

SPICE

simulation with a

O,18

_pam,

1.8 V

standard

CMOS

_pr"

cess

technology.

The

comparison of

inner

cell

cellu-1ar

multiplier

is

depicted

in

Fig.

1 [5].

The

evalua-tion

logics

are

investigated

under

the

same

frequency

operation:

the

_power

supplies of

adiabatic

logics

are

al1

trapezoidal

waveform,

_power

clock

frequency

is

12.5MHz,

and

inverter

input

frequency

are set

to

6.25 MHz

for

al1

instigated

logics.

We

calculate the normalived energy

deviation

(NED)

and normalized standard

deviation

(NSD)

of

bit-parallel

multiplier using

A-oell

and

B-cell

separately as shown

in

feble

1,

The

merit of

NED

and

NSD

is

to

measure

the

ability of

the

logic

against

_power

anal-ysis

attabk.

The

more smal1 value of

NES

and

NSD,

the

consumed energy

is

more constant

foT

different

in-put

transition.

Observing

the

[fable

1,

our

_proposed

logic

is

suitahle

for

A-cell

circuit

in

bit-parallel

cellular

multiplier over

CF(2M)

for

AES

hardware

architecture

design,3

Conclusion

The

inve$tigation

and comparison results show

that

our

_proposed

logic

in

A-cell

circuit structure

has

abil-ity

for

DPA

and

DEMA

attacks,

because

it

balances

the

transitional

currant

traces

and

]owers

_peak

supply

current values

36-times

small compare

to

the

corrvenr

tional

TDPL

logic

style.

The

_power

analysis model and the complete

logic

implementation

using our

_proposed

logic

for

AES

architecture

in

smart card are

addressed

in

future

work.

Rmferences

[1]

C. Monteiro, Y. [rhlahashiand T. Sekine,``Acomparisen of

cellular multiplier cell using secure adiabatic logics,"inProc.

ITC-CSCad12,

Sapporo,

Jul.

15-18,2e12

(aooepted).

[2]

M. Khatir, and A. Meradi, "Secure adiabaticlogic:A

energy DPA-resistant logicstyle," inIA(]R EPrint arthive

(Available

URL:

http:!leprint,iacr,org12oo8f123).

[3]

B.-D.

Choi,

K.E.

Kim,

K-S.

Chung,

and

D.K.

Kim,

metric adiabatic

logic

circuits against

differential

pcrwer

ysis,"inE7111IJournag vol, 32,no. 1,_pp. 166-168, Fbb,

2010.[4]

M. Bucci,L.

_Giancane,

R. Luzzi and

A.

1[tfiletti,

phase

dual-rai1

_pre-charge

logic,"

inPrec.

caEs'oa

LNcs,

vol. 4249,_pp. 232-241, 2006.

[5]

C,-H.

Liu,

N.-F.

Huang,

and

C.-Y,

Lee,

"Computation of

AB2 Trniltiplier inGF{2M) nsing an eMcient lowrcomplexity

cellular architecture,"

in

IEI(]E

71uns.

Fitndamentats.,

vol.

E83-A,

no, 12,pp.

2657-2663,

Dec.

2000.

201219111--14

esthM

116 (zaes

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