D45C12 (PNP), D44C12 (NPN) Complementary Silicon Power Transistor

(1)

October, 2011 − Rev. 3 1 Publication Order Number:

D45C12/D

D45C12 (PNP), D44C12 (NPN)

Complementary Silicon Power Transistor

The D45C12 and D44C12 are for general purpose driver or medium power output stages in CW or switching applications.

Features

• Low Collector−Emitter Saturation Voltage − 0.5 V (Max)

• ^{High f} t for Good Frequency Response

• Low Leakage Current

• Pb−Free Packages are Available*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎÎÎÎÎÎÎÎÎ

Rating

^ÎÎÎ

ÎÎÎ

Symbol

^ÎÎÎÎÎ

ÎÎÎÎÎ

Value

^ÎÎ

ÎÎ

Unit

Collector−Emitter Voltage

^ÎÎÎ

ÎÎÎ

V

_CEO^ÎÎÎÎÎ

ÎÎÎÎÎ

80

^ÎÎ

ÎÎ

Vdc

Collector−Emitter Voltage

^ÎÎÎ

ÎÎÎ

VCES

^ÎÎÎÎÎ

ÎÎÎÎÎ

90

^ÎÎ

ÎÎ

Vdc

Emitter Base Voltage

^ÎÎÎ

ÎÎÎ

V

_EB^ÎÎÎÎÎ

ÎÎÎÎÎ

5.0

^ÎÎ

ÎÎ

Vdc

Collector Current − Continuous Peak (Note 1)

ÎÎÎ

I

_C^ÎÎÎÎÎ

ÎÎÎÎÎ

4.0 6.0

ÎÎ

Adc

Total Power Dissipation @ T

_C

= 25°C Total Power Dissipation @ T

_A

= 25°C

ÎÎÎ

P

_DÎÎÎÎÎ ÎÎÎÎÎ

30 1.67

ÎÎ

W W/°C

Operating and Storage Junction Temperature Range

ÎÎÎ

T

_J

, T

_stg

ÎÎÎÎÎ

−55 to 150

ÎÎ

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

THERMAL CHARACTERISTICS

Characteristic

^ÎÎÎ

ÎÎÎ

Symbol

^ÎÎÎÎÎ

ÎÎÎÎÎ

Max

^ÎÎ

ÎÎ

Unit

Thermal Resistance, Junction−to−Case

ÎÎÎ

R

_qJC^ÎÎÎÎÎ

ÎÎÎÎÎ

4.2

^ÎÎ

ÎÎ

° C/W

Thermal Resistance, Junction−to−Ambient

ÎÎÎ

R

_qJA^ÎÎÎÎÎ

ÎÎÎÎÎ

75

ÎÎ

° C/W

Maximum Lead Temperature for Soldering Purposes: 1/8 in from Case for 5 Sec

ÎÎÎ

T

_L

ÎÎÎÎÎ

275

ÎÎ

°C 1. Pulse Width v 6.0 ms, Duty Cycle v 50%.

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

D4xC12G AYWW 1

Base 3

Emitter 4

Collector

2 Collector

4.0 AMPERE COMPLEMENTARY SILICON POWER

TRANSISTORS 80 VOLTS

TO−220AB CASE 221A STYLE 1 1 2

3 4

MARKING DIAGRAM

& PIN ASSIGNMENT

x = 4 or 5

A = Assembly Location

Y = Year

WW = Work Week G = Pb−Free Package

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

(2)

D45C12 (PNP), D44C12 (NPN)

http://onsemi.com 2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (T

J

= 25°C unless otherwise noted)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Unit

DC Current Gain

(V

_CE

= 1.0 Vdc, I

_C

= 0.2 Adc) (V

CE

= 1.0 Vdc, I

C

= 1.0 Adc) (V

CE

= 1.0 Vdc, I

C

= 2.0 Adc)

ÎÎÎÎ

h

_FE ^ÎÎÎÎ

ÎÎÎÎ

40 20 20

ÎÎÎÎ

120 −

−

ÎÎÎ

−

ELECTRICAL CHARACTERISTICS (T

_C

= 25°C unless otherwise noted)

Characteristic

^ÎÎÎÎ

ÎÎÎÎ

Symbol

^ÎÎÎ

ÎÎÎ

Min

^ÎÎÎ

ÎÎÎ

Typ

^ÎÎÎ

ÎÎÎ

Max

^ÎÎÎ

ÎÎÎ

Unit

OFF CHARACTERISTICS

Collector Cutoff Current (V

CE

= Rated V

CES

, V

BE

= 0)

ÎÎÎÎ

I

CES

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

0.1

ÎÎÎ

mA

Emitter Cutoff Current (V

_EB

= 5.0 Vdc)

ÎÎÎÎ

I

_EBO

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

10

ÎÎÎ

mA

ON CHARACTERISTICS

Collector−Emitter Saturation Voltage (I

_C

= 1.0 Adc, I

_B

= 50 mAdc)

^ÎÎÎÎ

ÎÎÎÎ

V

_CE(sat)^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

0.135

^ÎÎÎ

ÎÎÎ

0.5

^ÎÎÎ

ÎÎÎ

Vdc

Base−Emitter Saturation Voltage (I

_C

= 1.0 Adc, I

_B

= 100 mAdc)

^ÎÎÎÎ

ÎÎÎÎ

V

_BE(sat)^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

0.85

^ÎÎÎ

ÎÎÎ

1.3

^ÎÎÎ

ÎÎÎ

Vdc

DYNAMIC CHARACTERISTICS

Collector Capacitance (V

_CB

= 10 Vdc, f = 1.0 MHz)

^ÎÎÎÎ

ÎÎÎÎ

C

_cb ^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

125

^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

pF

Gain Bandwidth Product (I

_C

= 20 mA, V

_CE

= 4.0 Vdc, f = 20 MHz)

^ÎÎÎÎ

ÎÎÎÎ

f

_T ^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

40

^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

MHz

SWITCHING TIMES

Delay and Rise Times (I

_C

= 1.0 Adc, I

_B1

= 0.1 Adc)

ÎÎÎÎ

t

_d

+ t

_r

ÎÎÎ

−

ÎÎÎ

50

ÎÎÎ

75

ÎÎÎ

ns

Storage Time (I

_C

= 1.0 Adc, I

_B1

= I

_B2

= 0.1 Adc)

ÎÎÎÎ

t

_s ÎÎÎ

ÎÎÎ

−

ÎÎÎ

350

ÎÎÎ

550

ÎÎÎ

ns

Fall Time (I

_C

= 1.0 Adc, I

_B1

= I

_B2

= 0.1 Adc)

^ÎÎÎÎ

ÎÎÎÎ

t

_f ^ÎÎÎ

ÎÎÎ

−

^ÎÎÎ

ÎÎÎ

50

^ÎÎÎ

ÎÎÎ

75

^ÎÎÎ

ÎÎÎ

ns ORDERING INFORMATION

Device Package Shipping

^†

D45C12 TO−220AB

50 Units / Rail

D45C12G TO−220AB

(Pb−Free)

D44C12 TO−220AB

D44C12G TO−220AB

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

200

0.04 Figure 1. Typical DC Current Gain I

_C

, COLLECTOR CURRENT (AMPS) 20

0.07 0.1 0.2 0.3 1.0 2.0 4.0

70 50 40 30 80 60

h FE , DC CURRENT GAIN

0.4 0.7 100

V

_CE

= 1.0 Vdc T

_J

= 25 ° C

1.0 V

_CE

, COLLECTOR-EMITTER VOLTAGE (VOLTS) 10

1.0

0.01 I C , COLLECT OR CURRENT (AMPS)

dc

1.0 m s

2.0 0.1 ms

10 20 100

0.2 5.0 T

_C

≤ 70 ° C DUTY CYCLE ≤ 50%

Figure 2. Maximum Rated Forward Bias Safe Operating Area

90

3.0 1.0 ms 10 m s

0.02 0.03 0.05 0.3 0.1 0.5 2.0 3.0 5.0

3.0 7.0 30 50 70

(3)

TO−220 CASE 221A

ISSUE AK

DATE 13 JAN 2022

SCALE 1:1

STYLE 1:

PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

STYLE 2:

PIN 1. BASE 2. EMITTER 3. COLLECTOR 4. EMITTER

STYLE 3:

PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE

STYLE 4:

PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE 4. MAIN TERMINAL 2 STYLE 7:

PIN 1. CATHODE 2. ANODE 3. CATHODE 4. ANODE STYLE 10:

PIN 1. GATE 2. SOURCE 3. DRAIN 4. SOURCE STYLE 5:

PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN

STYLE 8:

PIN 1. CATHODE 2. ANODE

3. EXTERNAL TRIP/DELAY 4. ANODE

STYLE 6:

PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 9:

PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

STYLE 11:

PIN 1. DRAIN 2. SOURCE 3. GATE 4. SOURCE

STYLE 12:

PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE 4. NOT CONNECTED

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

98ASB42148B DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 TO−220

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www.onsemi.com

(4)

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PUBLICATION ORDERING INFORMATION

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North American Technical Support:

Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910

LITERATURE FULFILLMENT:

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Europe, Middle East and Africa Technical Support:

Phone: 00421 33 790 2910

For additional information, please contact your local Sales Representative

D45C12 (PNP), D44C12 (NPN) Complementary Silicon Power Transistor

October, 2011 − Rev. 3 1 Publication Order Number:

D45C12/D

D45C12 (PNP), D44C12 (NPN)

Complementary Silicon Power Transistor

The D45C12 and D44C12 are for general purpose driver or medium power output stages in CW or switching applications.

Features

• Low Collector−Emitter Saturation Voltage − 0.5 V (Max)

• High f t for Good Frequency Response

• Low Leakage Current

• Pb−Free Packages are Available*

MAXIMUM RATINGS

Rating

Symbol

Value

Unit

Collector−Emitter Voltage

V

80

Vdc

Collector−Emitter Voltage

VCES

90

Vdc

Emitter Base Voltage

V

5.0

Vdc

Collector Current − Continuous Peak (Note 1)

I

4.0 6.0

Adc

Total Power Dissipation @ T

= 25°C Total Power Dissipation @ T

= 25°C

P

30 1.67

W W/°C

Operating and Storage Junction Temperature Range

T

, T

−55 to 150

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

THERMAL CHARACTERISTICS

Characteristic

Symbol

Max

Unit

Thermal Resistance, Junction−to−Case

R

4.2

° C/W

Thermal Resistance, Junction−to−Ambient

R

75

° C/W

Maximum Lead Temperature for Soldering Purposes: 1/8 in from Case for 5 Sec

T

275

°C 1. Pulse Width v 6.0 ms, Duty Cycle v 50%.

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

D4xC12G AYWW 1

Base 3

Emitter 4

Collector

2 Collector

4.0 AMPERE COMPLEMENTARY SILICON POWER

TRANSISTORS 80 VOLTS

TO−220AB CASE 221A STYLE 1 1 2

3 4

MARKING DIAGRAM

& PIN ASSIGNMENT

x = 4 or 5

A = Assembly Location

Y = Year

WW = Work Week G = Pb−Free Package

ORDERING INFORMATION

http://onsemi.com

D45C12 (PNP), D44C12 (NPN)

• ^{High f} t for Good Frequency Response