A伽trad
So far, many of 血e design・for・testability techniques have been investigated and developed mainly to ease the difficulty of test generation and application, focussino on DC functionaltestin8. This paper suggests that design、for、 testability techniques should also be investi8ated from a different point of view such as to cope with new and Cha11en即n号 Problems ofveTy high speed testin80ffuture MOS
Or GaAs circuits
Design for 旺igh・speed TestabⅡity
Hideo Fujiwara
Depar註nent ofElecu'onics aTld c0加nunications Meijiuniversity
Kawasaki 214, Japan
Backgr0血d
As the techn010gy of 血e vLsl circuits advances with Iarger pin counts and higher speed of operation, automatic test equipment(ATE) systems are required to keep up with the fast Speed as we11 as high pin counts. Although today'S ATE Systems seem to keep pace with curtent vLsl advances [1], With the incTease of 血e use of very・high・speed inteorated Circuits (VHSICS) such as high、speed Mos or GaAS VLSI Circuits, much more powedultest eqUゆment wi11 be required in future for those veTy fast vLsl circuits [2]. Moreover, when accurate t1軌ng measurements ate required for those vHSICS, the ATE system wiu be faced with sedous problems such as Waveform dist0武ion caused by tranS血Ssion line reaections !3].
There 紅e four types of testing for digital circuits: DC functional, Dc parametdc, Ac parametric, and clock、rate functional.1n Dc functionaltesting, the circuit under testis exercised by applying test input pattems and analyzing the Corresponding steady state oUゆUts, i.e. only functional behavior of the circuit under test is tested. DC
Parametrlc
tesnng ls to measure such Dc parameters as v01τages and CurTents of the circuit under test at a low rate. Ac parametric testlng ls to check time・related parameters such as dse and faⅡ times, and propagation delay. clock・rate testin三 is aimed to
ensure that the circuit under test operates correctly at the maximum clock rate,i.e. to verify the time・Telated behavior of the circuit under test. High・speed testina is thus required for both AC P釘ametric and clock・Tate testing. Especia11y for VHSIC'S,itis importantto assure the maximum performance Of circuits aS 晒,e11 as to verify the time・related behavior at the maximum clock Tate. Thus the need for high・speed testing of VLsl and vHsl circuits is as clear as day. This problem, though di丘icult, is unavoidable, and new techn0103ies or appToaches aTe expected to reach a solution. To cope with the Problem that we are now faced with, the f0110wing three approaches would be consjdered.
(D Further development of more powerfulexternaltest equipment which can properly test vLsl and vHsl ciTcuits. Test equipment operating up t01-3 GHz wiⅡ be needed to test GaAs circuits [2}. This approach, though straightforward, 血ght be very difficult and expensive to achieve.
(2) Designing lc's for testability so as to lighten the burden ofextemaltest equipment
(3) Designing lc's for testability so as to require no externaltest equipment. Built・in self・test (BIST) approach belongs here.
Built.hl self.Test
A pdmary weahless ofa conventionaltesting philosophy based on external testina, in which expHcit test patterns are applied by test equipment externalto the circuit under test, is that a technique is eχ杠'emely constrained by limited access to internal points in the circuit under Test. This implies some Problems on test・pattern geneTation and application costs:(1) increasing time required to geneTate Test pattern data,(2) the 容rowing volume of test pattern data, and (3) the sianificant cost Of ATE and the test appHcation time. so far, many of the design・for・testability techniques have been investi8ated and
19871nternational Test conference
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developed mainly to reduce those costs or to ease those difficulties of test pattem generation and application, focussing On Dc functionaltesting [4]. H0圦,ever, as mentioned above, new design・for・testability techniques are needed to cope with high・speed testino of vHSIC's as wen as vLsl ciTcuits. Built・ 血 Self・test(BIST) approaches,in which test patternS 釘e applied intema11y to the circuit under test and their oU中Ut responses are evaluated withoutthe use of externaltest equipment, seem to t)e Preferred over exteTnaltesting and hold a good prospect for M8h・speed testing in futuTe.
A BIST circuit requires thatthe functions of test pattern generation and oU中Ut response evaluation are incorporated into the circuit under test. The most popular approach used for BIST is compact testing using pseudo・random patterns Pseudo・random test patterns are usua11y generated by a linear feedback shift register (LFSR) and applied to the circuit under test. The output responses from the circuit under test are then Compressed through another LFSR to form a signature. By analyzing the si3nature, one can determine whetheT the circuit Under testis faulty or not [5].
BIST can a11eviate the above・mentioned problems on test・pattem generation and application costs: since test patterns are 名enerated by a built・in random pattem generator,the time・ Consuming e丘ort oftestpattem generation can beremoved from the design cycle. since compacttesting compresses response data and compares the signatute only once,血e dif丘Culty of analysis and storage of huge amounts of test response data can
be avoided
FunhermoTe, BIST has anotherimponant advantage that {he circuit under test is fed with random test patterns at the functional clock rate. Hence, it is possible to perform high・ Speed tesing using intemaltest equiprnent b峨lt in the circuit Under test. BIST could provide an effective method of hi3h・ Speed testing,including Ac delay teS廿ng f6]. since delay faults affectthe U血ng operation ofcircuits, delay testing is ped0血ed to ensure that the circuit under test can operate correctly at the funcdonaldock rate. BIST has the capability of this high・speed
tesung
BIST approaches have been applied either partia11y or fU11y to commercialproducts such as mjcroprocessors [フ・釘 and 容ate arrays {9] though focussing on Dc functionaltesdng. The Current techniques on BIST, however, have some problems, e.g.血e difficulty of achieving high fault coverage for sequendal CiTcuits due to Tandomness of test pattems, etc. Furthermore, th巳τe are some unso!ved problems; BIST techniques foT aiding in patame杠'ic testing or Ac charactedzation, BIST techniques
applicable to analog and hybrid ciTcuits, etc.110]. Further investigations are thus required to find out e丘ective approaches Capable of answering those difficult ot unsolved problems. Considering the situation that testing with externaltest equipment has come up against a wau of "intractability" and is at a standsti11, it would be na山ralto expect internaltesting, i.e BIST, instead of extemaltestino. Mote research on BIST,
including the extention ofthe concepts ofBIST, should be done to cope 圦,ith 血e above・mentioned problems in future.
Acknowledgments
The author wishes to thank Dr. T.Yamada of Meiji University and Mr. T.Kurobe of NEc corp. for their valuable Con血ents and suggestions
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