Chapter 5
Hardware Design
5.1 Introduction
Since FLSs and ANNs have parallel processing architectures, the development of their hardware is beneficial for performance improvement. The fuzzy boom in Japan has led to the development of commercial fuzzy processors. Major fuzzy chips are reviewed in [15][44][55]. Neural network chips are also widely used in real-time applications. The advantages of the hardware implementation of FLSs and ANNs include the following:
1. Speed enhancement due to the parallel processing.
2. Real-time learning capabilities obtained by concurrently performing learning and other computations.
(when learning ability is possessed)
3. Acquisition of fault tolerance by the parallel processing structure.
In the IDS method, the number of IDS units increases significantly with the number of inputs and parti-tions. Assuming that we have an IDS modeling system with a number of IDS units integrated into a standard computer, performing the IDS and calculating the narrow path and spread for each IDS unit would place a heavy load on the host CPU. This would lengthen the processing time required for modeling and impact the entire system performance. Furthermore, as described in Section 4.3, the structure of the IDS models provides robustness against failures. Although the hardware systems of FLSs and ANNs are almost provided by single chip solutions, a high fault tolerance is achieved by providing distributed hardware units. In order to realize the real-time capabilities and robustness of the IDS modeling systems, the development of dedicated hardware for the IDS units is desirable. This chapter describes the hardware development of the IDS unit.
48 CHAPTER 5. HARDWARE DESIGN
PCI bus
Local bus
XY plane memory
Sync. SRAM
Sync. SRAM
64-bit / 100MHz 32-bit / 55MHz
32-bit / 33MHz
IDS controller PCI-IDS
interface 512 Kbyte
8M byte
Shared memory
Figure 5.1: Block diagram of HIDS.
operating frequency is 100 MHz. The XY plane memory stores the pattern of thex-y plane. One x-y plane comprises 256×256 cells with an 8-bit depth and requires 64 Kbytes of memory. In the HIDS, 8 Mbyte SRAM was used for the XY plane memory to allow a single IDS controller to have multiple x-y planes.
Figure 5.2 shows the address allocation of the x-y plane. The IDS controller performs 8-byte access to the XY plane memory and simultaneously obtains eight narrow path and spread sets. The shared memory stores the narrow path and spread sets, which are updated by the IDS controller and fetched by the host CPU. The local bus in the figure is a simple original bus that operates at a frequency of 55 MHz. The HIDS contains two FPGAs. One FPGA is the Altera Cyclone device (P/N: EP1C6Q240C6), which is used as the IDS controller.
The other FPGA is the Altera ACEX device (P/N: EP1K50QC208-1) and is used for the PCI-IDS interface.
The circuit diagram of the HIDS is shown in Appendix C.
Figure 5.3 shows a block diagram of the IDS controller. The controller provides operational registers in the local bus interface and register block, to which the host CPU writes x and y coordinates of data points and the radius of the ink drop pattern. The controller includes two memory blocks: ink drop pattern memory and IDS local memory. The ink drop pattern memory stores an ink drop pattern and the size of the memory is 8 Kbytes. Figure 5.4 shows the address allocation of the ink drop pattern memory and the 11×11 ink drop pattern obtained by (2.6). The values in each cell represent the darkness added in the x-y plane. The central cell of the pattern with the highest darkness is placed on the data points on the x-y plane. The IDS controller adds the read data from the internal ink drop pattern memory to the read data from the XY plane memory and writes the added data back to the XY plane memory. Due to the implementation of an individual memory block for ink drop patterns, the processing time of the IDS is reduced due to the simultaneously reading of the
5.2. DESIGN OF HIDS: HIGH-SPEED IDS HARDWARE UNIT 49
0h 8h 10h 18h 7F8h
800h 808h 810h 818h FF8h
1000h 1008h 1010h 1018h 17F8h
F800h F808h F810h F818h FFF8h
1800h 1808h 1810h 1818h 1FF8h
0 1 2 3 255
0 1 2 3 255
X Y
Figure 5.2: Address allocation of XY plane memory.
Local bus interface and register
Ink drop spread Ink drop pattern memory
XY plane memory interface Narrow path and
spread calculator
XY plane memory
Host
Image update IDS local memory Shared memory
Figure 5.3: Block diagram of IDS controller.
50 CHAPTER 5. HARDWARE DESIGN
0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF
0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F
0x200 0x201 0x208 0x209
0 0 0 0 0 1 0 0 0 0 0 0
Address
Darkness 0 0 0 0 1 0 0 0 0 0x202 0x203
0 1 1 1 2 1 1 1
0 0
0 0 0
1 1 2 2 3 2 2 1 1 0 0
0x20A 0x20B 0x210 0x211 0x212 0x213 0x218 0x219 0x21A 0x21B
1 2 3 3 4 3 3 2 1 0 0
1 2 3 4 5 4 3 2 1 0 0
2 3 4 5 6 5 4 3 2 1 0
0x220 0x221 0x222 0x223 0x228 0x229 0x22A 0x22B
1 2 3 4 5 4 3 2 1 0 0
1 2 3 3 4 3 3 2 1 0 0
1 1 2 2 3 2 2 1 1 0 0
0 1 1 1 2 1 1 1 0 0 0
0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0x230 0x231 0x232 0x233 0x238 0x239 0x23A 0x23B 0x240 0x241 0x242 0x243 0x248 0x249 0x24A 0x24B 0x250 0x251 0x252 0x253 0x258 0x259 0x25A 0x25B
Figure 5.4: 11×11 ink drop pattern stored in ink drop pattern memory.
XY plane memory and the ink drop pattern memory. The IDS local memory stores the image information that enables the IDS controller to quickly find the narrow path and spread; the size of this memory is 512 bytes.
The memory format is shown in Figure 5.5. The START and END fields are the lower and upper points, respectively, of the range of the y coordinate used for calculating the narrow path and spread. The default values of the START and END fields are 0 and 0xFF, respectively. If the y coordinate of the lower end of an added ink drop pattern is lower than the value of the START field, the START field is updated with the y coordinate of the lower end of the added ink drop pattern. Similarly, if the y coordinate of the upper end of an added ink drop pattern is higher than the value of the END field, the END field is updated with the y coordinate of the upper end of the added ink drop pattern.
The narrow path and spread calculator reads the XY plane memory and determines the narrow path and spread according to (2.7) and (2.8). In order to avoid the overflow of the x-y planes, the image update block always checks the write data to the XY plane memory during IDS operations. If the write data is above a given threshold, the image update block starts a routine that decreases the darkness level of the entire x-y plane after the completion of the IDS operation. The controller provides two thresholds: 0xE0 and 0xF0, and the threshold condition is set by the host CPU.
The Altera Cyclone device used in the HIDS provides 5,980 logic elements and a 92,160-bit memory. We implemented the abovementioned functions in this device. The design of the IDS controller required 54 % of the available logic elements of the device and 72 % of the available memory.
Figure 5.6 shows the appearance of the HIDS board. This board can be installed in both the 3.3 and 5 V PCI slots.