４．１．６ 電卓のブロック図 電卓のブロック図を図4.4に示す。
10進→2進変換回路
（DEC̲TO̲BIN）
27ビットレジスタ
（REG̲A）
×10 乗算回路
（CNV̲MUL）
加算回路
（cnv̲adder）
演算回路
（ADD、SUB、
MUL、DIV）
29ビットレジスタ
（REG̲B）
セレクタ
（ASMD̲SEL）
セレクタ
（lastsel）
2の補数 出力回路
（2hosu）
非同期→同期変換回路
（syncro）
状態遷移機械
（state）
2進→BCD変換回路
（bintobcd）
7セグメントデコーダ回路
（７SEG̲DEC）
電卓（calc）
7セグメントLED出力
（７LED）
符号出力
（SIGN）
10キー入力
（DECIMAL）
演算キー入力
（PLUS、MINUS、KAKERU、
WARU、EQUAL、C、CE）
オーバーフロー出力
（OVF）
エラー出力
（ERROR̲OUT）
リセット
（RESET）
クロック
（CLK）
セレクタ
（INPUT̲SEL）
４．２ VHDLによる電卓の設計
第3章の演算回路と、4.1節のブロック図からVHDLで電卓を設計する。
library ieee;
use ieee.std_logic_1164.all;
entity ADD is
port(A:in std_logic_vector(26 downto 0);
B:in std_logic_vector(28 downto 0);
S:out std_logic_vector(28 downto 0);
START,CLOCK,RESET_B:in std_logic);
end ADD;
architecture ADD of ADD is
signal ADDER4_OUT:std_logic_vector(4 downto 0);
signal BIT_A_OUT:std_logic_vector(3 downto 0);
signal BIT_B_OUT:std_logic_vector(3 downto 0);
signal BIT_REG_OUT:std_logic_vector(28 downto 0);
signal CNT16_OUT:std_logic_vector(4 downto 0);
signal JK_FF_K_IN:std_logic;
signal JK_FF_Q_OUT:std_logic;
component ADDER4
port(a,b:in std_logic_vector(3 downto 0);
cin:in std_logic;
s:out std_logic_vector(4 downto 0));
end component;
component BIT_SHIFT_A
port(LOAD,CLK,EN:in std_logic;
A_IN:in std_logic_vector(26 downto 0);
Q_A:out std_logic_vector(3 downto 0));
end component;
図4.5 加算器のVHDL（1/3）
component BIT_SHIFT_B
port(LOAD,CLK,EN:in std_logic;
B_IN:in std_logic_vector(28 downto 0);
Q_B:out std_logic_vector(3 downto 0));
end component;
component BIT_REG
port(RESET,RESET_B,CLK,EN:in std_logic;
PIN:in std_logic_vector(4 downto 0);
Q:out std_logic_vector(28 downto 0));
end component;
component RS_SYJKFF port(RESET_B:in std_logic;
SET_B:in std_logic := '1';
J,K,CLK:in std_logic;
Q,Q_B:out std_logic);
end component;
component EN_CNT16
port(Q:out std_logic_vector(4 downto 0);
EN,CLK,CLR_SY,CLR_USY:in std_logic);
end component;
begin
JK_FF_K_IN <= not CNT16_OUT(4) and not CNT16_OUT(3) and CNT16_OUT(2) and CNT16_OUT(1) and not CNT16_OUT(0);
S <= BIT_REG_OUT;
U_A:BIT_SHIFT_A port map(START,CLOCK,JK_FF_Q_OUT,A,BIT_A_OUT);
U_B:BIT_SHIFT_B port map(START,CLOCK,JK_FF_Q_OUT,B,BIT_B_OUT);
U_ADDER4:ADDER4 port map(BIT_A_OUT,BIT_B_OUT,BIT_REG_OUT(28), ADDER4_OUT);
U_REG:BIT_REG port map(RESET_B,START,CLOCK,JK_FF_Q_OUT, ADDER4_OUT,BIT_REG_OUT);
JK_FF:RS_SYJKFF port map(RESET_B,open,START,JK_FF_K_IN,CLOCK, JK_FF_Q_OUT,open);
図4.5 加算回路のVHDL（2/3）
CNT8:EN_CNT16 port map(CNT16_OUT,JK_FF_Q_OUT,CLOCK,START,RESET_B);
end ADD;
図4.5 加算回路のVHDL（3/3）
library ieee;
use ieee.std_logic_1164.all;
entity MUL is
port(START,CLOCK,RESET_B:in std_logic;
MD:in std_logic_vector(28 downto 0);
MQ:in std_logic_vector(26 downto 0);
ANS:out std_logic_vector(55 downto 0));
end MUL;
architecture MUL of MUL is signal MQ_S_OUT:std_logic;
signal JK_FF_K_IN:std_logic;
signal JK_FF_Q_OUT:std_logic;
signal MD_Q_OUT:std_logic_vector(28 downto 0);
signal ADDER32_A_IN:std_logic_vector(28 downto 0);
signal ADDER32_OUT:std_logic_vector(29 downto 0);
signal CNT16_OUT:std_logic_vector(4 downto 0);
signal ACC_D_IN:std_logic_vector(56 downto 0);
signal ACC_Q_OUT:std_logic_vector(56 downto 0);
component ADDER32
port(a,b:in std_logic_vector(28 downto 0);
cin:in std_logic :='0';
s:out std_logic_vector(28 downto 0);
cout:out std_logic);
end component;
図4.6 乗算回路のVHDL（1/3）
component REG_MD
port(LOAD,CLK:in std_logic;
D:in std_logic_vector(28 downto 0);
Q:out std_logic_vector(28 downto 0));
end component;
component EN_REG
port(RESET,EN,CLR,CLK:in std_logic;
D:in std_logic_vector(56 downto 0);
Q:out std_logic_vector(56 downto 0));
end component;
component BIT_SHIFT port(SIN:in std_logic :='0';
EN,LOAD,CLK:in std_logic;
D:in std_logic_vector(26 downto 0);
SOUT:out std_logic);
end component;
component RS_SYJKFF
port(RESET_B:in std_logic;
SET_B:in std_logic := '1';
J,K,CLK:in std_logic;
Q,Q_B:out std_logic);
end component;
component EN_CNT16
port(EN,CLK,CLR_SY,CLR_USY:in std_logic;
Q:out std_logic_vector(4 downto 0));
end component;
begin
ADDER32_A_IN <= MD_Q_OUT and (MQ_S_OUT & MQ_S_OUT &
MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT &
MQ_S_OUT& MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT &
MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT& MQ_S_OUT &
MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT &
MQ_S_OUT & MQ_S_OUT& MQ_S_OUT & MQ_S_OUT & MQ_S_OUT &
MQ_S_OUT & MQ_S_OUT);
図4.6 乗算回路のVHDL（2/3）
ACC_D_IN <= ADDER32_OUT & ACC_Q_OUT(27 downto 1);
JK_FF_K_IN <= CNT16_OUT(4) and CNT16_OUT(3) and not CNT16_OUT(2) and CNT16_OUT(1) and CNT16_OUT(0);
ANS <= ACC_Q_OUT(55 downto 0);
U_MD:REG_MD port map(START,CLOCK,MD,MD_Q_OUT);
U_ADDER:ADDER32 port map(ADDER32_A_IN,ACC_Q_OUT(56 downto 28), open,ADDER32_OUT(28 downto 0),ADDER32_OUT(29));
ACC:EN_REG port map(RESET_B,JK_FF_Q_OUT,START,CLOCK,
ACC_D_IN,ACC_Q_OUT);
U_MQ:BIT_SHIFT port map (open,JK_FF_Q_OUT,START,CLOCK,
MQ,MQ_S_OUT);
JK_FF:RS_SYJKFF port map(RESET_B,open,START,JK_FF_K_IN,CLOCK, JK_FF_Q_OUT,open);
CNT16:EN_CNT16 port map(JK_FF_Q_OUT,CLOCK,START,RESET_B, CNT16_OUT);
end MUL;
図4.6 乗算回路のVHDL（3/3）
library IEEE;
use IEEE.std_logic_1164.all;
entity DIV is
port(DD:in std_logic_vector(28 downto 0);
DQ:in std_logic_vector(26 downto 0);
ANS:out std_logic_vector(28 downto 0);
ARE:out std_logic_vector(26 downto 0);
START,CLOCK,RESET_B:in std_logic ; ER : out std_logic);
end DIV;
図4.7 除算回路のVHDL（1/5）
architecture DIV of DIV is
signal DQ_E_OUT:std_logic;
signal E_JK_FF_J_IN:std_logic;
signal STR:std_logic;
signal DQ_SEL_IN:std_logic;
signal ACC_SEL_IN:std_logic;
signal ACC_EN1:std_logic;
signal JK_FF_K_IN: std_logic;
signal JK_FF_Q_OUT:std_logic;
signal ANS_SIN:std_logic;
signal ANS_EN:std_logic;
signal LAST:std_logic;
signal DQ_Q_OUT:std_logic_vector(26 downto 0);
signal DQ_SEL_A_IN:std_logic_vector(27 downto 0);
signal DQ_SEL_B_IN:std_logic_vector(27 downto 0);
signal DQ_SEL_OUT:std_logic_vector(27 downto 0);
signal ADD_SUB_B_IN:std_logic_vector(27 downto 0);
signal ADD_SUB_OUT:std_logic_vector(28 downto 0);
signal ACC_SEL_A_IN:std_logic_vector(55 downto 0);
signal ACC_SEL_B_IN:std_logic_vector(55 downto 0);
signal ACC_D_IN:std_logic_vector(56 downto 0);
signal ACC_Q_OUT:std_logic_vector(56 downto 0);
signal ANS_Q_OUT:std_logic_vector(28 downto 0);
signal CNT16_OUT:std_logic_vector(4 downto 0);
component ADD_SUB
port(A,B:in std_logic_vector(27 downto 0);
SUB:in std_logic;
S:out std_logic_vector(27 downto 0);
CY_BR:out std_logic );
end component;
component EN_REG4
port(D:in std_logic_vector(26 downto 0);
Q:out std_logic_vector(26 downto 0);
図4.7 除算回路のVHDL（2/5）
EN,CLK:in std_logic);
end component;
component EN_REG13
port( D:in std_logic_vector(56 downto 0);
Q:out std_logic_vector(56 downto 0);
RESET,EN,CLK:in std_logic);
end component;
component EN_SIN_POUT_SHIFT port(SIN:in std_logic;
Q:out std_logic_vector(28 downto 0);
EN,PS,CLK:in std_logic);
end component;
component RS_SYJKFF
port(RESET_B:in std_logic;
SET_B:in std_logic := '1';
J:in std_logic;
K:in std_logic := '0';
CLK:in std_logic;
Q,Q_B:out std_logic);
end component;
component EN_CNT16
port(Q:out std_logic_vector(4 downto 0);
EN,CLK,CLR_SY,CLR_USY:in std_logic);
end component;
component SEL5
port(A,B:in std_logic_vector(27 downto 0);
O:out std_logic_vector(27 downto 0);
SEL:in std_logic);
end component;
component SEL12
port(A,B:in std_logic_vector(55 downto 0);
O:out std_logic_vector(55 downto 0);
SEL:in std_logic);
図4.7 除算回路のVHDL（3/5）
end component;
begin
DQ_E_OUT <= not DQ(26) and not DQ(25) and not DQ(24) and not DQ(23) and not DQ(22) and not DQ(21) and not DQ(20) and not DQ(19) and not DQ(18) and not DQ(17) and not DQ(16) and not DQ(15) and not DQ(14) and not DQ(13) and not DQ(12) and not DQ(11) and not DQ(10) and not DQ(9) and DQ(8) and not DQ(7) and not DQ(6) and not DQ(5) and not DQ(4) and not DQ(3) and not DQ(2) and not DQ(1) and not DQ(0);
E_JK_FF_J_IN <= DQ_E_OUT and START;
STR <= START and (not DQ_E_OUT);
DQ_SEL_IN <= not JK_FF_K_IN; ACC_SEL_IN <= not STR;
ACC_EN1 <= STR or JK_FF_Q_OUT;
JK_FF_K_IN <= CNT16_OUT( 4 ) and CNT16_OUT( 3 ) and not CNT16_OUT( 2 ) and CNT16_OUT( 1 ) and CNT16_OUT( 0 );
LAST <= not ( JK_FF_K_IN and ANS_Q_OUT( 0 ));
DQ_SEL_A_IN <= '0' & DQ_Q_OUT; DQ_SEL_B_IN <= DQ_Q_OUT & '0';
ADD_SUB_B_IN <= DQ_SEL_OUT and ( LAST & LAST & LAST & LAST & LAST
& LAST & LAST & LAST & LAST & LAST & LAST & LAST& LAST & LAST &
LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST &
LAST& LAST & LAST & LAST & LAST );
ACC_SEL_A_IN <= ADD_SUB_OUT( 26 downto 0 ) &
ACC_Q_OUT( 25 downto 0 ) & '0';
ACC_SEL_B_IN <= DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)&
DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)&
DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)&
DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD;
ACC_D_IN( 54 ) <= ADD_SUB_OUT( 27 );
ANS <= ANS_Q_OUT;
ANS_SIN <= ANS_Q_OUT( 0 ) xor ADD_SUB_OUT( 28 );
ANS_EN <= not JK_FF_K_IN and JK_FF_Q_OUT;
ARE <= ACC_Q_OUT( 56 downto 30 );
U_ADD_SUB:ADD_SUB port map ( ACC_Q_OUT( 55 downto 28 ), ADD_SUB_B_IN, ANS_Q_OUT( 0 ), ADD_SUB_OUT( 27 downto 0 ), ADD_SUB_OUT( 28 ));
U_D:EN_REG4 port map ( DQ, DQ_Q_OUT, STR, CLOCK );
図4.7 除算回路のVHDL（4/5）
ACC:EN_REG13 port map(ACC_D_IN,ACC_Q_OUT,RESET_B,
ACC_EN1,CLOCK );
U_ANS:EN_SIN_POUT_SHIFT port map(ANS_SIN,ANS_Q_OUT,ANS_EN, STR,CLOCK );
JK_FF:RS_SYJKFF port map(RESET_B,open,STR,JK_FF_K_IN,
CLOCK, JK_FF_Q_OUT, open );
E_JK_FF:RS_SYJKFF port map(RESET_B,open,E_JK_FF_J_IN,open,
CLOCK,ER,open);
CNT16:EN_CNT16 port map(CNT16_OUT,JK_FF_Q_OUT,CLOCK,
STR, RESET_B );
DQ_SEL:SEL5 port map(DQ_SEL_A_IN,DQ_SEL_B_IN,
DQ_SEL_OUT,DQ_SEL_IN);
ACC_SEL:SEL12 port map(ACC_SEL_A_IN,ACC_SEL_B_IN,
ACC_D_IN( 55 downto 0 ),ACC_SEL_IN);
end DIV;
図4.7除算回路のVHDL（5/5）
library IEEE;
use IEEE.std_logic_1164.all;
entity DEC_TO_BIN is
port(DEC:in std_logic_vector(9 downto 0);
BIN:out std_logic_vector(3 downto 0));
end DEC_TO_BIN;
architecture DEC_TO_BIN of DEC_TO_BIN is begin
process(DEC) begin
case DEC is
図4.8 10キー入力のBCD変換回路のVHDL（1/2）
when "0000000001" => BIN <= "0000";
when "0000000010" => BIN <= "0001";
when "0000000100" => BIN <= "0010";
when "0000001000" => BIN <= "0011";
when "0000010000" => BIN <= "0100";
when "0000100000" => BIN <= "0101";
when "0001000000" => BIN <= "0110";
when "0010000000" => BIN <= "0111";
when "0100000000" => BIN <= "1000";
when "1000000000" => BIN <= "1001";
when others => BIN <= "0000";
end case;
end process;
end DEC_TO_BIN;
図4.8 10キー入力のBCD変換回路のVHDL（2/2）
library ieee;
use ieee.std_logic_1164.all;
entity REGA is
port(DECI:in std_logic_vector(9 downto 0);
KEKKA:out std_logic_vector(26 downto 0);
REG_EN,IN_SEL,RST,CLK:in std_logic);
end REGA;
architecture REGA of REGA is
signal BCD:std_logic_vector(3 downto 0);
signal ADDER_OUT:std_logic_vector(26 downto 0);
signal REG_A_IN:std_logic_vector(26 downto 0);
signal REG_A_OUT:std_logic_vector(26 downto 0);
図4.9 REGAのVHDL（1/3）
signal MUL_OUT:std_logic_vector(26 downto 0);
component DEC_TO_BIN is
port(DEC:in std_logic_vector(9 downto 0);
BIN:out std_logic_vector(3 downto 0));
end component;
component REG_A is
port(EN,RESET_B,CLK:in std_logic;
PIN:in std_logic_vector(26 downto 0);
Q:out std_logic_vector(26 downto 0));
end component;
component cnv_mul is
port(MD:in std_logic_vector(23 downto 0);
ANS:out std_logic_vector(26 downto 0);
MO:out std_logic);
end component;
component cnv_adder is
port(A:in std_logic_vector(26 downto 0);
B:in std_logic_vector(3 downto 0);
S:out std_logic_vector(26 downto 0));
end component;
component INPUT_SEL is
port(A,B:in std_logic_vector(26 downto 0);
O:out std_logic_vector(26 downto 0);
SEL:in std_logic);
end component;
begin
KEKKA <= REG_A_OUT;
U_ENC:DEC_TO_BIN port map(DECI,BCD);
U_REG_A:REG_A port map(REG_EN,RST,CLK,REG_A_IN,REG_A_OUT);
U_MUL:cnv_mul port map(REG_A_OUT(23 downto 0),MUL_OUT,open);
U_ADD:cnv_adder port map(MUL_OUT,BCD,ADDER_OUT);
図4.9 REGAのVHDL（2/3）
U_SEL:INPUT_SEL port map(ADDER_OUT,"00000000000000000000000" &
BCD,REG_A_IN,IN_SEL);
end REGA;
図4.9 REGAのVHDL（3/3）
library ieee;
use ieee.std_logic_1164.all;
entity REGB is
port(ASMD:in std_logic_vector(1 downto 0);
REGA_OUT:in std_logic_vector(26 downto 0);
REGB_OUT:out std_logic_vector(26 downto 0);
TO_STATE:out std_logic_vector(28 downto 0);
CLK,REG_RST,ADD_EN,SUB_EN,MUL_EN,DIV_EN:in std_logic;
ERR:out std_logic);
end REGB;
architecture REGB of REGB is
signal REG_B_IN:std_logic_vector(28 downto 0);
signal REG_B_OUT:std_logic_vector(28 downto 0);
signal HOSU_OUT:std_logic_vector(26 downto 0);
signal ADDER_OUT:std_logic_vector(28 downto 0);
signal SUB_OUT:std_logic_vector(28 downto 0);
signal MUL_OUT:std_logic_vector(55 downto 0);
signal DIV_OUT:std_logic_vector(28 downto 0);
component REG_B is
port(RESET_B,CLK:in std_logic;
PIN:in std_logic_vector(28 downto 0);
Q:out std_logic_vector(28 downto 0));
end component;
図4.10 REGBのVHDL（1/3）
component hosu is
port(PIN:in std_logic_vector(27 downto 0);
Q:out std_logic_vector(26 downto 0);
CLK:in std_logic);
end component;
component ASMD_SEL is
port(A,S,M,D:in std_logic_vector(28 downto 0);
O:out std_logic_vector(28 downto 0);
SEL:in std_logic_vector(1 downto 0));
end component;
component ADD is
port(A:in std_logic_vector(26 downto 0);
B:in std_logic_vector(28 downto 0);
S:out std_logic_vector(28 downto 0);
START,CLOCK,RESET_B:in std_logic);
end component;
component SUB is
port(A:in std_logic_vector(26 downto 0);
B:in std_logic_vector(28 downto 0);
DIF:out std_logic_vector(28 downto 0);
START,CLOCK,RESET_B:in std_logic);
end component;
component MUL is
port(START,CLOCK,RESET_B:in std_logic;
MD:in std_logic_vector(28 downto 0);
MQ:in std_logic_vector(26 downto 0);
ANS:out std_logic_vector(55 downto 0));
end component;
component DIV is
port(DD:in std_logic_vector(28 downto 0);
DQ:in std_logic_vector(26 downto 0);
ANS:out std_logic_vector(28 downto 0);
ARE:out std_logic_vector(26 downto 0);
図4.10 REGBのVHDL（2/3）
end component;
begin
REGB_OUT<=HOSU_OUT;
TO_STATE <= REG_B_OUT;
U_REG_B:REG_B port map(REG_RST,CLK,REG_B_IN,REG_B_OUT);
U_HOSU:hosu port map(REG_B_OUT(27 downto 0),HOSU_OUT,CLK);
U_SEL:ASMD_SEL port map(ADDER_OUT,SUB_OUT, MUL_OUT(28 downto 0),DIV_OUT,REG_B_IN,ASMD);
U_ADD:ADD port map(REGA_OUT,REG_B_OUT,ADDER_OUT,ADD_EN,
CLK,REG_RST);
U_SUB:SUB port map(REGA_OUT,REG_B_OUT,SUB_OUT,SUB_EN,
CLK,REG_RST);
U_MUL:MUL port map(MUL_EN,CLK,REG_RST,REG_B_OUT,REGA_OUT, MUL_OUT);
U_DIV:DIV port map(REG_B_OUT,REGA_OUT,DIV_OUT,open,DIV_EN,CLK, REG_RST,ERR);
end REGB;
図4.10 REGBのVHDL（3/3）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity machine is
port(REGB:in std_logic_vector(28 downto 0);
ASMD:out std_logic_vector(1 downto 0);
CLK,RESET,DECI,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic;
SEL,EN,RST_A,RST_B,ADD,SUB,MUL,DIV:out std_logic);
end machine;
図4.11 状態遷移機械のVHDL（1/5）
signal BR:std_logic;
signal B_RST:std_logic;
signal COUNT:std_logic_vector(3 downto 0);
signal CAL:std_logic_vector(1 downto 0);
signal ASMD_SEL:std_logic_vector(1 downto 0);
signal ASMD_SELECT:std_logic_vector(3 downto 0);
begin
process(CLK,RESET) begin
if(RESET = '0') then COUNT <= "0000";
CAL <= "00";
state <= DECIMAL;
elsif(CLK'event and CLK ='1') then case state is
when DECIMAL =>
SEL <= '1';BR<='0';
if((DECI = '1') and (COUNT < 8)) then B_RST<='0';
COUNT <= COUNT + 1;
state <= DECIMAL;
elsif(C = '1') then
COUNT <= "0000";
state <= DECIMAL;
elsif(CE = '1') then COUNT <= "0000";
state <= DECIMAL;
elsif((PLUS or MINUS or KAKERU or WARU or EQUAL) = '1') then architecture machine of machine is
type t_state is (DECIMAL,OPE,HALT);
signal state:t_state;
図4.11 状態遷移機械のVHDL（2/5）
if(CAL = "00") then
ASMD_SELECT <= "0001";
ASMD_SEL<="00";
elsif(CAL = "01") then
ASMD_SELECT <= "0010";
ASMD_SEL<="01";
elsif(CAL = "10") then
ASMD_SELECT <= "0100";
ASMD_SEL<="10";
elsif(CAL = "11") then
ASMD_SELECT <= "1000";
ASMD_SEL<="11";
end if;
if(PLUS = '1')then CAL <= "00";
elsif(MINUS = '1') then CAL <= "01";
elsif(KAKERU = '1') then CAL <= "10";
elsif(WARU = '1') then CAL <= "11";
elsif(EQUAL = '1') then CAL <= "00";
BR <= '1';
end if;
state <= OPE;
end if;
when OPE =>
SEL <= '0';
if(((REGB(28) = '1') and (REGB < 436870913)) or ((REGB(28) ='0') and (REGB > 99999999))) then
state <= HALT;
elsif((PLUS or MINUS or KAKERU or WARU) = '1') then
図4.11 状態遷移機械のVHDL（3/5）
if(PLUS = '1')then CAL <= "00";
elsif(MINUS = '1') then CAL <= "01";
elsif(KAKERU = '1') then CAL <= "10";
elsif(WARU = '1') then CAL <= "11";
end if;
state <= OPE;
elsif(DECI = '1') then if(BR = '0') then B_RST <= '0';
COUNT <= "0001";
ASMD_SELECT<="0000";
elsif(BR = '1') then B_RST <= '1';
COUNT <= "0001";
ASMD_SELECT<="0000";
end if;
state <= DECIMAL;
end if;
when HALT =>
if(C = '1') then CAL <= "00";
COUNT <= "0000";
state <=DECIMAL;
elsif(CE = '1') then CAL <= "00";
COUNT <= "0000";
state <=DECIMAL;
end if;
end case;
図4.11 状態遷移機械のVHDL（4/5）
end if;
end process;
EN<=DECI and not(COUNT(3)and not COUNT(2)and not COUNT(1)and not COUNT(0));
RST_A<=not(CE or C);
RST_B<=not (C or B_RST);
ADD<=ASMD_SELECT(0);
SUB<=ASMD_SELECT(1);
MUL<=ASMD_SELECT(2);
DIV<=ASMD_SELECT(3);
ASMD<=ASMD_SEL;
end machine;
図4.11 状態遷移機械のVHDL（5/5）
library ieee;
use ieee.std_logic_1164.all;
entity state is
port(DECIMAL:in std_logic_vector(9 downto 0);
REG_B_OUT:in std_logic_vector(28 downto 0);
ASMD:out std_logic_vector(1 downto 0);
CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic;
A_D_SEL,REGA_EN,REGA_RST,REGB_RST,ADD_EN,SUB_EN,MUL_EN,DIV_E N:out std_logic);
end state;
architecture state of state is signal DEC:std_logic;
signal ADD_IN:std_logic;
signal SUB_IN:std_logic;
図4.12 STATEのVHDL（1/3）
signal MUL_IN:std_logic;
signal DIV_IN:std_logic;
signal ADD_OUT:std_logic;
signal SUB_OUT:std_logic;
signal MUL_OUT:std_logic;
signal DIV_OUT:std_logic;
signal ASMD_SELECT:std_logic_vector(1 downto 0);
component machine is
port(REGB:in std_logic_vector(28 downto 0);
ASMD:out std_logic_vector(1 downto 0);
CLK,RESET,DECI,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic;
SEL,EN,RST_A,RST_B,ADD,SUB,MUL,DIV:out std_logic);
end component;
component ASMD_OUT is
port(input,RESET,CLK:in std_logic;
output:out std_logic);
end component;
component syncro is
port(input,RESET,CLK:in std_logic;
output:out std_logic);
end component;
begin
DEC <= DECIMAL(9) or DECIMAL(8) or DECIMAL(7) or DECIMAL(6) or DECIMAL(5) or DECIMAL(4) or DECIMAL(3) or DECIMAL(2) or DECIMAL(1) or DECIMAL(0);
ADD_EN<=ADD_OUT;
SUB_EN<=SUB_OUT;
MUL_EN<=MUL_OUT;
DIV_EN<=DIV_OUT;
U_STATE:machine port map(REG_B_OUT,ASMD_SELECT,CLK,RESET,DEC, PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE,
A_D_SEL,REGA_EN,REGA_RST,REGB_RST,ADD_IN,SUB_IN,MUL_IN,DIV_IN);
図4.12 STATEのVHDL（2/3）
U_SYNC_A:syncro port map(ADD_IN,RESET,CLK,ADD_OUT);
U_SYNC_S:syncro port map(SUB_IN,RESET,CLK,SUB_OUT);
U_SYNC_M:syncro port map(MUL_IN,RESET,CLK,MUL_OUT);
U_SYNC_D:syncro port map(DIV_IN,RESET,CLK,DIV_OUT);
U_SYNC_ENC0_OUT:ASMD_OUT port map(ASMD_SELECT(0),
RESET,CLK,ASMD(0));
U_SYNC_ENC1_OUT:ASMD_OUT port map(ASMD_SELECT(1),RESET,
CLK,ASMD(1));
end state;
図4.12 STATEのVHDL（3/3）
library ieee;
use ieee.std_logic_1164.all;
entity calc is
port(DECIMAL:in std_logic_vector(9 downto 0);
OUT_A,OUT_B,ANS:out std_logic_vector(26 downto 0);
ANS_BCD8,ANS_BCD7,ANS_BCD6,ANS_BCD5,ANS_BCD4,
ANS_BCD3,ANS_BCD2,ANS_BCD1:out std_logic_vector(3 downto 0);
CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic;
SIGN,ERROR_OUT:out std_logic);
end calc;
architecture calc of calc is
signal DECIMAL_IN:std_logic_vector(9 downto 0);
signal B_STATE:std_logic_vector(28 downto 0);
signal A_OUT:std_logic_vector(26 downto 0);
signal B_OUT:std_logic_vector(26 downto 0);
signal REG_B_RST:std_logic;
図4.13 電卓のVHDL（1/4）
signal ENZAN_OUT:std_logic_vector(1 downto 0);
signal ANS_BIN:std_logic_vector(26 downto 0);
signal ADD_IN:std_logic;
signal SUB_IN:std_logic;
signal MUL_IN:std_logic;
signal DIV_IN:std_logic;
signal E_IN:std_logic;
signal C_IN:std_logic;
signal CE_IN:std_logic;
signal ADD:std_logic;
signal SUB:std_logic;
signal MUL:std_logic;
signal DIV:std_logic;
signal ANS_SEL:std_logic;
component A_S is
port(DECIMAL:in std_logic_vector(9 downto 0);
OUT_A:out std_logic_vector(26 downto 0);
OUT_B:in std_logic_vector(28 downto 0) :="00000000000000000000000000000";
ASMD:out std_logic_vector(1 downto 0);
CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic;
REGB_RST,ENZAN_ADD,ENZAN_SUB,ENZAN_
MUL,ENZAN_DIV,KIRIKAE:out std_logic);
end component;
component REGB is
port(ASMD:in std_logic_vector(1 downto 0);
REGA_OUT:in std_logic_vector(26 downto 0);
REGB_OUT:out std_logic_vector(26 downto 0);
TO_STATE:out std_logic_vector(28 downto 0);
CLK,REG_RST,ADD_EN,SUB_EN,MUL_EN,DIV_EN:in std_logic;
ERR:out std_logic);
end component;
図4.13 電卓のVHDL（2/4）