第 6 章 終わりに
付録 6 輝度データ転送出力回路
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PC_PD is
Port ( RESET : in std_logic;
CLK : in std_logic;
PD_DATA : in std_logic_vector(7 downto 0);
BIT_SELECT : in std_logic_vector(2 downto 0);
PC_PD_EN : in std_logic;
PC : out std_logic;
PD : out std_logic;
PC_PD_END : out std_logic;
MEMORY_ADDRESS : out std_logic_vector(9 downto 0));
end PC_PD;
architecture RTL of PC_PD is
signal PD_BIT_DATA_CN : std_logic_vector(10 downto 0);
signal PC_PD_END_REG : std_logic;
signal PC_REG1 : std_logic;
signal PC_REG2 : std_logic;
signal PD_REG : std_logic;
begin
--PC_OUT, PC_PD_END--
PC_PD_END <= PC_PD_END_REG;
MEMORY_ADDRESS <= PD_BIT_DATA_CN (10 downto 1);
process ( RESET, CLK, PC_PD_EN ) begin
if ( RESET = '0' or PC_PD_EN = '0' ) then
PD_BIT_DATA_CN <= ( others => '0' );
PC_PD_END_REG <= '0';
elsif ( CLK'event and CLK = '1' ) then
if ( PD_BIT_DATA_CN = "11000000000" ) then PD_BIT_DATA_CN <= "11000000000";
PC_PD_END_REG <= '1';
else
PD_BIT_DATA_CN <= PD_BIT_DATA_CN + '1';
PC_PD_END_REG <= '0';
end if;
end if;
end process;
process ( RESET, CLK ) begin if ( RESET = '0' ) then PC_REG1 <= '0';
elsif ( CLK'event and CLK = '0' ) then PC_REG1 <= PD_BIT_DATA_CN (0);
end if;
end process;
PC <= PC_REG2;
process ( RESET, CLK ) begin if ( RESET = '0' ) then PC_REG2 <= '0';
elsif ( CLK'event and CLK = '0' ) then PC_REG2 <= PC_REG1;
end if;
end process;
--PD_OUT-- PD <= PD_REG;
process ( RESET, PC_PD_EN, PD_BIT_DATA_CN (0) ) begin if ( RESET = '0' or PC_PD_EN = '0' ) then PD_REG <= '0';
elsif ( PD_BIT_DATA_CN (0)'event and PD_BIT_DATA_CN (0)
= '0' ) then case BIT_SELECT is
when "000" => PD_REG <= PD_DATA(0);
when "001" => PD_REG <= PD_DATA(1);
when "010" => PD_REG <= PD_DATA(2);
when "011" => PD_REG <= PD_DATA(3);
when "100" => PD_REG <= PD_DATA(4);
when "101" => PD_REG <= PD_DATA(5);
when "110" => PD_REG <= PD_DATA(6);
when "111" => PD_REG <= PD_DATA(7);
when others => PD_REG <= '0';
end case;
end if;
end process;
end RTL;
付録7 切換信号発生回路
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity QC is
Port ( RESET : in std_logic;
CLK : in std_logic;
QC_EN : in std_logic;
QC_END : out std_logic;
QC : out std_logic);
end QC;
architecture RTL of QC is
signal QC_REG : std_logic_vector(1 downto 0);
begin
QC <= QC_REG(0);
QC_END <= QC_REG(1);
process ( CLK, RESET, QC_REG, QC_EN ) begin
if ( RESET = '0' or QC_EN = '0' ) then QC_REG <= ( others => '0' );
elsif ( CLK'event and CLK = '1' ) then if ( QC_REG = "10" ) then
QC_REG <= "10";
else
QC_REG <= QC_REG + '1';
end if;
end if;
end process;
end RTL;
付録8 SC出力とSC_CLK出力の結合回路
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SC_OUT is
Port ( CLK : in std_logic;
RESET : in std_logic;
SC_EN : in std_logic;
BIT_SELECT : in std_logic_vector(2 downto 0);
RGB_DATA : in std_logic_vector(7 downto 0);
SC_END : out std_logic;
SC_S : out std_logic;
RGB_ADDRESS_S : out std_logic_vector(1 downto 0));
end SC_OUT;
architecture RTL of SC_OUT is component SC_CLK
Port ( CLK : in std_logic;
RESET : in std_logic;
SC_EN : in std_logic;
BIT_SELECT : in std_logic_vector(2 downto 0);
SC_CLK_OUT : out std_logic);
end component;
component SC
Port ( RESET : in std_logic;
CLK : in std_logic;
SC_EN : in std_logic;
SC_CLK_IN : in std_logic;
RGB_DATA : in std_logic_vector(7 downto 0);
SC : out std_logic;
SC_END : out std_logic;
RGB_ADDRESS : out std_logic_vector(1 downto 0));
end component;
signal SC_CLK_REG : std_logic;
begin
U0:SC_CLK port map ( CLK => CLK, RESET => RESET, SC_EN => SC_EN, BIT_SELECT =>
BIT_SELECT, SC_CLK_OUT => SC_CLK_REG );
U1:SC port map ( CLK => CLK, RESET => RESET,
SC_EN => SC_EN, SC_CLK_IN => SC_CLK_REG, RGB_DATA => RGB_DATA, SC => SC_S,
SC_END => SC_END, RGB_ADDRESS =>
RGB_ADDRESS_S );
end RTL;
付録9 LED点灯時間出力回路
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SC is
Port ( RESET : in std_logic;
CLK : in std_logic;
SC_EN : in std_logic;
SC_CLK_IN : in std_logic;
RGB_DATA : in std_logic_vector(7 downto 0);
SC : out std_logic;
SC_END : out std_logic;
RGB_ADDRESS : out std_logic_vector(1 downto 0));
end SC;
architecture RTL of SC is signal SC_REG : std_logic;
signal SC_END_REG : std_logic;
signal RGB_COUNT : std_logic_vector(7 downto 0);
signal RGB_ADDRESS_COUNT : std_logic_vector(1 downto 0);
signal SC_COUNT : std_logic_vector(3 downto 0);
signal STATE : std_logic_vector(1 downto 0);
begin
SC <= SC_REG;
SC_END <= SC_END_REG;
RGB_ADDRESS <= RGB_ADDRESS_COUNT;
process ( RESET, SC_CLK_IN, SC_EN ) begin if ( RESET = '0' or SC_EN = '0' ) then SC_REG <= '0';
SC_END_REG <= '0';
RGB_COUNT <= (others => '0');
RGB_ADDRESS_COUNT <= (others => '0');
SC_COUNT <= (others => '0');
STATE <= (others => '0');
elsif ( SC_CLK_IN'event and SC_CLK_IN = '1' ) then case STATE is
when "00" =>
SC_REG <= '1';
RGB_COUNT <= ( others => '0' );
RGB_ADDRESS_COUNT <= ( others => '0' );
SC_COUNT <= SC_COUNT + '1';
STATE <= "01";
when "01" =>
if ( RGB_COUNT = RGB_DATA ) then SC_REG <= '1';
RGB_COUNT <= (others => '0');
if ( SC_COUNT = "1100" ) then
RGB_ADDRESS_COUNT <= ( others => '0' );
SC_COUNT <= (others => '0');
STATE <= "10";
else
if ( RGB_ADDRESS_COUNT = "10" ) then RGB_ADDRESS_COUNT <= ( others =>
'0' );
else
RGB_ADDRESS_COUNT <=
RGB_ADDRESS_COUNT + '1';
end if;
SC_COUNT <= SC_COUNT + '1';
STATE <= "01";
end if;
else
SC_REG <= '0';
RGB_COUNT <= RGB_COUNT + '1';
STATE <= "01";
end if;
when "10" =>
SC_REG <= '0';
SC_END_REG <= '1';
STATE <= "10";
when others =>
STATE <= "00";
end case;
end if;
end process;
end RTL;
付録10 クロック分周選択出力回路
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SC_CLK is
Port ( CLK : in std_logic;
RESET : in std_logic;
SC_EN : in std_logic;
BIT_SELECT : in std_logic_vector(2 downto 0);
SC_CLK_OUT : out std_logic);
end SC_CLK;
architecture RTL of SC_CLK is
signal CLK_COUNT : std_logic_vector(7 downto 0);
signal Q_OUT : std_logic_vector(7 downto 0);
signal CLK_IN : std_logic_vector(7 downto 0);
begin
Q_OUT(0) <= CLK_IN(0);
Q_OUT(1) <= CLK_IN(1);
Q_OUT(2) <= CLK_IN(2);
Q_OUT(3) <= CLK_IN(3);
Q_OUT(4) <= CLK_IN(4);
Q_OUT(5) <= CLK_IN(5);
Q_OUT(6) <= CLK_IN(6);
Q_OUT(7) <= CLK_IN(7);
--CLK_COUNT--
process ( RESET, CLK, SC_EN ) begin
if ( RESET = '0' or SC_EN = '0' ) then CLK_COUNT <= (others => '0');
elsif ( CLK'event and CLK = '1' ) then if ( CLK_COUNT = "11111111" ) then CLK_COUNT <= ( others => '0' );
else
CLK_COUNT <= CLK_COUNT + '1';
end if;
end if;
end process;
--CLK_BUSYU--
process ( CLK_COUNT(0) ) begin
if ( CLK_COUNT(0) = '1' ) then CLK_IN(0) <= '1';
else
CLK_IN(0) <= '0';
end if;
end process;
process ( CLK_COUNT(1 downto 0) ) begin
if ( CLK_COUNT(1 downto 0) = "11" ) then CLK_IN(1) <= '1';
else
CLK_IN(1) <= '0';
end if;
end process;
process ( CLK_COUNT(2 downto 0) ) begin
if ( CLK_COUNT(2 downto 0) = "111" ) then CLK_IN(2) <= '1';
else
CLK_IN(2) <= '0';
end if;
end process;
process ( CLK_COUNT(3 downto 0) )
begin
if ( CLK_COUNT(3 downto 0) = "1111" ) then CLK_IN(3) <= '1';
else
CLK_IN(3) <= '0';
end if;
end process;
process ( CLK_COUNT(4 downto 0) ) begin
if ( CLK_COUNT(4 downto 0) = "11111" ) then CLK_IN(4) <= '1';
else
CLK_IN(4) <= '0';
end if;
end process;
process ( CLK_COUNT(5 downto 0) ) begin
if ( CLK_COUNT(5 downto 0) = "111111" ) then CLK_IN(5) <= '1';
else
CLK_IN(5) <= '0';
end if;
end process;
process ( CLK_COUNT(6 downto 0) ) begin
if ( CLK_COUNT(6 downto 0) = "1111111" ) then CLK_IN(6) <= '1';
else
CLK_IN(6) <= '0';
end if;
end process;
process ( CLK_COUNT(7 downto 0) ) begin
if ( CLK_COUNT(7 downto 0) = "11111111" ) then