INVITED PAPER
Special Section on Electronic DisplaysUncooled Infrared Radiation Focal Plane Array with Low Noise
Pixel Driving Circuit
Risako UENO†a), Hiroto HONDA†, Honam KWON†, Koichi ISHII†, Masako OGATA†, Hitoshi YAGI†, Ikuo FUJIWARA†, Kazuhiro SUZUKI†, Keita SASAKI†, and Hideyuki FUNAKI†, Nonmembers
SUMMARY We have analyzed the dominant noise sources in the driv-ing circuit of an uncooled infrared radiation focal plane array fabricated on a silicon-on-insulator (SOI) substrate by 0.35 μm CMOS technology and bulk- micromachining. We found no noise property of SOI-MOSFET in-ferior compared to those of NMOSs formed on SOI and bulk substrate, respectively. In addition, we reduced the total noise of the sensor chip by designing the current source NMOS sufficiently large, and optimized the operating current of pixel pn-junctions.
key words: infrared, focal plane array, MEMS
1. Introduction
Recently, many kinds of microelectromechanical system (MEMS)-based sensor devices, such as acceleration sensors and pressure sensors, have been developed. Among them, the uncooled infrared radiation (IR) focal plane array (FPA), utilizing MEMS technologies for pixel structures, has at-tracted wide interest because of its potentially wide appli-cation field [1], [2].
The uncooled IRFPA is an imaging device, which con-verts the temperature rise of each pixel caused by inci-dent infrared absorption into electric signal with thermo-electric converters. Usually, both the IR absorbing struc-ture and thermoelectric converter in a pixel are thermally isolated from the substrate by surface-micromachining or bulk-micromachining techniques. Such thermally isolated pixel structure is essential for converting small IR irradia-tion to a sufficiently large pixel temperature rise [3].
To diversify the application of uncooled IRFPAs from the current security/surveillance, automotive, and defense fields to the future mass market, the next-generation IRFPA requires further system size/cost reduction, scale-up of the pixel number, and signal-to-noise ratio (SNR) improvement. In this paper, we focus on the SNR improvement by reduc-ing the noise of analog pixel drivreduc-ing circuits formed on SOI substrate. We analyzed the noise of constant current source MOSFET formed on SOI substrate, which was one of the dominant noise sources in our IRFPA chip [4].
Manuscript received March 2, 2010. Manuscript revised June 11, 2010.
†The authors are with Toshiba Corporate Research &
Develop-ment Center, Kawasaki-shi, 212-8582 Japan. a) E-mail: [email protected]
DOI: 10.1587/transele.E93.C.1577
2. Sensor Design and Noise Models 2.1 Sensor and Pixel Design
Figure 1 shows the optical micrograph of the sensor chip, and the top view of 3 by 2 IR detection pixels. The imaging area contains 160× 120 IR detecting pixels. The on-chip driving and readout circuit area contains the vertical and the horizontal registers, and the integration read-out circuit.
Figure 2 shows the cross-sectional image of an IR tecting pixel, driving circuit, and read-out circuit. The de-vices were fabricated on SOI substrate with 400 nm-thick silicon layer and 150 nm-thick buried oxide layer. The
cen-Fig. 1 Schematic cross section of an IR detection pixel, the read-out circuit, and the driving circuit.
Fig. 2 Schematic cross section of an IR detection pixel, the read-out circuit, and the driving circuit.
tral part of the pixel is the IR absorbing cell, which is ther-mally isolated by anisotropic etching of silicon substrate be-neath the cell. The driving circuit and the reading circuit are formed on the side of pixel area.
The absorbing films consisting of silicon dioxide and silicon nitride on the cells absorb the incident infrared light, which generates the temperature variation of several mK while a target has temperature difference of 1 K. Twelve p-n jup-nctiop-ns ip-n a sep-nsor cell are formed ip-n the sip-ngle-crystal SOI layer and serially connected, which work as thermo-electric converters. Those p-n junctions, which are based on standard CMOS technology, could show better unifor-mity of detector characteristics and lower noise property than those of other bolometer devices [5].
2.2 Current Source Driving of Pixels
The pixel driving and read-out circuit and their operation based on the column parallel architecture are shown in Fig. 3. At the beginning of one vertical line period, the integrating capacitor is charged at constant reset voltage (Vreset DC) with Vreset pulse. Then the vertical shift regis-ter supplies the bias voltage to IR detection p-n junctions with Vclkpulse. The constant current (If) is supplied to the biased p-n junctions by the constant current source. The vertical signal line voltage reflecting to the p-n junctions forward voltage (Vf) changes the gate voltage of the col-umn amplifier via the coupling capacitor. The stored charge in the integrating capacitor flows through the drain-source of the column amp to the ground according to the amplifier gate voltage. At the end of the integration, the voltage of the integrating capacitor is read out by the horizontal shift register (Hsel).
The serially connected 12 p-n junctions are driven by the constant current source SOI-MOFET. The If of the se-ries diodes is described as follows;
If = A0T(3+γ/2)exp −Eg kT exp qVf nkT − 1 (1)
Fig. 3 The schematic of the series p-n diodes driving circuit, the read-out circuit, and the timing diagram.
where A0is the temperature-independent constant value, T is the temperature, Egis the energy band gap of Si, k is the Boltzmann constant, q is the elementary charge, Vf is the p-n junction diode forward voltage, and n is the number of series diodes [6].
When If is constant, temperature (T ) rise of the diodes by the IR irradiation decreases the diode forward voltage (Vf). From the Eq. (1), this variation of the diode for-ward voltage by the temperature change (dVf/dT) is approx-imately described as follows:
dVf dT − nk q − ln(If)+ 3+γ 2 (ln(T )+1)+ln(A0) (2) In the IRFPA chip, this change of forward voltage (dVf) is amplified by the column amplifier and then read out as an IR signal voltage.
The dVf is as slight as only 100 μV of Vf shift accord-ing to the Eq. (1). So the current noise contamination gener-ated in the constant current source MOSFET should be suf-ficiently small for sensing highly accurate Vf shift, which determines the temperature resolution.
2.3 Low-Frequency Noise of MOSFET
The dominant noise at the low-frequency operation of MOS-FET or pn-junction is often called 1/f noise (also called
flicker noise) because it is known to be inversely propor-tional to the frequency. In particular, MOSFET is known to generate relatively high noise originating from the trapping and detrapping of carriers at the defects in the interface be-tween the gate oxide and the silicon substrate. The 1/f noise of Si pn-junction in forward operation is also known [7]. However, in our IRFPA, forward current of pn-junctions was designed to go through the single-crystal silicon to avoid ex-cess noise generation from the interface traps. So the noise level of the pn-junctions is much lower than that of MOS-FET.
The 1/f noise of MOSFET is modeled as noise cur-rent power spectral density (PSD) (Sid(A2/Hz) in BSIM3v3 Spice2 model resolution [8].
Sid=
KF COXL2
IAFD
fEF (3)
where IDis the drain current density, Cox is the capacity of the gate oxide per unit area, L is the gate length (effective channel length), and f is the frequency. KF, AF, and EF are empirical parameters specified by process conditions. In particular, the proportional factor KF is known to depend strongly on the fabrication process and substrate. The root mean square (RMS) current noise (If n(A)) is often utilized to estimate the effect of noises and it is determined by inte-grating Sidin the band width ( f1– f2) as follows:
If n= f2 f1 Siddf = f2 f1 KF CoxL2 IAF D fEFdf (4)
2.4 Noise from Current Source
Due to such current noises (If n), the diode forward current and diode forward voltage are swung, which are converted to the noise Vf nas follows:
Vf n= dVf dIf × I f n nkT q If n If (5) where dVf/ dIf is the dynamic resistance of series diodes. In our IRFPA chip, the high-frequency noise could be can-celled sufficiently because the signal from pixels is inte-grated in the integrating capacitor for several tens of mi-croseconds as shown in Fig. 3. However, the low- frequency noise could not be canceled by the circuit itself, which caused SNR degradation.
This paper focuses on the noise of MOSFET formed on SOI, because there have been few reports to evaluate the SOI-MOSFET noise in the case of the combination of the pn- junction for the analog sensor devices. The effects of substrates and the design of the MOSFET were examined to evaluate the SOI-MOSFET noise characterization. Then, the influence on the IRFPA SNR was also estimated as de-scribed in the following section.
3. Characterization of SOI-MOSFET Noise 3.1 Noise Measurement
Noise current power spectral density (PSD) was measured with the spectrum analyzer, the low-noise bias source, and the low-noise amplifier unit. The measurement system was shielded enough to prevent the measurement noise contam-ination.
To measure the MOSFET noise at the same condition as driving pixels in the chip, drain-source current (Ids) was kept constant during measurement. The Ids condition was varied from 1 to 100 μA by changing the gate voltage to re-veal the effect of the drain current value on the noise. The drain voltage was fixed at 4.0 V throughout all measure-ments.
3.2 Comparing SOI and Bulk Substrates
To confirm the influence of substrates, the noise of the NMOS formed on SOI and bulk substrates were measured, respectively. Both were formed in the identical CMOS pro-cess for the comparison. The gate sizes of the NMOS were designed to be 5 μm in length and 30 μm in width.
Figure 4 shows the measured current noise PSD of NMOS fabricated on the SOI and the bulk substrates at 10 Hz as a function of drain current. The remarkable de-terioration of the noise property in the SOI was not found in the measurement. The Sidwas proportional to Ids1.12. 3.3 Gate Size Dependence
In order to investigate the influence of the gate size, we mea-sured noise current PSD at 10 Hz of SOI-NMOS made for the designed gate sizes (gate length L=1.5–10 μm, and gate width W=2–10 μm).
The noise measurement results of NMOS are shown
Fig. 4 Measured noise current power spectral density of NMOS (W/L=30/5 μm) formed on SOI as a function of the drain current at 10 Hz, compared with that of bulk substrates.
in Fig. 5 in relation to the gate length. Within these ranges of gate size, noise current PSD was almost inversely pro-portional to the square of the gate length, and showed little dependence on the gate width, which implies that the fitting by the Eq. (3) was admissible.
Therefore, supposing that Sid was proportional to the square of the gate length, empirical parameters (KF, AF, EF) were determined by fitting the measured noise current PSD of NMOSs (L=1.5, 2.5, 10 μm, W=10 μm). As a result, KF, AF, and EF were 3.50× 10−27, 1.12, and 0.89, respectively. 4. Chip Output Noise
4.1 Chip Output Noise Measurement
The SNR differences regarding the gate length and drain current value of the constant current source NMOS were also examined with our sensor chip. We developed sev-eral test circuits with different gate length of constant cur-rent source on the sensor chip for this examination.
In this measurement, the change in standard deviation of the IRFPA camera output digital signal was measured in the condition of no IR irradiation to the chip. The 600 frame data of 160× 120 pixels output value were utilized for the noise evaluation.
4.2 Noise Decrement by the Driving Current and Gate Length
Figure 6 shows the normalized noise from the current source as a function of the drain current of the current source at the gate length of 5, 11, and 22 μm. At the same drain current, the amount of the output noise decreased as the gate length increased. At each gate length, the noise decreased as the current value increased.
For the long gate sample, the noise value was saturated in the region of large current value. This could be attributed to the current source noise decrease below the other noise sources (ex. column amplifier, camera, etc.) Therefore, the noise from the current source NMOS was no longer predom-inant to determine the SNR of this IRFPA chip.
Fig. 5 Measured noise current power spectral density of SOI-NMOS at 10 Hz, W=10 μm as a function of gate length.
4.3 Trade-Off between Noise and Sensitivity
It should be noted that the IR sensitivity degrades as the constant current increases. From Eq. (2), the thermoelec-tric coefficient dVf /dT decreases as the constant current (If) increases. For instance, dVf/dT decreases by 14% as the
If increases from 1 μA to 10 μA at the 30◦C. However, the rate of the noise ( ¯Vf n) decreases by increasing If is always higher than the rate of sensitivity decrease from Eqs. (2) and (5). Then the sensor SNR was improved by increasing If.
Actually, considering the negative effect from other noise sources, the sensitivity degradation by If increasing amplified the impact of other noise sources on the SNR degradation. This indicates that the best current condition was determined to find the condition in which the current source noise was almost equal to the noise floor determined from other noises.
Moreover, the large If correspondent to the large Vf needs the large bias voltage. However, there is generally the restriction of the power-supply voltage.
5. Optimization Result of SNR
Based on the result of the precedent chip output noise decre-ments, we developed the new IRFPA chips with different current source gate design to examine the SNR improve-ment. Though we designed imaging area with further scale-up of pixel number (320× 240) simultaneously, the driving and the read-out circuit design were identical with the pre-vious design as shown in Fig. 3, with the exception of the current source gate length.
Figure 7 shows the measured NETD of the new IRFPA chip with the current source gate length of 5 μm and 22 μm at the identical operation driving condition.
The NETD was improved from 0.55 K (the average value of several chips) with the gate length 5 μm to 0.25 K
Fig. 6 Normalized noise from the current source as a function of the drain current of current source.
Fig. 7 Measured NETD of the IRFPA chips with constant current source gate L=5 μm, 22 μm, respectively. The error bars show the intra-chip vari-ability.
Table 1 Specification of 320× 240 uncooled IRFPA.
Fig. 8 Thermal image obtained with our 320× 240 uncooled IRFPA.
with the gate length 22 μm.
Finally, the specification of our IRFPA chip with 22 μm current source gate is summarized in Table 1 and the ob-tained thermal image is shown in Fig. 8. The obtained NETD 0.25 K was not so advanced compared with the prior works [1], [2]. However, it is possible to improve the NETD
further by decreasing the noise from other noise sources and uging digital filters.
6. Conclusion
We have analyzed the noise from the constant current source, which was the predominant noise source in the driv-ing circuit of uncooled IRFPA fabricated on SOI substrate by 0.35 μm CMOS technology and bulk- micromachining.
Remarkable noise difference between SOI and bulk substrates was not found in our process. The noise current PSD was inversely proportional to square of the gate length (L2) and dependence on the gate width was slight.
In the IRFPA chip (160× 120 pixels), the noise reduc-tion was also confirmed by increasing the gate length and the current value. For the gate length of 22 μm, the maxi-mum improvement of SNR was 3 times compared with the 5 μm of the gate current source.
In the further scale-up of pixel number (320× 240) IRFPA chip, the NETD was improved from 0.55 K (the av-erage value of several chips) with the gate length 5 μm to 0.25 K with the gate length 22 μm.
Acknowledgments
Authors would like to thank I. Amemiya and K. Kawabata of Toshiba Corporation for giving permission for this work, and R. Okamoto of Toshiba Corporation Semiconductor Company for supporting this research.
References
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Risako Ueno received the B.E. and M.E. degrees from Tokyo Institute of Technology in 2005 and 2007, respectively and joined the Elec-tronic Imaging Laboratory of Toshiba Research and Development Center, Japan. She has been engaged in the research of CMOS imaging de-vices.
Hiroto Honda received the B.E. degree in physics engineering from the Tokyo University in 2003 and joined the Advanced Electron vices Laboratory of Toshiba Research and De-velopment Center, Kawasaki, Japan. He has been working on the device technology for un-cooled IR imager and CMOS image sensor.
Honam Kwon received B.S. degree in con-trol and instrumentation engineering from Ko-rea University in 2000, and M.S. degree and Ph.D. degree in mechatronics engineering from Gwangju Institute of Science and Technology, Gwangju, Korea in 2002 and 2006, respectively. After joining the Electronic Image Laboratory of Toshiba Research and Development Center in 2008, he has worked on development of un-cooled IR imager and CMOS image sensor.
Koichi Ishii received the B.E. degree in medical engineering from the Keio University in 1991 and joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan. Since 2007 he has been engaged in the research and development of uncooled IR image sensor.
Masako Ogata received her M.S. degree from Hokkaido University, Japan, in 2006. She joined Toshiba corporate R&D center in 2006. Her research interest includes capacitance sen-sor and uncooled IR image sensen-sor.
Hitoshi Yagi received the B.E. and M.E. de-grees in applied physics from the Waseda Uni-versity in 1987 and 1989, respectively. In 1989, he joined Toshiba Corporate Research and De-velopment Center, Kawasaki, Japan. He’s been engaged in the development of semiconductor functional device, inkjet printing process and liquid toner electro-photographic process. He is presently working on the process technology for uncooled IR imager.
Ikuo Fujiwara received the B.E. degree in physics engineering from the Tsukuba Uni-versity in 1992 and joined the Toshiba Research and Development Center, Kawasaki, Japan. He is presently engaged in research and develop-ment of uncooled IR image sensor.
Kazuhiro Suzuki received the B.E., M.E. and Ph.D. degrees from Tokai University, Japan, in 2000, 2002, and 2008, respectively. He jointed Corporate Research and Development Center, Toshiba Corporation in 2002. He has been engaged in the research and development of SOI-based CMOS-MEMS integration tech-nology. Dr. Suzuki is a member of the Japan Society of Applied Physics.
Keita Sasaki received the M.E. degree in electrical and electronic engineering from the Iwate University, Morioka, Japan, in 2004. In 2004, he joined the Advanced Electron Devices Laboratory of Toshiba Research and Develop-ment Center, Kawasaki, Japan. He has been en-gaged in the research and development of un-cooled IR imager.
Hideyuki Funaki received his Ph.D. degree from Tokyo Institute of Technology in 1992. He joined Toshiba corporate R&D center in 1992, and has been engaged in the research of semi-conductor devices and image sensors. He is a member of the Japan Society of Applied Physics and the Institute of Electrical and Electronics Engineers.
