学 位 論 文 題 名 Studies on Dependable Sequential Circuits under Highly Electromagnetic Environment

氏 名 Aromhack

SAYSANASONGKHAM

所 属 システムデザイン研究科 システムデザイン専攻 学 位 の 種 類 博士（工学）

学 位 記 番 号 シス博 第 74 号 学位授与の日付 平成 28 年 3 月 25 日 課程・論文の別 学位規則第４条第１項該当

学 位 論 文 題 名 Studies on Dependable Sequential Circuits under Highly Electromagnetic Environment

（高電磁環境下におけるディペンダブル順序回路に関する研究）

論 文 審 査 委 員 主査 教 授 福本 聡 委員 教 授 岩崎 一彦 委員 教 授 三浦 幸也

委員 教 授 蓑原 隆(拓殖大学)

【論文の内容の要旨】

Integrations of power systems and ICT (Information and Communications Technology) are becoming more common and can be found in modern technology such as smart grid, PV (Photo Voltaic) and EV (Electric Vehicle). Meanwhile, power converter devices utilized in these technologies are evolving rapidly. They have reached a new level with extremely high switching speed, higher power density and higher voltage. They are now capable of being built in a very compact and highly densified circuit. In some cases, these devices are located nearby or integrated on the same board with sequential circuits such as processors and controller circuits. However, power converter devices are known for their noise issue. The noise is generated from the switching activity of the MOSFET in the main power circuit. It is created in a form of conductive noise and near-field (radiative) noise due to high current pulse.

Therefore, without a proper countermeasure the noise may affect the operations of the surrounding circuits.

Conventionally, EMC (Electro-Magnetic Compatibility) technique is utilized to

handle the noise in power converter devices. It is a design technique to decrease

the emission of unwanted noise and improve the immunity of the circuit to guarantee

correct operations in the presence of undesirable noise. In addition EMC technique

also involves shielding, grounding and noise filtering. However, as the devices are getting more miniaturized and highly densified, implementation of such methods is more difficult. Furthermore, question on tradeoffs between the cost and the effectiveness, particularly with strong noises that the power device may generate, still remains unanswered.

As a challenge towards novel technical diversities to combine or substitute with EMC technique, this paper discusses on dependable methods for sequential circuits in the two following scenarios. First is the case when a sequential circuit is located nearby a power converter circuit. For this scenario, we investigate for a fault-tolerant method to handle the effect of near-field noise. Second is the case when a sequential circuit is integrated with the power converter circuit. In this case, both near-field noise and conductive noise are considered in the fault model and fault-tolerant techniques are explored accordingly.

This dissertation is organized as follows:

Chapter 1 discusses the overall content of the dissertation.

Chapter 2 describes an introduction to power converter devices and their noise issue.

Along with the basic idea of how the EMC technique is implemented, its tradeoffs between the cost and effectiveness are also discussed. This chapter also describes the existing fault-tolerant techniques for sequential circuits and explains why the traditional methods are not capable of handling the noise from the power devices.

The concept of the fault model and some assumptions for this research are also described in this chapter.

In chapter 3, we present a fault-tolerant scheme for a processor, which a power converter device is located nearby. It employs a BIST (Built-in Self Test) circuit to measure the duration of the noise at power-on sequence. After the test is done, the system transfers to the normal mode operation. During the normal mode, by employing the clock-gating technique the system uses the measured noise duration value to cancel the clock supply for the processor in order to avoid noise whenever it may approach.

The controller of the converter device informs the noise generation timing and correspondingly the clock signal is cancelled. We also present a test policy to avoid underestimation of the noise duration due to fault masking and noise variations issue.

The simulation results show that with the test policy, the proposed method can

accurately measure the noise duration and set an appropriate clock-gating period.

This chapter further discusses on the area overhead evaluation to verify the applicability of the proposed scheme.

In chapter 4, we present a technique using an adaptive sampling method for highly reliable digital control power converter. Experimental results show that conductive noise from the main circuit can affect the operation of the controller circuit, resulting in incorrect control. As a countermeasure, a sampling method that adaptively tunes the sampling points based on the duty ratio to avoid the noise is proposed.

We initially verify the effectiveness of the proposed method through simulation evaluations. Then we implement the proposed adaptive sampling method on an FPGA and conduct an experiment. The experimental results show the effectiveness of the proposed method, where the controller can successfully avoid noise and correctly control the power converter circuit.

In chapter 5, we assume the effect of radiative noise on a controller of power converter device, which is implemented on an FPGA, and as a countermeasure we present a dual-FPGA architecture with mutual cooperation in recovery mode. It composes of two FPGAs operating identical tasks. When one FPGA is affected by noise, another FPGA can still operate the system while the faulty one executes reconfiguration to fix the error. During the recovery phase the FPGAs mutually cooperate by sharing state information. This allows the affected FPGA to recover to the normal operation even faster. In this chapter, we further provide an analytical evaluation of the reliability of the system. A Markov Chain model is utilized for the analysis, where the results show much higher reliability for the proposed architecture in comparison to a single FPGA architecture and a dual-FPGA architecture without mutual cooperation in recovery mode.

Chapter 6 concludes the dissertation and summarizes the contributions of our work.

The remaining issues for future study and exploration are also discussed in this

chapter.