SWITCHING FREQUENCY (Hz)

Design of a QR Adapter with Improved

Efficiency and Low Standby Power

Agenda

1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

Agenda

1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

What is Quasi-Square Wave Resonance ?

• MOSFET turns on when V

(t) reaches its minimum value.

¾ Minimizes switching losses

¾ Improves the EMI signature

MOSFET turns on in first valley MOSFET turns on in second valley

valley

Quasi-Resonance Operation

• In DCM, V_DS must drop from (V_in + V_reflect) to V_in

• Because of L_p-C_lump network Æ oscillations appear

• Oscillation half period:

V_in + V_reflect

V_in V_DS

Lp

Vin

SW Clump

Rload Cout

1 : N Vout

VDS Vin

x p lump

t = π L C

A Need to Limit the Switching Frequency

• In a self-oscillating QR, F

increases as the load decreases

• 2 methods to limit F

:

– Frequency clamp with frequency foldback – Changing valley with valley lockout

Higher losses at light load if F

is not limited

Frequency Clamp in QR Converters

‰ In light load, frequency increases and hits clamp

¾ Multiple valley jumps

¾ Jumps occur at audible range

¾ Creates signal instability

Second valley First valley QR mode

Agenda

1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

0 10000 20000 30000 40000 50000 60000 70000 80000

0 10 20 30 40 50 60

OUTPUT POWER (W)

SWITCHING FREQUENCY (Hz)

1^st 2^nd

3^rd 4^th

VCO mode

QR operation

The Valley Lockout

• As the load decreases, the controller changes valley (1^st to 4^th valley in NCP1380)

• The controller stays locked in a valley until the output power changes significantly.

1 2 3 4

VCO mode

– No valley jumping noise

– Natural switching frequency limitation

The Valley Lockout

• FB comparators select the valley and pass the information to a counter.

• The hysteresis of FB comparators locks the valley.

• 2 possible operating set points for a given FB voltage.

V_FB decreases (P_OUT decreases) V_FB increases (P_OUT increases)

1^st 2^nd 3^rd 4^th VCO

3.2 2.0 2.8

0.8 1.2 1.6 _2.4 V_FB (V)

Agenda

1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

• Operating modes:

– QR current-mode with valley lockout for noise immunity – VCO mode in light load for improved efficiency

• Protections

– Over power protection – Soft-start

– Short circuit protection – Over voltage protection

– Over temperature protection – Brown-Out

NCP1379/1380 Features

HV-bulk

Dovp ZCD / OPP

1 2 3

4 5

8

6 7

NCP1380 C/D

FB CS Rzcd1

GND

Rzcd2 Czcd Rstart

Ct

Cvcc Ct

DRV Vcc OVP/BO

Rbol Rbou

‰ Mass production: Q4 2009

QR Mode with Valley Lockout

• Operating principle:

– Locks the controller into a valley (up to the 4^th) according to FB voltage.

– Peak current adjusts according to FB voltage to deliver the necessary output power.

1 2 3 4

VCO mode

• Advantages

– Solves the valley jumping instability in QR converters

– Achieves higher min F_sw and lower max F_sw than in traditional QR converters – Reduce the transformer size

Fsw (Pout) for a 60 W adapter

0.00E+00 2.00E+04 4.00E+04 6.00E+04 8.00E+04 1.00E+05 1.20E+05 1.40E+05

0 10 20 30 40 50 60

Pout (W)

Fsw (Hz)

1^st 2^nd

3^rd 4^th

QR operation VCO

mode

VCO Mode

• Occurs when V_FB < 0.8 V (P_out decreasing) or V_FB < 1.4 V (P_out increasing)

• Fixed peak current (17.5% of I_pk,max), variable frequency set by the FB loop.

Constant peak current (17.5% of I_pk max)

F_sw1@ P_out1 F_sw2@ P_out2 P_out1> P_out2

I_pk max

Combined ZCD and OPP

• Zero-Crossing Detection (ZCD) and Over Power Protection (OPP) are achieved by reading the Aux. winding voltage

– ZCD function used during the off-time of MOSFET (positive voltage).

– OPP function used during the on-time of MOSFET (negative voltage)

2 1

0 V

50 mV

Possible restarts for ZCD V_OPP

V_DRV V_ZCD

0.8 V + Vopp

ZCD/OPP IpFlag

+

0.8 V

+ -

ESD protection Aux

Ropu

Ropl

1 Rzcd

CS

+ - Vth

DRV Tblank

leakage blanking

Demag

NCP1380 Versions

• 4 versions of NCP1380: A, B, C and D

X X

NCP1380 / X D

X X

NCP1380 / X C

X X

NCP1380 / X B

X X

NCP1380 / X A

Latched

Over current protection

Auto-Recovery

Over current protection

BO OVP

OTP

OTP: Over Temperature Protection OVP: Over Voltage Protection BO: Bown-Out

Short-Circuit Protection

• Internal 80 ms timer for short-circuit validation.

• Additional CS comparator with reduced LEB to detect winding short-circuit.

• V_CS(stop) = 1.5 * V_ILIMIT

ZCD/OPP

Laux CS

Rsense

LEB1 +

-

grand reset IpFlag

PWMreset

Up Down

TIMER

Reset FB/4

OPP

V_ILIMIT

+ - LEB2

V_CS(stop)

CsStop

DRV S

R Q Q

Stop controller

S

R Q Q

CS after LEB1 +

-

S

R Q Q

Vcc aux

management

latch

Vdd

fault

grand reset

grand reset

DRV

IpFlag +

-

PWMreset

Up Down

TIMER

Reset

VCCstop

FB/4

V_ILIMIT

V_OPP+

+ - V_CS(stop)

CS after LEB2 CSstop

t_LEB2 < t_LEB1

VCC

CSstop

Short-Circuit Protection (A and C versions)

• A and C versions: the fault is latched.

– V_CC is pulled down to 5 V and waits for ac removal.

SCR delatches when

I_CC< ICC_LATCH

• Auto-recovery short circuit protection: the controller tries to restart

• Auto-recovery imposes a low burst in fault mode.

V_DS

V_CC

Low average input power in fault condition

Short Circuit Protection (B and D)

S

R Q Q

+ -

Vcc Vdd aux

fault

grand reset to DRV stage

IpFlag +

-

+ -

PWMreset

Up Down

TIMER

Reset

VCCstop CS after LEB1

FB/4

V_ILIMIT V_OPP+

CS after LEB2

t_LEB2< t_LEB1

CSstop

V_CS(stop)

grand reset

management VCC

Fault Pin Combinations

• OVP and OTP or OVP and BO combined on one pin.

• Less external components needed.

time V_Fault

OK Latch!

Latch!

time V_Fault

OK BO Latch!

• OVP / OTP

– NCP1380 A & B versions

• OVP / BO

– NCP1380 C & D versions, NCP1379

Agenda

1. Quasi-Resonance (QR) Generalities 2. The Valley Lockout Technique

3. The NCP1379/1380

4. Step by Step Design Procedure

5. Performances of a 60 W Adapter Featuring

Valley Lockout

Step by Step Design Procedure

• Calculating the QR transformer

• Predicting the switching frequency

• Implementing Over Power Compensation

• Improving the efficiency at light load with the VCO mode

• Choosing the startup resistors

• Implementing synchronous rectification

Design Example

• Power supply specification:

– V_out = 19 V – P_out = 60 W

– F_sw,min = 45 kHz (at V_in = 100 Vdc) – 600 V MOSFET

– V_in = 85 ~ 265 Vrms

– Standby power consumption < 100 mW @ 230 Vrms

T1

. .

Vout

Gnd Vbulk

Turns Ratio Calculation

,

ds max dss D

V = BV k

‰ Derate maximum MOSFET BV_dss:

‰ For a maximum bulk voltage, select the clamping voltage:

‰ Deduce turns ratio:

, ,

clamp ds max in max os

V = V − V − V

( )

c out f

s ps

p clamp

k V V N N

N V

= = +

BV_dss V_ds,max

V_clamp

V_bulk,max

15% derating V_os

V_reflect

k_c: clamping coef.

k_c = V_clamp / V_reflect)

V_os: diode overshoot k_D: derating factor

How to Choose k

• k_c choice dependant of L_leak (leakage inductance of the transformer)

• k_c value can be chosen to equilibrate MOS conduction losses and clamping resistor losses.

1

out c

Rclamp leak

c

P k

P k

η k

= −

2

, 2

, , ,

4 1

3

out c

MOS on dson

in min in min dss D in max os

P k

P R

V V BV k V V

η

⎛ ⎞

= ⎜⎜⎝ + − − ⎟⎟⎠

1.2 1.5 1.8 2.1 2.4 2.7 3

0 1 2

3 600-V MOSFET

P_Rclamp

P_MOS,on@ V_in,min

Ploss(W)

k_c P_tot ≈ 2.5 W

k_leak=0.005 k_leak=0.008 k_leak=0.01

Curves plotted for:

R_dson = 0.77 Ω at T_j = 110

°C

P_out = 60 W

V_in,min = 100 Vdc

Primary Peak Current and Inductance

, ,

,

pri peak pri pri peak pri ps

sw pri lump

in min out f

I L I L N

T L C

V V V

π

= + +

‰

‰

out 2 pri pri peak sw

P = L I F

η

,

1 2

2

pri peak

in,min out f

N P C F

I P

V V V π

η η

⎛ ⎞

= ⎜ ⎜ ⎝ + + ⎟ ⎟ ⎠ +

2

pri

pri peak sw

L P

I F η

=

t_on t_off

t_v I_pri,peak

t_on t_off

t_v 0

DCM

C_oss contribution alone.

RMS Current

• Calculate maximum duty-cycle at maximum P_out and minimum V_in:

• Deduce primary and secondary RMS current value:

, ,

3

max pri rms pri peak

I = I d

, ,

1 3

pri peak max

sec rms

ps

I d

I N

= −

,

, ,

pri peak pri

max sw min

in min

I L

d F

= V

I_pri,rms and I_sec,rms Losses calculation

Design Example

, , ,

3.32 0.43 1.26

3 3

max

pri rms pri peak pri rms

I = I d = ⇒ I = A

,

, ,

1 3.32 1 0.43 3 0.25 3 5.8

pri peak max

sec rms sec rms

ps

I d

I I A

N

− −

= = ⇒ =

,

, ,

3.32 285

45 0.43

100

pri peak pri

max sw min max

in min

I L µ

d F k d

V

= = × ⇒ =

,

( ) 1.3 (19 0.8)

600 0.85 375 10 0.25

c out f

ps ps

Vdss D in max os

k V V

N N

B k V V

+ × +

= = ⇒ ≈

− − × − −

,

,

2 1 2

2 60 1 0.25 2 60 250 45 0.85 100 19.8 0.85 3.32

ps out lump sw

out pri peak

in,min out f

pri peak

N P C F

I P

V V V

p k

I A

η π η

π

⎛ ⎞

= ⎜⎜⎝ + + ⎟⎟⎠+

× ⎛ ⎞ × × ×

= ⎜⎝ + ⎟⎠+ ⇒ =

2 2

,

2 2 60

3.32 45 0.85 285

out

pri pri

pri peak sw

L P L µH

I F η k

= = × ⇒ =

× ×

‰ Based on equations from slides 11 to 14:

¾ Turns ratio:

¾ Peak current:

¾ Inductance:

¾ Max. duty-cycle:

¾ Primary rms current:

¾ Secondary rms current:

Predicting the Switching Frequency

• The controller changes valley as the load decreases.

=> How can we predict the switching frequency evolution as the load varies ?

• Depending upon the power increase or decrease, the FB levels at which the controller changes valley are different => valley lockout

2

,

1

2 4

FB prop

out p in dc sw

sense p

V t

P L V F

R L

η

⎛ ⎞

= ⎜⎜⎝ + ⎟⎟⎠

Predicting the Switching Frequency

• Knowing the FB threshold values, we can calculate F

evolution and the corresponding P

.

( )

,

,

1

1 1 2

4 π

= ⎛ ⎞ ⎛ ⎞

+ + + +

⎜ ⎟ ⎜ ⎟

⎜ ⎟ ⎜ + ⎟

⎝ ⎠ ⎝ ⎠

sw

prop ps

FB

in dc p p lump

sense p in dc out f

F

t N

V V L n L C

R L V V V

Replace V_FB by the valley thresholds values in the previous slide

Predicting the Switching Frequency

• Calculate by hand (using the previous equations) or use the Mathcad spreadsheet to deduce the maxima of the switching frequency => EMI

0 20 40 60

2 10× ⁴ 4 10× ⁴ 6 10× ⁴ 8 10× ⁴ 1 10× ⁵

sw ve sus ou V N

F sw(Hz)

P_out (W)

1^st 2^nd

3^rd 4^th

1^st 2^nd

3^rd 4^th

VCO mode

VCO mode

P_out decreases P_out increases 95 kHz

90 kHz 93 kHz

83 kHz

FB

Ct ICt

VCO

+ -

S

R Q Q Vdd

Vdd

Ct discharge Rpullup

DRV

CS comparator 6.5-(10/3)Vfb

VFBth

VCO Mode

• The switching frequency is set by the end of charge of C_t capacitor

• The end of charge of C_t capacitor is controlled by the FB loop

(Timing capacitor voltage) Load

V_Ct Controlled by FB loop

Enable VCO mode

C_t

4

Valley to VCO Mode Transition

• Output load slightly decreases:

0.8 V 1.4 V

V_FBth V_FB

4^thvalley VCO mode

Load

T_sw1

T_sw2

How to Calculate C

Capacitor ?

• Switching frequency at the end of the 4^th valley operation (V_FB = 0.8 V):

, ,

,

0.8 2 1

4 2 7

in max ps

sw 4th VCO prop p p OSS

sense p in max out f

V N

T t L L C

R L V V V

π

−

⎛ ⎞ ⎛ ⎞

= ⎜⎜⎝ + ⎟⎟⎠ ⎜⎜⎝ + + ⎟⎟⎠+

• T_sw gap between 4^th valley and VCO mode must not exceed 10 µs (based on lab experiments) for V_FB = 1.4 V (hysteresis):

, ,

10

sw VCO sw 4th VCO

T = T

+ µs

,

1.83

Ct sw VCO t

C = I T

• The relationship between V_FB and V_Ct is:

( )

6.5 (10 / 3) 6.5 10 / 3 1.4 1.83V

Ct FB

V = − V = − × =

C

Design Example

• Switching frequency at the end of the 4^th valley operation :

,

0.8 265 2 1 0.25

300 285 7 285 250

4 0.23 285 265 2 19 0.8

10.7

sw 4th VCO

T n µ µ p

µ µs

− π

⎛ ⎞ ⎛ ⎞

= ⎜⎜⎝ × + ⎟⎟⎠ ⎜⎝ + + ⎟⎠+ ×

=

• T_sw gap between 4^th valley and VCO mode must not exceed 10 µs (based on lab experiments):

, , 10 10.7 10 20.7

sw VCO sw 4th VCO

T =T ₋ + µs = µ+ µ = µs

, 20 20.7

1.83 1.83 226

Ct sw VCO t

I T µ µ

C = = × = pF

• The timing capacitor value is:

• Finally, we choose C_t = 200 pF

OPP: How it Works ?

• L_aux with flyback polarity swings to –NV_IN during the on time.

• Adjust amount of OPP voltage with (R_zcd+R_opu) // R_opl.

• V_CS,max = 0.8 V + V_OPP

• The diode bypass R_opu during the off-time for optimum zero-crossing detection.

100%

60%

370 Peak current

set point

V_IN(V)

0.8 V + Vopp

ZCD/OPP IpFlag

+

0.8 V

+ -

ESD protection Aux

Ropu

Ropl

1 Rzcd

CS

+ - Vth

DRV Tblank

leakage blanking

Demag

OPP Amount Needed for the Design

• Because of the propagation delay, at high line:

2

( ) ( )

( )

1 1

out high

2

sw high

P L I

T η

=

( ) ( )

,

1 2

ps

sw high pk high p p lump

out f

in max

T I L N L C

V V

V π

⎛ ⎞

= ⎜ ⎜ ⎝ + + ⎟ ⎟ ⎠ +

( ) ,

0.8 2

pk high in max

sense p

I V t

R L

= +

• The switching frequency is:

• The power capability at high line is:

9

( ) 6

0.8 600 10

265 2 4.32

0.23 290 10

pk high

I A

−

−

= + × =

×

6 6 12

( )

1 0.25

4.32 290 10 285 10 250 10 19.5

19 0.8 265 2

sw high

T = × × ^{− ⎛}⎜⎝ + + ^⎞⎟⎠+π × ⁻ × × ⁻ = µs

6 2

( ) 6

1 1

290 10 4.32 0.85 116

2 19.5 10

out high

P = × ⁻ × ₋ = W

×

Amount of OPP Voltage Needed

• Limit the output power to P

= 70 W at high line.

• What is the peak current I

corresponding to P

?

2 2

( ), ( ), ( )

( )

( )

1 1

ps ps 2 p

p p p lump

in max dc out f in max dc out f out limit

pk limit

p out limit

N N L

L L L C

V V V V V V P

I L

P

η π

η

⎛ ⎞ ⎛ ⎞

+ + + −

⎜ ⎟ ⎜ ⎟

⎜ + ⎟ ⎜ + ⎟

⎝ ⎠ ⎝ ⎠

=

( )^{2 2}

( )

1 0.25 1 0.25 285µ 0.85

285µ 285µ 2 285µ 250p

375 19 0.8 375 19 0.8 70

285µ 0.85 2.67 70

pk limit

I A

× π

⎛ + ⎞+ ⎛ + ⎞ − ×

⎜ + ⎟ ⎜ + ⎟

⎝ ⎠ ⎝ ⎠

= × =

• Amount of OPP voltage needed:

( )

( )

0.8 1 ^{pk limit}

OPP

pk max

V I

I

⎛ ⎞

= ⎜⎜ − ⎟⎟

⎝ ⎠ ^{VOPP = 0.8 1⎛}⎜⎝ ^{− 2.67}_4.32^⎞⎟⎠^{=300 mV}

Calculating the OPP Resistors

• The amount of OPP voltage needed to limit P_out to 70 W is : V_OPP = 300 mV

• Resistor divider law:

,

opu zcd p aux IN OPP

opl OPP

R R N V V

R V

+ −

=

0.18 375 0.3 0.3 224

opu zcd

opl

R R

R

+ = × − =

ZCD/OPP

Aux

Ropu

Ropl

1 Rzcd

opu

221

R = R − R

• We choose: R_opl = 1 kΩ and R_zcd = 1 kΩ

opu 223

R = kΩ

Why is the OPP Non Dissipative ?

• Input voltage information given by auxiliary winding

• In light load: VCO mode => T_sw expands, thus the average current in the resistor bridge decreases

( )

, ,

1

1

bridge avg p aux IN CC f

zcd opu opl sw opu opl sw

t t

I N V V V

R R R T R R T

= + +

+ + +

,

1 1.2 1 3.6

0.18 375 16 15

220 1 1 40 220 1 40

bridge mean

µ µ

I µA

k k k µ k k µ

= × × + =

+ + +

¾ Previous example: R_opu = 220 kΩ, R_opl = 1 kΩ, R_zcd = 1 kΩ At light load (P_out = 4 W), t_on= 1.2 µs, t_off = 3.6 µs, T_sw= 40 µs

Laux Vcc D1

CVcc Rstartup Bulk

Laux Vcc D2

CVcc

Rstartup/3.14

D4 D3

D5 D6

I1 I1

Startup Network

• The startup resistor can either be connected:

– To the bulk capacitor with R_startup

– To the half-wave – for a similar charging current, take R_startup/π

Classical configuration Improved startup dissipation

Startup Capacitor Calculation

• C_Vcc calculated to allow the power supply to close the loop before V_CC falls below V_CC(off)

• Needed startup current to charge C_Vcc:

(

)

17 9 3.9

Vcc

m n m

C + × × µF

= =

−

( )

( )

CC 3A g sw reg

Vcc

CC on CC(off)

I Q F t

C V V

= +

−

t_startup t_reg

V_CC

( )

CC on Vcc Cvcc

startup

V C

I = t

Cvcc 2.8

I = × µ = µA

We choose C_Vcc = 4.7 µF

t_reg

• Half wave connection

Startup Resistor Calculation

• Bulk capacitor connection

,

( )

in min 2

startup

Cvcc CC start

V

R I I

= π

+

Half wave connection saves 39 mW !

,

( )

in min 2

startup

Cvcc CC start

R V

I I

= +

2

, 2

in max

CC startup

startup

V V

P R

π

⎛ ⎞

⎜ − ⎟

⎜ ⎟

⎝ ⎠

=

(

)

startup

startup

V V

P R

= −

¾ Resistor calculation:

¾ Power dissipation:

¾ Resistor calculation:

¾ Power dissipation:

85 2 2.76 28.5 15

startup

R M

µ µ

= = Ω

+

(

)

2.68 55

startup

P mW

M

= − =

85 2 880

28.5 15

startup

R k

µ µ

= π = Ω

+

(

)

880 16

startup

P mW

k π −

= =

Synchronous Rectification

• High rms currents in secondary side Æ increased losses in the output diode.

• Replace the diode with a MOSFET featuring a very low R

.

Degraded light load and standby power consumption Increased efficiency

- +

. .

Vout

Gnd C_out

Q_sync

Losses in the Sync. Rect. Switch

2

( ) ,

ON DS on 120 sec rms

P = R I

Qsync ON Qdiode

P = P + P

Qdiode f out sw delay

P = V I F t

‰ Losses in the Sync. Rect. switch are mainly conduction losses.

Low if t_delay small

‰ MOSFET conduction losses

‰ Body diode conduction losses

. .

Vout

Gnd

R_load C_out

Qsync

• Body diode conducts before the MOSFET is turned-on.

No switching losses

t_delay

Choosing the Sync. Rect. MOSFET

• Target around 1 W conduction losses in Sync. Rect. switch to avoid using an heatsink.

2 ,

1

DSon120

sec RMS

R W

= I

Universal mains

1 2 3 4 5 6

0 2 4

6 MBR20H150

R_DSon110 = 30 mΩ R_DSon110 = 50 mΩ R_DSon110 = 70 mΩ

P loss(W)

I_out (A)

60 W QR Sync. Rect. Calculations

2 2

( ) ,

30 5.8

1

ON DS on 120 sec rms ON

P R I m

P W

= = ×

=

0.7 3.2 45000 70 7

Qdiode f out sw delay Qdiode

P V I F t n

P mW

= = × × ×

=

1 0.007 1

Qsync

P = + ≈ W

Power loss saving: 1.6 W

‰ Total Sync. Rect. switch losses:

‰ Losses into the MBR20200 diode: 2.6 W

‰ MOSFET losses:

‰ Body diode losses:

Agenda

1. Quasi-Resonance (QR) Generalities 2. The valley lockout technique

3. The NCP1379/1380

4. Step by step design procedure

5. Performances of a 60 W adapter featuring

valley lockout

60 W Demo Board Schematic

C5 1n C622p

C1 2.2n

C4200p C8

220p C11

4.7u

D5 1N4937

D6 1N967

X5TL431_G C10 47n

C9 330nF

L1

X2

C18100n C14

100u T1

. . .

M1

R16

10 D3

1N4148

R3 47k

D2 MBR20H150

C5a 680uF

L3 Vout

2.2u

C7 100uF

35V 25V

C5b 680uF

35V C15 Gnd

2.2nF Type = Y1 TO-220

R5 27k

R7 39k

R8 10k R91k

R15 1k R18

1k

IPA60R385

Gnd

X4 NTC

Gnd

+

- IN

X18 KBU4K

R26 0.47 R27

0.47

C20 100n R29

1k 10 mH

2 A

Rx 10

R14 1k

R4

18k R11

18k

1 2 3

4 5

8

6 7 X1 DIP8 R1

240k D4 1N4148

D7 1N4148

Q1 BC857 R2

1500k

R6 1200k

C13 100u

R12 1Meg

R13 1Meg

D1 1N4937

D8 1N4148

C17 10n R19

1Meg

NCP1380B in a 19 V, 60 W adapter

Startup

• Startup resistor connected to the bulk rail (R_startup = 2.7 MΩ)

• T_startup = 2.68 s

V_CC

• Startup resistor connected to the half-wave (R_startup = 910 kΩ)

• T_startup = 2.1 s

V_CC

Transient Load Step

• Load step:

3% to 100% of output load with a slew rate of 1 A / µs

• V_in = 230 Vrms

The overshoot / undershoot is 1% of the nominal value of V_out

Short-Circuit

• A short-circuit is made at the board output.

• The circuit pulses with a low burst (5%)

• The measured averaged input power is: P_in = 412.4 mW for V_in = 230 Vrms

V_DRV V_CC

V_CC(off)

Efficiency

74.5 0.94

0.7

72.0 0.69

0.5

76.4 1.30

1.0

17.61 86.4 15.2 25

34.40 88.2 30.3 50

51.29 88.7 45.5 75

68.65 88.3 60.6 100

Eff. (%) P_in (W)

P_out (%) P_out (W)

115 Vrms

73.0 0.958

0.7

70.2 0.71

0.5

75.4 1.325

1.0

17.66 86.1 15.2 25

34.78 87.3 30.3 50

51.43 88.4 45.5 75

68.00 89.1 60.6 100

Eff. (%) P_in (W)

P_out (%) P_out (W)

230 Vrms

Average efficiency

(25, 50, 75, 100% of P_out,max): 87.9%

Average efficiency

(25, 50, 75, 100% of P_out,max): 87.7%