博 士 学 位 論 文

博

Doctoral Dissertation

内容の要旨 及び 審査結果の要旨

Dissertation Abstracts and

Summaries of the Dissertation Review Results

第２９号

The Twenty-ninth Issue

平成２９年３月

March, 2017

The University of Aizu

はしがき

博士の学位を授与したので、学位規則（昭和２８年４月１日文部省令第９号）第８条の規定 に基づき、その論文の内容の要旨及び論文審査の結果の要旨をここに公表する。

学位記番号に付した｢甲｣は学位規則第４条第１項（いわゆる課程博士）によるものであるこ とを示す。

Preface

On granting the Doctoral Degree to the individuals mentioned below, abstracts of their theses and the theses review results are herewith publicly announced, in according to the provisions provided for in Article 8 of the Ruling of Degrees (Ministry Of Education Ordinance No.9, enacted on April 1, 1953)

The Chinese character, “甲”, at the beginning of the diploma number represents that an

individual has been granted the degree in accordance with the provisions provided for in

Paragraph 4-1 of the Ruling Of Degrees (what is called “Katei Hakase,” or the Doctoral

Degree granted by the University at which the grantee was enrolled.).

- 1 -

目 次

Contents

掲載順

Order

学位記番号 Diploma No.

学位

Degree

氏名

Name

論文題目

Dissertation Title

頁

Page

１ ^甲CI博 第55号

博士（コンピュー タ理工学）

増子 駿 MASHIKO, Hayato

最先端プロセス技術における製造ばら つきを考慮したデジタル集積回路設計 手法

Digital LSI Design Methods Considering Process Variations in Advanced Technology Nodes

2

２ ^甲CI博 第56号

博士（コンピュー

タ理工学） MEYER, Michael

高性能なメニーコアシステムオンチップ の為のマイクロリングの障害耐性を持 つ光通信オンチップネットワーク Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core Systems-on-Chip

6

３ ^甲CI博 第57号

博士（コンピュー

タ理工学） MAI, Viet Vuong

光無線通信ネットワークのためのクロス レイヤ設計・分析および最適化 Cross-layer Design, Analysis, and Optimization for Optical Wireless Communication Networks

10

４ ^甲CI博 第58号

博士（コンピュー タ理工学）

金田 祐也 KANEDA, Yuya

コンパクトな察知エージェントに適した 効率的且つ効果的学習アルゴリズム Efficient and Effective Learning Algorithms for Compact Aware Agents

13

- 2 -

Name

氏名

MASHIKO, Hayato

The relevant degree

Doctoral degree (in Computer Science and Engineering)

Number of the diploma of the Doctoral Degree

学 位 記 番 号

甲

CI

55

The Date of Conferment

March 21, 2017

29

3

21

Requirements for Degree Conferment

学位授与の要件

Please refer to the article five of “University Regulation on University Degrees”

会津大学学位規程 第５条該当

Dissertation Title

論文題目

Digital LSI Design Methods Considering Process Variations in Advanced Technology Nodes

最先端プロセス技術における製造ばらつきを考慮した デジタル集積回路設計手法

Dissertation Review Committee Members

University of Aizu, Senior Associate Prof. KOHIRA, Y.

(Chief Referee)

University of Aizu, Prof. TSUKAHARA, T.

University of Aizu, Prof. BEN, A.

University of Aizu, Senior Associate Prof. SAITO, H.

University of Aizu, Associate Prof. TOMIOKA, Y.

会津大学上級准教授 小平 行秀（主査）

会津大学教授 束原 恒夫 会津大学教授 ﾍﾞﾝ ｱﾌﾞﾃﾞﾗｾﾞｸ 会津大学上級准教授 齋藤 寛 会津大学准教授 富岡 洋一

- 3 -

Abstract

Due to the progress of the process technology in LSI, although the performances of the circuits have been advanced, the process variations are increased in fabrication. The delay variations by the process variations cause malfunction in the circuits. Therefore, the yield of the chips is reduced by the process variations.

To improve the yield reduction by the process variations in the lithography, 1D-layout style in the layout design of the circuits, where the layout pattern does not bend and it extends in one direction, is promising. Furthermore, the area minimization in the layout design is required.

However, the existing methods, which reduce the width rather than the height in the standard cell design where the height is fixed, do not always obtain a layout with the minimum area since the width is larger than the height in general layouts. In this thesis, a n area minimization method which minimizes the width with the minimum height for CMOS circuits in the 1D-layout style is proposed for the custom design or the cell design where the height is unfixed. The experimental results show that the area of the layou ts obtained by the proposed method is reduced by 11% in comparison with that obtained by the existing method which minimizes the height with the minimum width.

Recently, post-silicon delay tuning is promising to recover the malfunction by the delay variations after fabrication. In the post-silicon delay tuning, programmable de-lay elements (PDEs), whose delays can be tuned after fabrication, are inserted into the clock tree before fabrication and the delays of PDEs are tuned to recover the malfunction by t he delay variations in test process after fabrication. To realize the post -silicon delay tuning, the optimality and time complexity of delay tuning algorithm, the PDE structure, the design flow of circuit with PDEs and the test costs for the delay tuning o f PDEs must be taken into consideration.

However, the existing methods may not be practical since each existing method does not take all of them into consideration. In this thesis, three delay tuning methods are proposed: a delay tuning method using PDEs with two delays, a delay tuning method using PDEs with discrete delays, and a design method applying technology mapping and post -silicon delay tuning.

In the proposed delay tuning method using PDEs with two delays, a PDE structure is realized by buffers and a multiplexer. To design circuit with PDEs, a flow where commercial CAD tools are used is proposed. Furthermore, a delay tuning algorithm for PDEs with two delays is proposed so that the algorithm proposed in [1] is applied with the less number of tests . The experimental results under Monte-Carlo simulations show that the yield of circuits obtained by the proposed method is higher than that obtained by a heuristic method and the number of tests in the proposed method is reduced by 45.6% compared to that in the algorithm proposed in [1].

In the proposed delay tuning method using PDEs with discrete delays, the PDE structure and

- 4 -

the design flow of circuit with PDEs are applied in the similar way of the proposed delay tuning method using PDEs with two delays. Furthermore, the proposed delay tuning algorithm guarantees that an optimum solution is obtained in polynomial time since it is based on the modified Bellman-Ford algorithm using tests. The experimental results show that although there is the overhead in the area and the power consumption, the proposed methods using PDEs with two delays, PDEs with four delays and PDEs with eight delays improve the yield by 11.5%, 54.7% and 72% on average compared to the conventional design method respectively.

In the proposed design method applying technology mapping and post -silicon de-lay tuning, the technology mapping method proposed in [2] and the proposed delay tuning method using PDEs with discrete delays are applied to circuits to improve the yield and reduce the p ower consumption. The experimental results show that the pro-posed method improves the minimum clock period, where the yield is over 90%, by 8% and the power consumption in technology mapping by 15% in comparison to the conventional design method using the high speed cell library in gate-level design. In the layout design, the proposed method improves the minimum clock period, where the yield is over 90% in the conventional design method using the high speed cell library, by 13% and the leakage power in the only delay tuning method by 5% with the overhead in the area and the power consumption.

Summary of the Dissertation Review Result

The two contributions of the candidate are mainly on the LSI design considering the process variations. One is 1D-layout style, and the other is post-silicon delay tuning.

1D-layout style is promising to improve the yield against the process va riations in the lithography. In the lithography, the straight line can be formed more easily than the complex pattern. In1D-layout style, each layout pattern is formed by a straight line. Furthermore, the area minimization is required in the layout design. He proposed an area minimization method for CMOS circuits in the 1D-layout style for the custom design or the cell design. His proposed method is based on SAT problem. The experimental result shows that the area of the layouts obtained by the proposed method is reduced compared with an existing method.

Post-silicon delay tuning is promising to improve the yield aga inst the delay variations after

fabrication. In the post-silicon delay tuning, programmable delay elements called PDEs are

inserted into the clock tree before fabrication. In test process after fabrication, the delays of

PDEs are set appropriately to recover the function. He proposed three delay tuning methods: a

delay tuning method using PDEs with two delays, a delay tuning method using PDEs with

discrete delays, and a design method applying technology mapping and post -silicon delay

tuning. These proposed methods are based on graph algorithms and Integer Linear

- 5 -

Programming. In experimental results, although there are overheads in the area and the power consumption, the proposed methods improved the yield.

He has published papers in two major journals as the first author, t hree international

conferences, and many domestic conferences. In the final review, he gave good presentation

and answered almost questions appropriately.

- 6 -

Name

氏名

MEYER, Michael

The relevant degree

学位の種類

Doctoral degree (in Computer Science and Engineering)

Number of the diploma of the Doctoral Degree

学 位 記 番 号

甲

CI

56

The Date of Conferment

March 21, 2017

29

3

21

Requirements for Degree Conferment

学位授与の要件

Please refer to the article five of “University Regulation on University Degrees”

会津大学学位規程 第５条該当

Dissertation Title

論文題目

Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core

Systems-on-Chip

高性能なメニーコアシステムオンチップの為のマイクロ リングの障害耐性を持つ光通信オンチップネットワーク

Dissertation Review Committee Members

論文審査委員

University of Aizu, Prof. BEN, A.

University of Aizu, Prof. MIYAZAKI, T.

University of Aizu, Prof. TSUKAHARA, T.

University of Aizu, Prof. KITAMICHI, J.

University of Aizu, Senior Associate Prof. KOHIRA, Y.

会津大学教授 ﾍﾞﾝ ｱﾌﾞﾃﾞﾗｾﾞｸ（主査）

会津大学教授 宮崎 敏明 会津大学教授 束原 恒夫 会津大学教授 北道 淳司 会津大学上級准教授 小平 行秀

- 7 -

Abstract

Humans continue to demand higher performance from their computing systems, and as a result we have had aggressive increases in the scaling of technology, but this is showing signs of change. The power consumed by a chip is ever increasing, and recently the power efficiency of communications has become as important as the computational power of the cores. Typical electronic Networks-on-Chip (NoCs) are reaching their performance limitations thanks to various factors.

One highly sought after technology is Photonic Networks-on-Chip (PNoCs). PNoCs offer several benefits over conventional electrical NoCs, such as high-bandwidth support, distance independent power consumption, lower latency, and improved performance-per-watt. Wavelength Division Multiplexing allows for multiple parallel optical streams of data to concurrently transfer through a single waveguide and MRs can be switched at speeds as high as 40 GHz to realize wavelength-selective modulators or switches. These technologies allow for multiple bits of data to travel concurrently through the same waveguide, which contradicts the one bit per wire limitation of electronic circuits. Another benefit is that data is transferred in an end-to-end fashion once a path is configured, meaning that the data does not need to be buffered multiple times, and thus saving power.

The photonic domain is immune to transient faults caused by radiation, but is still susceptible to process variation (PV) and thermal variation (TV) as well as aging. The aging typically occurs faster in active components as well as elements that have high thermal variation. In the optical domain, faults can occur in MRs, waveguides, routers, etc. Active components, such as photodetectors, have higher failure rates than passive components, e.g. waveguides. Moreover, when paired with the fact that a PNoC is highly vulnerable, as a fault may expose the single-point failure, a faulty MR can cause a message to misdelivered or lost. In this dissertation, a set of novel photonic routing algorithms and architectures are proposed for future on-chip optical networks.

First, a new fault tolerant photonic switch, capable of handling multiple faulty MRs. The proposed switch is based on a non-blocking 5-port optical router. It requires no MRs to travel in the opposite direction (e.g. East to West or North to South). The switch is also able to handle the previous hybrid spatial switching used in PHENIC.

Second, a fault tolerant Path configuration algorithm, which checks for MR faults and allocates the proper MRs to be used. This means that our previous 2 state MRST must also have a faulty state.

Additionally, the algorithm must use two MR Configuration Tables, one for standard use and another to be used for the backup paths. This makes all of the routing decisions within a single optical switch.

Third, a power estimation scheme for the optical layer, which is fast enough to be used for routing

decisions. Because of the speed that the calculation must be done, the calculation itself must be

simple.

- 8 -

Finally, I propose an architecture and routing algorithm pair, which allow for the network to make

“strain" based decisions for the routing. This strain value is based on the number of faulty MRs and the optical power of a node. This should improve the networks reliability and performance by avoiding nodes with high temperature, a high number of faulty nodes, or a lot of traffic.

The proposed architectures and algorithms were evaluated with a discrete-event simulator, which incorporates detailed physical models of the photonic components. Results show that the proposed system was able to achieve a higher reliability with minimal sacrifices in the overall system performance and energy. The resulting system is able to address the problems of process variation as well as temperature variation in optical components, and is more reliable than previous existing systems.

Summary of the Dissertation Review Result

This thesis presents three main contributions: (1) a reliable nanophotonic switch which we call FTTDOR, which has different versions with a different number of ports; (2) a proposed architecture called FT-PHENIC which utilizes a new fault-tolerant path configuration algorithm called FTPP; and (3) a stress-aware fault-tolerant routing algorithm for the optical on-chip networks.

Starting with a non-blocking 5x5 optical switch, we added redundancy at key locations in order to create a switch which can be utilized to provide some fault tolerance before avoiding the switch completely. This results in less blocked packets when faults are introduced, thus maintaining a more graceful decline in performance as a higher percentage of faulty MRs are introduced into the system.

This switch can be utilized by any network which uses an optical switch with the same number of ports as one of the variants.

To control the fault-tolerant switch, we proposed a fault-tolerant path configuration algorithm. The proposed algorithm was very specific because it was an adaptation of the previous PHENIC's complex optical path configuration algorithm, but we believe that any path configuration algorithm can be modified in a similar way to allow for the use of two MRCTs. This resulted in a new network

architecture, which we called FT-PHENIC, which allowed for various fault-tolerance techniques to be implemented.

Finally, we proposed a new and improved routing algorithm. The routing algorithm used traffic and

fault information to create a 'Strain' value. This strain value is mostly based off of the power estimate

with the assumption that the temperature is based off of the power use. The other factor was an

upper limit on the number of MRs that could fail in each switch, which improved the message's ability

to avoid possible system failure. This also helped us reduce the number of blocked packets, because

the algorithm automatically avoided nodes that were being used more than other neighboring nodes.

- 9 -

In the preliminary review, the candidate explicitly answered the questions that the reviewers had asked.

Additionally, he addressed any of the comments to which they had on his paper and presentation, to improve the quality and understanding of the paper and the proposed system. In the final review, the candidate successfully changed his presentation and paper accordingly to the comments, which improved the dissertation.

In conclusion, the candidate has fulfilled all of the formal requirements for the doctoral degree.

- 10 -

Name

氏名

MAI, Viet Vuong

The relevant degree

学位の種類

Doctoral degree (in Computer Science and Engineering)

Number of the diploma of the Doctoral Degree

学 位 記 番 号

甲

CI

57

The Date of Conferment

March 21, 2017

29

3

21

Requirements for Degree Conferment

学位授与の要件

Please refer to the article five of “University Regulation on University Degrees”

会津大学学位規程 第５条該当

Dissertation Title

論文題目

Cross-layer Design, Analysis, and Optimization for Optical Wireless Communication Networks

光無線通信ネットワークのためのクロスレイヤ設計・分 析および最適化

Dissertation Review Committee Members

University of Aizu, Prof. PHAM, A.

University of Aizu, Prof. TEI, S.

University of Aizu, Prof. MIYAZAKI, T.

University of Aizu, Senior Associate Prof.

TRUONG, C.T.

会津大学教授 ｱﾝ ﾄｩｱﾝ ﾌｧﾝ（主査）

会津大学教授 程 子学 会津大学教授 宮崎 敏明

会津大学上級准教授 ｺﾝﾀﾝ ﾁｮｵﾝ

- 11 -

Abstract

With the rapid proliferation of Internet mobile devices, the fifth generation (5G) of mobile networks is predicted to achieve 1000 times system capacity, 10 times spectral/energy efficiency, 10-100 times data rate, and 25 times average cell throughput, compared to the fourth generation (4G) networks. To increase the network capacity for supporting high-density mobile users with high-speed data services, the inevitable trend is the deployment of smaller cells (i.e., picocells and femtocells). The massive data traffic from the small cells shall be connected to the core network through the backhaul network with extreme requirements in terms of capacity, latency, reliability, efficiency, and cost effectiveness.

Currently, three transport media are used for backhaul networks: copper, radio frequency (RF) links, and optical fibers (OF). Leased copper lines are becoming infeasible options for meeting future backhaul demands due to the low data rate. Microwave technology also has its own issues including limited data rates, licensed spectrum, interference, and weather conditions. Optical fiber, on the other hand, can support very high data rates, yet it is not always economical and possible to deploy optical fibers. Free-space optics (FSO) is an optical communication technology that uses light propagating in free space to wirelessly transmit data. FSO communication based systems have advantages over microwave radio systems such as free license, interference immunity, and high capacity. Relative to fiber systems, FSO communication has the advantage of ease of setup and tear down, provision of access in difficult locations, and lower cost.

This thesis explores a hybrid architecture utilizing FSO and other technologies (i.e., OF and RF) to provide a flexible, cost effective and reliable solution for next generation mobile backhaul networks.

5G-backhaul networks with OF/FSO/RF are, however, faced with several challenges. Especially for network design, designing networks taking into account dynamic FSO weather-dependence channels and variety of technology combinations is challenging. Our research mainly focus on different combinations of FSO and other technologies for next-generation mobile backhaul networks, and solutions for their network designs. In particular, we study PHY/Data-Link cross-layer designs for different subsystems of 5G-backhaul network, including point-to-point FSO, cooperative FSO, hybrid FSO/RF, and integrated FSO/OF. Several original contributions have been made in this work. Details will be shown in Chapters 3–6.

Chapter 3 focuses on point-to-point FSO. This introduces a cross-layer framework, in which Automatic Repeat reQuest (ARQ) in Data-Link layer and Adaptive Rate (AR) transmission in PHY layer are integrated to offer an effective solution to improve the overall system performance over atmospheric turbulence channels. Different aspects of AR/ARQ cross-layer design, analysis and optimization, are investigated for point-to-point FSO.

Chapter 4 focuses on cooperative FSO. This considers an application of ARQ in cooperative FSO.

Two joint designs of ARQ and cooperative diversity are considered: ARQ and cooperative diversity

with/without storing messages at the relay nodes. We analytically study the system performance of

- 12 -

two designs, and discuss cross-layer optimization for selecting parameters in both PHY and Data-Link layers in order to optimize the performance of FSO systems over different atmospheric turbulence conditions and channel distances.

Chapter 5 focuses on hybrid FSO/RF. This proposes adaptive multi-rate (AMR) scheme for hybrid FSO/RF systems, which jointly employs traffic delivering and AR transmission. Furthermore, we employe the ARQ/AR cross-layer design approach for designing switching thresholds of AMR. We comprehensively consider effects of fading channels and different weather conditions in the performance of AMR.

Chapter 6 focuses on integrated FSO/OF. This comprehensively addresses two major challenging issues: providing efficient Multiple Access Control (MAC) protocol and ensuring high reliable transmission. We jointly consider the dynamic bandwidth allocation (DBA), AR transmission, and ARQ with different retransmission strategies. We develop a cross-layer analysis to qualify QoS performance metrics, and show that the proposed protocol stack design can offer considerable performance improvement over conventional ones.

Summary of the Dissertation Review Result

This dissertation is a novel study on cross-layer design of free-space optical (FSO) communication networks. The key idea is to exploit the interactions between the protocols/layers to improve and optimize the performance of FSO systems. In particular, the dissertation works on the different Physical/Data-Link cross-layer designs, analysis and optimization framework for various FSO configurations in the context of the next-generation mobile backhaul networks.

The dissertation consists of seven (07) chapters, of which the first three chapters lay down the background of FSO technologies and the motivations of the study. The last 4 chapters reflect four major contributions of the candidate on the cross-layer design of P2P FSO, Cooperative FSO, Hybrid RF/FSO and Integrated FSO/PON systems. Each of these four contributions are published in one major journal article (IEEE or IEICE). In total, the candidate has published five (05) major journal articles and nineteen (19) conference papers in major conferences, such as IEEE GLOBECOM, ICC and VTC. As a highlight, the candidate also won several research awards during his PhD study, including the IEEE ComSoc Sendai Section’s Excellent Research Award in 2015 and the IEEE VTS Tokyo Chapter Young Researcher's Encouragement Award in 2016.

The committee unanimously agree that the research is novel and significant for the area of free-space

optical (FSO) communications & networks, especially in the design of the FSO-based next-generation

mobile backhaul networks. In overall, the candidate is qualified for the conferment of PhD degree

considering the contribution of the dissertation, his publication record and his scholastic ability.

- 13 -

Name

氏名

KANEDA, Yuya

The relevant degree

学位の種類

Doctoral degree (in Computer Science and Engineering)

Number of the diploma of the Doctoral Degree

学 位 記 番 号

甲

CI

58

The Date of Conferment

March 21, 2017

29

3

21

Requirements for Degree Conferment

学位授与の要件

Please refer to the article five of “University Regulation on University Degrees”

会津大学学位規程 第５条該当

Dissertation Title

論文題目

Efficient and Effective Learning Algorithms for Compact Aware Agents

コンパクトな察知エージェントに適した効率的且つ効 果的学習アルゴリズム

Dissertation Review Committee Members

University of Aizu, Prof. ZHAO, Q.

University of Aizu, Prof. SUGIYAMA, M.

University of Aizu, Prof. PAIK, I.

University of Aizu, Senior Associate Prof. LIU, Y.

会津大学教授 趙 強福（主査）

会津大学教授 杉山 雅英 会津大学教授 白 寅天 会津大学上級准教授 劉 勇

- 14 -

Abstract

Decision boundary making (DBM) algorithm was proposed to induce compact and high performance machine learning models for implementing aware agents (A-agents) on portable/wearable computing devices (P/WCDs). The DBM algorithm reconstructs the decision boundary (DB) of a support vector machine (SVM) using a less expensive single hidden layer multilayer perceptron (MLP). The DBM can obtain compact MLPs that preserve the performance of the SVMs, and this has been proved via experiments on many databases. In this thesis, I propose two efficient and effective learning algorithms for the DBM algorithm to use machine learning models in real applications. The one is to improve the DBM performance by removing outlier data. In previous experiments, sometimes the DBM performance is not good enough compared with SVM. To improve the performance, I propose an SVM-based outlier detection method using a threshold parameter. Experimental results show that the DBM algorithm with the SVM-based outlier detection improve the performance, and the performance becomes higher or equivalent to the SVM performance in almost all cases. In addition, this thesis also investigates the classification time performance of the DBM using some different P/WCDs. The DBM algorithm can reduce the classification time greatly, and the effectiveness of the DBM is proportional to the number of training data. Another contribution is to upgrade the model performance efficiently in real time on P/WCDs. I propose an on-line training algorithm with guide data (OLTAGD) to update the model using the guide data and each datum observed in real time. By updating the model efficiently in real time, the model performance can be kept in high level, and this also can resolve problems, such as some new projects have to collect many data at the beginning and so on. To generate the guide data set, I also investigate three methods for guide data selection, namely random selection, and two cluster center based selection methods. The cluster centers are found either by the k-means algorithm or by the decision surface mapping (DSM) algorithm. Experimental results for OLTA-GD reveal that OLTA-GD with the cluster center based selection using k-means outperforms others on stability and efficient performance for model updating. By the two learning algorithms, the DBM algorithm becomes more efficient and effective algorithm for real applications.

Summary of the Dissertation Review Result

This doctoral dissertation proposes efficient and effective learning algorithms for compact aware agents (A-agents) that can be implemented easily in portable or wearable computing devices. There are mainly two contributions. The first is a support vector machine (SVM)-based outlier detection method to improve the performance of the decision boundary making (DBM) algorithm, which was proposed by Kaneda-kun in his master program, and the second one is an on-line training algorithm with guide data (OLTA-GD).

The significance of the first contribution has been proved via experiments, and a journal paper has

been published. Its main idea here is to detect the outliers in the training data using SVM, so that a

more compact and more effective MLP can be obtained based the “clean” data. Since the same SVM

- 15 -

is used both for detecting the outliers and for determining the decision boundary, the performance of the MLP can be improved without increasing the computational cost.

The second contribution is useful for upgrading the performance or customize an existing A-agent in real time. Newly observed data often have new information. It is necessary to incorporate the

information into the agent to improve its performance, or to satisfy the needs of the user. The main

idea of using guide data is to introduce a damper to stabilize on-line learning, and at the same time, to

reduce computational cost for updating the agent. This dissertation proposes the new algorithms, and

proves their efficiency and efficacy via experiments. Some interesting results have been published in

the international conferences.

- 16 -

博 士 学 位 論 文 Doctoral Dissertation

内容の要旨 及び 審査結果の要旨 Dissertation Abstracts

and

Summaries of the Dissertation Review Results

第29号

The Twenty-ninth Issue

平成２９年３月 March, 2017

発行 会津大学

〒965-8580 福島県会津若松市一箕町鶴賀 TEL: 0242-37-2600

FAX: 0242-37-2526 THE UNIVERSITY OF AIZU Tsuruga, Ikki-machi Aizu-Wakamatsu City

Fukushima, 965-8580 Japan