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(1)

Phase-Locked Loop Circuit Design

— From Basics to State-of-The-Art and Industrial Practices —

Atsushi Motozawa

(email: atsushi.motozawa.kx@renesas.com )

Renesas Electronics Corporation

(2)

Outline

◼ What is a PLL?

◼ Applications

◼ Building blocks & Design tips

◼ Advanced architecture

◼ Summary

(3)

MCU Operation Frequency

6300

2MHz

H8/500

10MHz

SH7055

40MHz

V850

195MHz

Quadruple over decade

1980 1990 2000 2010

Year

Operat ion fre quency for MCU

◼ Operation frequency getting higher year by year

◼ Quadruples every decade

(4)

What is a PLL?

◼ Frequency multiplication ◼ Phase difference reduction CLKin PLL CLKout

CLKin

CLKout

x N

CLKin

CLKout

(5)

How to distribute high frequency clock

◼ IC without PLL ◼ IC with PLL

CPU 1.5GHz

Logic 500MHz PLL

PLL

20MHz

CPU 1.5GHz

Logic 500MHz

1.5GHz

500MHz

✓Crosstalk and reflection can occur

✓Extra space in PCB

✓Many pins are needed

✓Low input frequency

✓w/o crosstalk or reflection

✓Several identical PLLs with different divisors in one IC

X 75

X 25

(6)

Outline

◼ What is a PLL?

◼ Applications

◼ Building blocks & Design tips

◼ Advanced architecture

◼ Summary

(7)

Clock Deskewing

◼ Clock skew due to clock distribution

◼ With skew, It’s difficult to make synchronous systems

◼ Skew is dependent on

power supply voltage and temperature Skew

CLK1 Logic1

Logic2

CLK2

CLK1

CLK2 Data

buffers

(8)

Clock Deskewing

◼ Clock buffers are put into deskew PLL

◼ PLL reduces the phase difference between CLK1 and CLK2

◼ PLL can work

PFD

/CP Filter VCO

Logic1

Logic2

Deskew PLL CLK1

CLK2

CLK1

CLK2

Data

(9)

Spread Spectrum Clock (SSC)

PFD

/CP Filter VCO 1/N Fin=10MHz

DIV

Fout

1GHz

Output frequency

PSD

1 GHz Conventional

◼ An LSI operates at 1GHz.

The LSI emits EMI noise.

◼ It can interfere with other LSIs and signals on PCBs.

Freq.

Amplitude

N=100

time

(10)

Spread Spectrum Clock (SSC)

PFD

/CP Filter VCO 1/N

ΔΣ Fin=10MHz

N=100 N=99

DIV

1%

Fout

1GHz 0.99GHz

10MHz

Output frequency

PSD

1 GHz 0.99

GHz SSC

Conventional EMI

reduction

(1% of 1GHz)

◼ ΔΣ modulated divider to generate SSC

◼ ΔΣ noise is filtered by PLL

Freq.

Amplitude

1/f

mod

(11)

CDR(Clock and Data recovery)

PLL

Incoming

data Data

Recovered

CLK 1 0 1 0 1 0

Recovered CLK

Data

D Q

◼ Incoming data without accompanying clock

◼ CDR extracts a clock to sample incoming data

Incoming data

1

0

(12)

Outline

◼ What is a PLL?

◼ Applications

◼ Building blocks & Design tips

◼ Advanced architecture

◼ Summary

(13)

PLL Diagram

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

IN

OUT

How do we design a PLL?

(14)

Block diagram and Domains

IN

rad→rad

OUT

rad→A A→V V→A A→rad/s→rad

radrad

PFD CP Filter GM CCO

DIV

PLL’s building blocks

⚫ PFD: Phase-Frequency Detector

⚫ CP: Charge Pump

⚫ Loop filter

⚫ GM (Voltage-current converter)

⚫ CCO: Current-controlled Oscillator

[rad]

[A]

[V]

Line Domain

(15)

PLL Diagram

IN

OUT

PFD

(Phase-frequency detector)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

(16)

PFD(Phase-frequency detector)

D Q R

DRQ

Delay CLKin

CLKfb

UP

DN

CLKin CLKfb RST RSTd UP

CLKin CLKfb RST RSTd UP

Case1 (CLKfb is behind) Case2 (CLKfb is ahead)

RSTd RST VDD

◼ CLKfb is behind CLKin

→UP is wider

◼ CLKfb is ahead of CLKin

→DN is wider

◼ RST is delayed

to avoid dead zone

(17)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

PLL Diagram

IN

OUT

CP

(Charge pump)

(18)

UP DN

I

out I

CP

-ICP

0

CP (Charge Pump)

◼ Output is pulse-shaped current that is

dependent on the width of the phase difference

UP DN

I

out

I

CP

I

CP

CLKin CLKfb

Case1 Case2 Case3

Average of Iout [A]

𝜽𝟏

𝟐𝛑∙ 𝐈𝐂𝐏

𝜽𝟏 𝜽𝟐 𝜽𝟑

− 𝜽𝟐

𝟐𝛑∙ 𝐈𝐂𝐏 𝜽𝟑

𝟐𝛑∙ 𝐈𝐂𝐏

(19)

Modeling of PFD and CP set

◼ PFD becomes summing block.

◼ CP becomes gain block

D Q R

DRQ

CLKin

CLKfb

UP

DN

VDD

I

out

I

CP

I

CP

I

CP

2π Φin[rad]

Φfb[rad]

I

out[A]

PFD CP

PFD CP

(20)

PLL Diagram

IN

OUT

Loop filter

(Lead-lag filter)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

(21)

Loop Filter

◼ Converts the domain: current → voltage

◼ Cz is much larger than Cpl → Cz+Cpl ≈ Cz

I

in

V

out

C

pl

R

C

z

H s = V

out

I

in

= 1

sC

z

∙ sRC

z

+ 1 sRC

pl

+ 1

20*log|H|[dB] -20dB/dec

∠H[deg]

f

p

= 1 2πRC

pl

f

z

= 1

2πRC

z [Hz] [Hz]

log(f) [Hz]

f

p

10f

p

f

z

/10 f

z

-90 -45 0

log(f) [Hz]

From CP To GM

Zero 2

nd

pole

(22)

PLL Diagram

IN

OUT

GM

(Transconductor)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

(23)

GM

◼ Voltage-current converter

◼ Rdeg reduces the

transconductance but the linear range becomes wider.

R

deg

V

in

From Filter

I

cco Connected to CCO

g

m

g

m_eq

= g

m

g

m

R

deg

+ 1

(24)

Modeling of loop filter and GM set

R

deg

I

cco

Connected to CCO

g

m

C

pl

R

C

z

From CP

I

in

Loop Filter GM

1

sC

z

∙ sRC

z

+ 1 sRC

pl

+ 1

I

cco[A]

g

m_eq

I

in[A]

Vc Vc[V]

◼ Loop filter converts

the domain from current to voltage

◼ GM becomes gain block and

coverts the domain from voltage to current

gm_eq = gm gmRdeg + 1

Loop Filter GM

(25)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

PLL Diagram

IN

OUT

CCO

(Current-controlled oscillator)

(26)

CCO (Current-Controlled Oscillator)

I

cco

Icco[A]

𝜕

𝜕Icco

Icco[A]

ω

cco

[ra d /s ] K

cco

rad /s A

◼ The number of stages is commonly 3—5.

◼ Fcco=1/(2*Td*N) [Hz]

◼ In this talk, [rad/s/A] is used for Kcco. NOT [Hz/A]

Delay = Td

(27)

t[s]

t[s]

Relationship Between Frequency and Phase

𝛚

1 s

0 0.5 1 1.5

𝛚[ 𝐫𝐚𝐝 𝐬] Τ 𝛉 𝐫𝐚𝐝

t t

◼ Phase is the time integral of frequency

𝛚 ∙ 𝒕

ω 𝜃

𝛉

𝛉

Frequency Phase

(28)

Modeling of CCO

◼ Domain change: A → rad/s → rad

◼ -90° phase shift at DC

◼ Kcco is dependent on the operation frequency

I

cco

1 Kcco s

I

cco

[A]

[rad/s/A]

ω

cco

[rad/s]

ϕout [rad]

CCO CCO

(29)

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

PLL Diagram

IN

OUT

Divider

(30)

Divider

D Q D Q

CLK

D Q D Q

CLK

D1

Q1(Divide-by-2)

D2 D1

Q1 Q2

CLK Q1 D1 Q2 D2

CLK Q1 D1 Q2

Divide-by-2 and 4 dividerDivide-by-3 divider

Q2(Divide-by-4)

Q2(Divide-by-3)

(31)

Modeling of Divider

D Q D Q

CLK

D1

Q1

D2

1 𝜔

𝑖𝑛

𝑁

𝜔

𝑜𝑢𝑡

𝜑

𝑖𝑛

𝜑

𝑜𝑢𝑡

Divide-by-N divider Divide-by-N divider

𝜔

𝑜𝑢𝑡

= 1

𝑁 𝜔

𝑖𝑛

𝜙

𝑜𝑢𝑡

= 1

𝑁 𝜙

𝑖𝑛

Frequency Domain

Phase Domain

[rad/s]

[rad]

(32)

Modeling of Single-Path PLL

Φfb[rad]

ICP

Φin[rad] Iout[A] 1

sCz sRCz+ 1

sRCpl+ 1 Vc[V] gm_eq 1 Kcco s

Icco[A]

ωcco

[rad/s] Φout[rad]

D Q R

DRQ

UP

DN

Rdeg

gm

Cpl R

Cz

D

Q Q D

Icp

Icp

PFD CP CCO

Filter GM Divider

PFD CP Filter GM CCO

Divider

CLKin

CLKfb

CLKout

Iout Vc Icco

(33)

PLL transfer function and Bode Plot

Φfb[rad]

ICP

Φin[rad] Iout[A] 1

sCz sRCz+ 1

sRCpl+ 1 Vc[V] gm_eq 1 Kcco s

Icco[A]

ωcco

[rad/s] Φout[rad]

PFD CP Filter GM CCO

Divider

𝐻

𝑜𝑝

= 𝐾

𝐶𝐶𝑂

𝐼

𝑐𝑝

2𝜋𝑁 ∙ 1

𝑠

2

∙ 𝑔

𝑚_𝑒𝑞

𝐶

𝑧

∙ 𝑠𝑅𝐶

𝑧

+ 1 𝑠𝑅𝐶

𝑝𝑙

+ 1

1 2𝜋𝑅𝐶

𝑝𝑙

0

0 , ,

Poles[Hz]

1 2𝜋𝑅𝐶

𝑧

Zero[Hz]

Open loop Gain[dB]

-135° -90°

-40dB/dec

-20dB/dec

[deg]

0dB

-40dB/dec Log(f)

Open loop

Transfer function

(34)

-360 -345 -330 -315 -300 -285 -270 -255 -240 -225 -210 -195 -180 -165 -150 -135 -120 -105 -90 -75 -60 -45 -30 -15 0 -60

-50 -40 -30 -20 -10 0 10 20 30 40 50 60

6 dB 3 dB 1 dB

0.5 dB 0.25 dB

0 dB

-1 dB

-3 dB -6 dB

-12 dB

-20 dB

-40 dB

-60 dB ニコルス線図

開ループ位相 (deg)

開ル ー プ ゲ イ ン ( dB )

PLL open loop line on Nichols Chart

◼ The X-axis: Open loop Phase The Y-axis: Open loop Gain

Dashed circles: Closed loop Gain

◼ If the open loop line passes by the right side of

60

0

Open Loop Phase [deg]

40

Open loop Gain[dB]

-180 -135 -90

Open loop Phase[deg]

Log(f)

Log(f)

1dB

Nichols chart

-180deg 0dB

0.25dB

3dB

60dB

20

-20

Open loop Gain [dB]

Bode chart

(35)

Dual-Path PLL

𝐻

𝑜𝑝

= 𝐾

𝐶𝐶𝑂

𝐼

𝐶𝑃𝐼

2𝜋𝑁 ∙ 1

𝑠

2

∙ 𝑔

𝑚_𝑒𝑞

𝐶

𝑧

𝑠 𝐶

𝑧

𝑔

𝑚_𝑒𝑞

𝐼

𝐶𝑃𝑃

𝐼

𝐶𝑃𝐼

+ 1 𝑠𝑅𝐶

𝑝𝑙

+ 1

Open loop

Transfer function

1 2𝜋𝑅𝐶

𝑝𝑙

0

0 , ,

Poles[Hz]

1 𝑔

𝑚_𝑒𝑞

𝐼

𝐶𝑃𝐼

Crossover freq.[Hz]

≈ 𝐾

𝐶𝐶𝑂

𝐼

𝐶𝑃𝑃

2𝜋

2

𝑁 Integral Path

Proportional Path

◼ Zero can be controlled by the ratio of I

CPP

and I

CPI

. That leads to smaller C

z

Φfb[rad]

ICPP

Φin[rad] 1

sRCpl+ 1

gm_eq

1 Kcco s

Φout[rad]

ICP

1 sCz

(36)

Outline

◼ What is a PLL?

◼ Applications

◼ Building blocks & Design tips

◼ Advanced architecture

◼ Summary

(37)

Hybrid PLL

“A 0.7-to-3.5 GHz 0.6-to-2.8 mW

Highly Digital Phase-Locked Loop With Bandwidth Tracking”

Wenjing Yin, et al., IEEE JSSC, VOL. 46, NO. 8, pp1870—1880, AUG. 2011

◼ Analog-Digital Hybrid

✓ Small & programmable

✓ Analog proportional path to reduce quantization error

◼ !!PD instead of TDC

✓ Simple, Small, and Low power

(38)

Outline

◼ What is a PLL?

◼ Applications

◼ Building blocks & Design tips

◼ Advanced architecture

◼ Summary

(39)

Summary

◼ PLLs are utilized in many ICs

✓ One IC contains several identical PLLs to provide different frequency clocks

while reducing I/O pins and avoiding the reflection

◼ Many PLL applications

✓ Not only frequency multiplication

✓ SSC to reduce EMI noise

✓ CDR system to generate from incoming data

✓ Deskew PLL to decrease phase error among clocks

◼ Building blocks and transfer functions are discussed

✓ Several domains in PLL loop

✓ Dual-path PLL is used to reduce capacitor

◼ Analog-digital hybrid PLL with !!PD is introduced

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