Takao KIHARA†a), Nonmember, Toshimasa MATSUOKA†, and Kenji TANIGUCHI†, Members
SUMMARY Previously reported wideband CMOS low-noise ampli-fiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originat-ing from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) ap-plications is implemented in a 90 nm digital CMOS process. It occupies 0.12 mm2and achieves|S
11| < −10 dB, NF < 4.4 dB, and |S21| > 9.3 dB
across 3.1–10.6 GHz with a power consumption of 2.5 mW from a 1.0 V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.
key words: CMOS, low-noise amplifier (LNA), noise cancellation,
ultra-wideband (UWB), transformer
1. Introduction
Ultra-wideband (UWB) technology has attracted much in-terest in recent years, because of its ability to realize high-speed wireless personal area networks (WPANs), in which electronic devices are required to transfer large amounts of data, such as audio or video files, at a high data transfer rate. UWB frequency bands assigned from 3.1 to 10.6 GHz are utilized by two different communication systems: multiband orthogonal frequency division multiplexing (MB-OFDM) UWB [1] or single-carrier direct sequence (DS) UWB [2]. The MB-OFDM UWB system using 14 sub-bands, each with a bandwidth of 528 MHz, transmits signals modulated by OFDM in the subband. The data rate is up to 480 Mbps. The DS-UWB system spreads the spectrum over the low band (3.1–4.85 GHz) or high band (6.2–9.7 GHz), and pro-vides a maximum data rate of 1320 Mbps. In either case, wideband low-noise amplifiers (LNAs) are essential for the RF front-ends of UWB receivers.
The UWB LNA must meet several stringent require-ments: input impedance matching, low noise performance, and sufficient gain across 3.1–10.6 GHz at low power con-sumption, a low supply voltage, and low cost (i.e., small area and requiring no additional layers). In addition, it is desir-able to implement the LNA with digital CMOS technologies for the integration of RF front-ends and digital circuits.
Al-Manuscript received May 2, 2009. Manuscript revised August 30, 2009.
†The authors are with the Division of Electrical, Electronics
and Information Engineering, Graduate School of Engineering, Osaka University, Suita-shi, 565-0871 Japan.
a) E-mail: [email protected] DOI: 10.1587/transele.E93.C.187
though several wideband CMOS LNAs have been proposed in recent years, none of them have simultaneously met all these requirements. An LNA with wideband LC match-ing networks [3] consumes a large chip area. Although resistive-feedback LNAs [4]–[6] and common-drain feed-back LNAs [7], [8] occupy small chip areas, they require high power consumption and high supply voltages to si-multaneously achieve wideband input impedance matching and low noise performance. A reactive-feedback LNA [9], [10] demands two thick metal layers to form a transformer that provides a reactive feedback. Noise-canceling LNAs [11]–[14] require additional circuits and power consump-tion. Distributed LNAs [15], [16] consume much higher power and larger areas than other LNAs.
In this paper, we propose a transformer noise-canceling common-gate LNA employing an output series inductor [17]. The proposed LNA is suitable for low-power and low-voltage operation, and achieves|S11| < −10 dB, NF <
4.4 dB, and|S21| > 9.3 dB across 3.1–10.6 GHz. This
pa-per is organized as follows. Section 2 describes the pro-posed circuit topology and noise cancellation mechanisms. The noise, input admittance, gain, stability, and group de-lay of the proposed LNA are analyzed in Sect. 3. tion 4 describes the design methodology for the LNA. Sec-tion 5 shows the measurements of the LNA implemented in a 90 nm digital CMOS process, and Sect. 6 concludes the paper.
2. Transformer Noise-Canceling LNA
This section presents the circuit topology of the transformer noise-canceling CMOS LNA and the noise cancellation mechanisms.
2.1 Circuit Topology
Figure 1 shows a schematic of the proposed LNA, based on a common-gate (CG) LNA with a shunt-peaking inductor. The CG topology is suitable for low-voltage operation, be-cause it does not require a cascode transistor to alleviate the Miller effect from the CG transistor M1[18]. The main
dif-ference between the proposed LNA and the CG LNA is that the input and shunt-peaking inductors, Lpand Ls, are
mag-netically coupled to form a transformer. A similar topology has been reported for narrowband applications [19]. The transformer cancels the noise produced by M1and the load
resistor RL, thereby improving the noise performance
Fig. 1 Schematic of the proposed LNA.
out additional circuits or increased power consumption. The transformer also provides a positive feedback, whose mech-anism is as follows: An output current generated by a signal voltage flows through Ls, which induces a voltage that is in
phase with the signal voltage to Lp. The output series
induc-tor L1forms a π network with the parasitic capacitances, C1
and C2, extending not only the gain bandwidth, but also the
input bandwidth, which is defined as the frequency range of |S11| < −10 dB. The chip area of the proposed LNA is the
same as that of a CG LNA with a shunt-peaking inductor, because Lpcan be stacked on Ls, i.e., a stacked transformer,
which occupies the area of one inductor. 2.2 Noise Cancellation
The transformer partly cancels the output noise originating from the CG transistor M1and load resistor RL, thereby
im-proving the LNA noise performance. The small-signal cir-cuit of the proposed LNA is shown in Fig. 2, where the volt-age supply terminal (VDD) is connected to the AC ground;
the noise of the signal source resistance Rs, M1, and RLare
represented by the noise current sources ins, ind, and noise
voltage source vnRL, respectively; M, given by k
LpLs, is
the mutual inductance of the transformer and k the magnetic coupling factor; Cp represents the sum of the gate-source
capacitance of M1 and the parasitic capacitances of the
in-put pad and Lp; ZLis the load impedance considering the
right hand side of output node A. The mechanisms for the noise cancellation are conceptually illustrated in Figs. 3(a) and (b). The transformer detects noise currents flowing through the primary (or secondary) inductor Lp, inducing
voltages correlated with the currents to the secondary (or primary) inductor Ls.
2.2.1 Transistor Noise Cancellation
The output noise voltage generated by ind is partly canceled
by the induced noise voltage originating from ind flowing
through Lp, as shown in Fig. 3(a). The noise current indfirst
flowing through Ls and RL generates a noise voltage vn1 =
Fig. 2 Small-signal equivalent circuit with noise sources.
−ind(RL+ sLs), and then a noise voltage vn1 = −ind · sM
is induced in Lp. Next, ind flows through Lp, producing a
noise voltage vn2 = ind· sLp, which is canceled by vn1. Here,
the transformer induces a noise voltage vn2 = ind· sM in Ls.
The induced noise voltage vn2is correlated and in antiphase with vn1and hence the total output noise voltage is reduced:
−ind(RL+ sLs− sM). The expression of the output noise
voltage (at node A) including the effect of ZLcan be derived
from Fig. 2: vout,ind= −indZL ×n 2k2−nk+1 Rs+sCp+ 1 sLp RL+s(1−k2)Ls 1 Rs + YIN ZL+RL+s(1−k2)Ls , (1)
where n= Ls/Lpis the turn ratio of the transformer; YIN=
iin/vin, described in the next section, is the input admittance
of the LNA, and iinand vinare the input current and voltage,
respectively, as shown in Fig. 2. The term of s(1− k2)L
sin
the numerator of Eq. (1) shows that the transistor noise is partly canceled by the transformer.
2.2.2 Load Resistor Noise Cancellation
The CG transistor M1drains a part of the output noise
cur-rent originating from vnRL, reducing the output noise
volt-age, as shown in Fig. 3(b). The noise current due to vnRL,
which is given by vnRL/(sLs+ RL+ ZL), first flows through Ls and then the transformer induces a noise voltage vnRL =
−sMvnRL/(sLs+ RL+ ZL) in Lp. The transistor M1detects a
gate-source voltage vgs= vnRL/sLp(1/Rs+gm+sCp+1/sLp),
and drains noise current of gmvgsaccordingly. This results in
a reduction of the output noise current originating from vnRL.
Considering the noise current due to M1, we can obtain the
output noise current flowing ZL:
iout,vnRL = 1 Rs + (1 − nk)gm+ sCp+ 1 sLp vnRL 1 Rs + YIN ZL+ RL+ s(1 − k2)Ls , (2)
and the output noise voltage (at node A), vout,vnRL, is given
Fig. 3 Mechanisms for noise cancellation of (a) indand (b) vnRL.
Fig. 4 Simulated NF and NFminof the LNAs with and without noise
cancellation (k= 0, 1.0).
noise cancellation. 2.2.3 Verification
The effectiveness of the transformer noise cancellation is verified through simulation. Figure 4 shows the simulated
NF and NFmin of the proposed LNAs with and without the
noise cancellation (i.e., k = 0, 1.0), where 90 nm CMOS process parameters are used and Rprepresents the parasitic
resistance of Lp. The LNA with k= 0 corresponds to a CG
LNA with a load resistor and shunt-peaking inductor. The
Fig. 5 Simulated noise contributions from M1, RL, and Rpto the LNAs
with and without noise cancellation (k= 0, 1.0).
NF of the LNA with k = 1.0 is up to 2.2 dB lower than
that of the LNA with k = 0. Figure 5 shows the simulated noise factors contributed from M1, RL, and Rp (FM1, FRL,
and FRp, respectively) with and without the noise
cancella-tion. The transformer reduces FM1by up to 35% and FRLby
65%. The contribution from Rpalso slightly decreases and
hence Rpcontributes little to the overall NF (i.e., 0.1 dB in
Fig. 4). The noise contributions from M1 and RL change
with the turn ratio. A noise optimization procedure will be presented in the next section.
3. Circuit Analysis
The transformer improves the LNA noise performance at the cost of the input and gain bandwidths. The output series inductor L1 extends both the bandwidths. In this section,
the noise, input admittance, gain, stability, and group de-lay of the LNA are analyzed, and noise optimization and impedance matching procedures are presented.
3.1 Noise
The amount of noise cancellation is mainly determined by the turn ratio of the transformer. From the small-signal equivalent circuit shown in Fig. 2, the output noise voltage due to Rsis given by vout,ins = ZL gmRL+ nk + s(1 − k2)Lsgm ins 1 Rs + YIN ZL+ RL+ s(1 − k2)Ls. (3)
Using Eqs. (1)–(3), we obtain the noise factor of the pro-posed LNA: F ≈ 1 + FM1+ FRL, (4) FM1 = vout,ind vout,ins 2
= n2− n + 1 Rs + jωCp+ 1 jωLp RL gmRL+ n 2 γgd0Rs, (5) FRL = vout,vnRL vout,ins 2 = (1− n) gmRL+ 1 Rs + jωCp+ 1 jωLp RL gmRL+ n 2 Rs RL , (6) where gd0 is the zero-bias drain conductance of M1; the
coefficient of channel thermal noise γ equals 2/3 in long-channel MOSFETs, but exceeds this value in short-long-channel MOSFETs [20]–[22]. The value of γ in a fabricated 90 nm MOSFET is approximately two, shown by the measured and simulated NF of the LNA, as will be shown in Sect. 5. For simplicity, the magnetic coupling factor k is assumed to be one. The parasitic resistance of Lp, the parasitic capacitance
between Lp and Ls, and the induced-gate noise current of
M1are ignored, because they do not have a significant effect
on the overall NF. The transconductance gmand load
re-sistance RLcannot be optimized for noise, because they are
determined from input impedance matching conditions, as will be shown in the following subsection.
The optimum n for the noise performance can be ob-tained from Eqs. (4)–(6). Setting the derivatives of Eqs. (5) and (6) with respect to n to zero (i.e., ∂FM1/∂n = 0 and
∂FRL/∂n = 0 for ω = 1/ LpCp), we can obtain nopt,ind= −gmRL+ (gmRL)2+ gmRL+ RL Rs , (7) nopt,vnRL = 1 +g1 mRs , (8)
for which a minimum FM1 and FRL are achieved,
respec-tively. Similarly, the optimum n for F, nopt, can be obtained
from ∂F/∂n= 0: n2opt− nopt+ RL Rs × n2opt+ (2nopt− 1)gmRL− RL Rs γgd0 − 1− nopt gm+ 1 Rs g2 mRL+ gm+ 1 Rs RL= 0. (9)
Figures 6(a) and (b) show the calculated F, FM1, and FRL
(RL = 50 Ω) versus n and NF with RL as a parameter at
ω = 1/LpCp, respectively. For RL= 50 Ω, minimum FM1,
FRL, and F are achieved for n of 0.68, 1.66, and 1.0, given
by Eqs. (7)–(9), respectively. Figure 6(b) shows that the cal-culated NF (RL = 150 Ω) for n = 1.0 is consistent with
the simulated NF (k = 1.0) at 7.2 GHz, shown in Fig. 4, although Rp is ignored in Eqs. (4)–(6). Moreover, the NF
becomes a minimum around one even with varying RLfrom
50 to 200Ω. A large n makes the LNA unstable, as will be
Fig. 6 Calculated (a) F, FM1, and FRL(RL= 50 Ω) versus n and (b) NF
with RLas a parameter.
explained in Section 3.4, and leads to an increase in the par-asitic capacitance of Ls, causing poor high-frequency
per-formance. The optimum n is thus determined to be one. 3.2 Input Impedance Matching
In the proposed topology with the input and shunt-peaking inductors coupled, the output load affects the LNA input impedance through the coupling. The output series induc-tor L1 contributes to wideband input impedance matching.
From Fig. 2, the input admittance of the proposed LNA, YIN,
is given by
YIN( jω)= gm+ jωCp+
1
jωLp + Y
T. (10)
The first three terms in Eq. (10) represent the input admit-tance of the CG LNA. The last term YT is generated by
cou-pling Lpand Ls, and is given by
YT( jω)=
nk(nk− gmZL)
RL+ ZL+ jωn2Lp(1− k2)
. (11) When L1 is connected in series with the output, ZL is
Fig. 7 Calculated real and imaginary parts of (a) YTand (b) YIN, and (c) S11of the LNAs with and without L1. ZL( jω)= 1 jωC1 // jωL1+ 1 jωC2 , (12) where C1 represents the sum of the gate-drain capacitance
of M1and the parasitic capacitance of L1; C2, which is
typ-ically larger than C1, represents the sum of the input
capac-itance of the following stage and the parasitic capaccapac-itance of L1. Equations (10)–(12) show that YIN is a function of
YT, whose frequency behavior significantly depends on that
of ZL. From Eqs. (10)–(12), the calculated frequency
behav-ior of YT is shown in Fig. 7(a) (solid line), and that of YT
for ZL( jω)= 1/ jω(C1+ C2) is also shown for comparison
(dashed line). The π network consisting of C1, L1, and C2
acts as a short or an open [23] (i.e., ZL= 0 or ∞), providing
a maximum and minimum Re[YT( jω)] and Im[YT( jω)]:
Re[YT( jω)]max≈ n2k2 RL , (13) Re[YT( jω)]min≈ −nkgm, (14) Im[YT( jω)]max≈ nk 2 gm+ nk RL , (15) Im[YT( jω)]min≈ − nk 2 × ⎛ ⎜⎜⎜⎜⎜ ⎜⎝ gm L1C2 C1+C2 L1C2 C1+C2 + n 2(1− k2)L p + nk RL ⎞ ⎟⎟⎟⎟⎟ ⎟⎠ , (16) at the following frequencies:
ω1= 1 √ L1C2 , (17) ω2= 1 L1CC11+CC22 , (18) ω3≈ ωc= 1 RL(C1+ C2) , (19) ω4≈ RL L1C2 C1+C2+ n 2(1− k2)Lp, (20)
respectively. The above equations and approximations are derived from the following conditions: ZL = 0 and
jωn2(1− k2)L
pis ignored against RLin Eqs. (13) and (17);
ZL = ∞ in Eqs. (14) and (18); ZL = 1/ jω(C1 + C2)
and ω2n2(1− k2)L
p(C1+ C2) 1 in Eqs. (15) and (19);
ZL = jωL1C2/(C1+ C2) in Eqs. (16) and (20). A negative
Re[YT( jω)] shown in Eq. (14) originates from the positive
feedback provided by the transformer. The calculated YINis
also shown in Fig. 7(b). The real part of YIN, Re[YIN( jω)],
is simply shifted by gmfrom Re[YT( jω)], and the imaginary
part of YIN, Im[YIN( jω)], becomes zero at resonance
fre-quencies. The first resonance frequency ω0is derived from
the following equation: Im[YIN( jω0)]≈ jω0Cp+ 1 jω0Lp + jω0 nk(C1+ C2)(nk+ gmRL) 1+ ω2 0R 2 L(C1+ C2)2 = 0, (21) where the last term in Im[YIN( jω0)] is Im[YT( jω0)] for ZL=
1/ jω0(C1+ C2) and ω20n2(1− k2)Lp(C1+ C2) 1.
The requirements of gmand RLare derived from the
in-put impedance matching condition in the frequency range from ω0 to ω1. For input impedance matching (|S11| <
−10 dB), YINmust satisfy the following condition:
|S11| =
1− RsYIN
1+ RsYIN
When Im[YIN( jω)]= 0, Eq. (22) can be simplified to
10 mS < Re[YIN( jω)] < 38 mS. (23)
At ω0, Im[YIN( jω0)] = 0 and the real part of YIN( jω) is
approximated as Re[YIN( jω0)]≈ gm ⎛ ⎜⎜⎜⎜⎝1 − nk 1+ ω20R2L(C1+ C2)2 ⎞ ⎟⎟⎟⎟⎠, (24) where ω20nkRL(C1+C2)2/gm 1. Substituting Eq. (24) into
Eq. (23) gives the lower limit to gm:
10 mS < gm ⎛ ⎜⎜⎜⎜⎝1 − nk 1+ ω2 0R2L(C1+ C2)2 ⎞ ⎟⎟⎟⎟⎠. (25) In the frequency range from ω0 to ω1, the real and
imagi-nary parts of YIN reach the maximum values at ω1and ω3,
respectively: Re[YIN( jω)]max= gm+ n2k2 RL , (26) Im[YIN( jω)]max= ω3Cp− 1 ω3Lp + nk 2 gm+ nk RL , (27) where ω0 < ω3 < ω1 and ω3 < 1/ LpCp are
as-sumed. Substituting Eqs. (26) and (27) into Eq. (22), we can have the worst case upper limit to gmand lower limit
to RL. For example, when Im[YIN( jω)] is negligible against
Re[YIN( jω)] (around ω1), the following condition is derived
from Eqs. (22) and (26): gm+
n2k2 RL
< 38 mS. (28)
An impedance matching procedure for the proposed LNA is as follows:
1. Select gmand RLto satisfy Eqs. (25) and (28)
2. Select Lp such that ω0 equals the lower edge of the
desired input band
3. Select L1such that ω4equals the upper edge of the
de-sired input band
Figure 7(c) shows the calculated S11 of the LNAs
with and without L1, where ω0 and ω4 are set to
approxi-mately 3.1 GHz and 10.6 GHz, respectively. A transconduc-tance of 30 mS, a load resistransconduc-tance of 150Ω, and other val-ues shown in Fig. 7 result in Re[YIN( jω)]max 35 mS and
Im[YIN( jω)]max 10 mS, allowing |S11| < −10 dB from ω0
to ω1. Around ω4, the π network including L1 decreases
Re[YIN( jω)] and Im[YIN( jω)]:
Re[YIN( jω4)]= gm− nk 2RL ω 4L1C2gm C1+ C2 − nk , (29) Im[YIN( jω4)]= ω4Cp− 1 ω4Lp − nk 2RL ω 4L1C2gm C1+ C2 + nk , (30)
providing |S11| < −10 dB. Consequently, the input
impedance matching is achieved from ω0to ω4.
3.3 Gain
The transformer provides the positive feedback from node A to the input, as shown in Sect. 2.1. The transformer positive feedback reduces the gain (S21) bandwidth of the LNA. The
S21of the LNA with output impedance matching is given by
S21= vout vs/2 = 2vin vs vout vin = 2 1+ RsYIN Av, (31)
where vs is the signal voltage and Av, defined by vout/vin, is
the voltage gain from the input to the output of the LNA, as shown in Fig. 2. Equation (31) shows that the frequency response of Av is shaped by that of YIN (i.e., S11), which
results in that of S21.
The frequency response of Av of the proposed LNA
is similar to that of a CG LNA with a load resistor and output series inductor. The output network combining a shunt-peaking inductor with an output series inductor gives a larger bandwidth than the counterpart with either induc-tor, as explained in [23], [24]. However, the shunt-peaking inductor Lsin the proposed LNA does not increase the
band-width. The Avof the LNA is given by
Av(s)= gmRL 1+gnk mRL + 1−k2 m1 s ωc 1+ωs c + 1−k2 m1 + 1−kc m2 s2 ω2 c + kc(1−kc) m2 s3 ω3 c + 1−k2 m1 kc(1−kc) m2 s4 ω4 c , (32) where kc = C1/(C1 + C2), m1 = R2L(C1 + C2)/Ls, and
m2 = R2L(C1+ C2)/L1[24]. Substituting k= 0 into Eq. (32)
gives the Avof the CG LNA with both the shunt-peaking and output series inductors. Equation (32) shows that all m1are
divided by a factor of (1−k2), i.e., L
sis multiplied by a factor
of (1− k2). This means that the effective L
sin the proposed
LNA becomes small, compared with the shunt-peaking in-ductor in the CG LNA, and then contributes less to band-width extension. The calculated Avwith k as a parameter is
shown in Fig. 8, where fc = 4.2 GHz, kc = 0.4, m1 = 1.6,
and m2 = 2.25 originate from C1 = 100 fF, C2 = 150 fF,
Ls = 3.5 nH, L1 = 2.5 nH, and RL = 150 Ω. A very large
peak (ripple) is found when k= 0, because Lsis larger than
L1, i.e., m1 < m2 [23], [24]. Figure 8 shows that both the
peak and bandwidth decrease as k increases. Consequently, the bandwidth of the proposed LNA (k 0.9) closely equals that of the CG LNA with only the output series inductor. A flat voltage gain of the CG LNA across the entire UWB frequency band can be obtained by selecting an appropriate value of m2(approximately 2), as discussed in [24].
An S21 variation of the proposed LNA mainly
origi-nates from the characteristic of YIN (S11). As shown in
Fig. 7(c), the input impedance matching condition improves around ω0and ω4, but deteriorates around ω1. This means
Fig. 8 Calculated Avof the proposed LNA with k as a parameter.
Fig. 9 Calculated Avand S21of the proposed LNA with k= 0.9.
the LNA, compared to that of ω0or ω4, which results in a
reduction in the magnitude of S21around ω1. The difference
between S21( jω0) and S21( jω1) can be approximated from
Eq. (31): ΔS21= S21( jω0) S21( jω1) = 1+ RsYIN( jω1) 1+ RsYIN( jω0) ≈ 1+ Rs· Re[YIN( jω1)] 1+ Rs· Re[YIN( jω0)] , (33)
where Av( jω0) = Av( jω1) is assumed, the real parts of
YIN( jω0) and YIN( jω1) are given by Eqs. (24) and (26),
respectively, and the imaginary parts of YIN( jω0) and
YIN( jω1) can be neglected, as shown in the previous
subsec-tion. Figure 9 shows the calculated Avand S21 of the
pro-posed LNA with k= 0.9. Substituting the parameters shown in Fig. 9 into Eq. (33) givesΔS21 = −3.6 dB, while an S21
variation of−4.7 dB is seen in Fig. 9, and then −1.1 dB orig-inates from the difference of Av. The difference of S21 can
be reduced by decreasing RL, as shown by Eqs. (24), (26),
and (33). Moreover, using a common-source (CS) ampli-fier with a gain peak around ω1as the second stage, we can
obtain a flat gain.
|ΓS| < 1, (34)
|ΓL| < 1, (35)
|ΓIN| < 1, (36)
|ΓOUT| < 1, (37)
whereΓS, ΓIN, ΓL, and ΓOUT represent the source, input,
load, and output reflection coefficients, respectively. Equa-tions (34)–(37) state that the real parts of the input and output impedances for passive source and load impedances must be positive [25]:
Re[ZIN] > 0, (38)
Re[ZOUT] > 0. (39)
In what follows, to simplify the expression of the output impedance of the LNA, we will verify whether the LNA without the output π network (C1, L1, and C2) satisfies the
above conditions or not.
First, the real part of the input admittance of the LNA can be derived from Eqs. (10)–(11) for ZL= ∞:
Re[YIN( jω)]= gm(1− nk) . (40)
In the case of the proposed LNA, n is selected to be one, shown in Sect. 3.1, and k of the on-chip transformer is less than one [26]: nk < 1. The requirement of Eq. (38) is thus satisfied. Next, the output impedance considering the left hand side of output node A (Fig. 2) is given by
ZOUT,A( jω)= 1 Rs+ gm+ jωCp RL+ jω(1 − k2)Ls + n2+ RL jωLp 1 Rs + gm(1− nk) + jωCp+ 1 jωLp . (41) Equation (41) indicates that the real part of ZOUT,Abecomes
a maximum around ω= 1/LpCpand can be approximated
by Re[ZOUT,A( jω)]≈ RL, (42) Re[ZOUT,A( jω)]≈ RL+ (1− k2)L s Cp 1 Rs + g m , (43)
at low and high frequencies (i.e., ω 1/LpCp and
ω 1/LpCp), respectively. The requirement of Eq. (39)
is therefore satisfied.
The stability is also ensured through simulation. Fig-ure 10 shows the simulated K and B1of the proposed LNA,
which are given by [25]
K= 1− |S11|
2− |S
22|2+ |Δ|2
2|S12S21|
Fig. 10 Simulated K and B1of the proposed LNA.
B1= 1 + |S11|2− |S22|2− |Δ|2, (45)
respectively, whereΔ = S11S22 − S12S21. The necessary
and sufficient conditions for unconditional stability are K > 1 and B1 > 0 [25]. The simulations show that the LNA
satisfies these conditions across the entire UWB frequency band.
3.5 Group Delay
A group delay variation is important for DS-UWB or pulse-based UWB systems. The group delay is the derivative of the phase of the signal transfer function (S21), and hence
any resonance in the signal path contributes to the variation [27]. The critical resonances in the proposed LNA origi-nate from the combinations of Lp (transformer) and Cp at
the input, and L1, C1, and C2 at the output, and these
res-onance frequencies, ω0and ω2, are given by Eqs. (21) and
(18), respectively. Pushing the resonance frequencies out of the desired frequency band (i.e., increasing Lpor decreasing
L1) allows a small group delay variation. Figure 11 shows
that the simulated group delays of the proposed LNA with
Lpand L1as a parameter. The group delay (for Lp= 3.0 nH
in Fig. 11(a)) dramatically changes around 3 GHz (ω0) and
11 GHz (ω2). The simulations also show that the variation
can be reduced by increasing Lpor decreasing L1.
4. Design
By using a 90 nm CMOS process and device parameters, the proposed LNA is designed to satisfy the following typical specifications of the UWB LNA:|S11| < −10 dB, NF <
4 dB, and|S21| > 10 dB across the entire UWB frequency
band (3.1–10.6 GHz). Current consumption is set to 2.5 mA at a 1.0 V supply.
4.1 Input Transistor and Load Resistor
The transconductance gmand load resistance RL are
deter-mined by the input impedance matching conditions, given
Fig. 11 Simulated group delays with (a) Lpand (b) L1as a parameter.
by Eqs. (25) and (28), and the desired gain. A transconduc-tance of 30 mS and load resistransconduc-tance of 145Ω provide both |S11| < −10 dB and Av 14 dB† in the lower UWB band
(3.1–5 GHz). The load resistance includes the parasitic re-sistance of Ls. A bias current of 2.5 mA and gmof 30 mS
result in a gate width of 4× 10 μm (10 gate fingers, each with a unit of of 4 μm width) and gate length of 100 nm. 4.2 Transformer
The transformer adopts a stacked configuration in which Lp
is stacked on Ls. This configuration provides the largest
coupling factor and a small area [26]. The large parasitic resistance of Ls, due to the lower thin metal layer, is not
problematic, because it can be absorbed into RL.
The parasitic capacitance between Lpand Ls, Cc, has a
relatively small effect on the LNA performance. This capac-itance significantly affects the frequency response of a non-inverting transformer [26]. Although the proposed LNA em-ploys the noninverting stacked transformer, the signal cur-rent injected into Ls by M1 reduces the effect of Cc.
Fig-ure 12 shows the simulated S11and NF of the LNA includ-†At low frequencies, Av≈ g
Fig. 12 Simulated S11and NF of the LNA with Ccas a parameter.
ing Cc. In the lower UWB band, Ccslightly decreases the
magnitude of the S11 and has little impact on the NF; in
the higher, a large Cc decreases the input bandwidth and
increases the NF by up to 0.20 dB. In the simulations, for wideband input impedance matching, Ccmust be less than
300 fF, which can be realized even with the stacked trans-former.
The transformer is designed to achieve|S11| < −10 dB
(of the LNA) in the lower UWB band and NF < 4.0 dB across the entire UWB band. Selecting Lp such that ω0
equals approximately 3.1 GHz allows the LNA to achieve |S11| < −10 dB in the lower band. A wide metal for
real-izing Lp reduces the parasitic resistance; however, it leads
to a large chip area and large parasitic capacitance. For Lp,
we adopt a 3.5-turn square inductor with an outer diameter of 165 μm, metal width of 3 μm, and metal spacing of 2 μm. To achieve a turn ratio of one, Lsis designed as follows: an
outer diameter is 165 μm, a metal width 2 μm, and a metal spacing 3 μm. The metal thicknesses of Lp (top pad metal)
and Ls(metal 6) are 1.9 μm and 0.9 μm, respectively†. The
parasitic capacitance Cc is reduced by offsetting the
up-per metal layer from the lower by short horizontal distance (3 μm), which results in Cc 240 fF. Three-dimensional
(3-D) electromagnetic (EM) simulations by Ansoft HFSS showed Lp= Ls= 4.0 nH and k = 0.9 at low frequencies.
4.3 Output Series Inductor
The output series inductor L1is designed to set ω4to the
up-per edge of the desired input band (10.6 GHz). We use a rel-atively low Q inductor to reduce the chip area and parasitic capacitance, which reduces the gain bandwidth of the LNA. The outer diameter of L1 is 140 μm, the metal width 3 μm,
the metal spacing 2 μm, and the metal thickness 1.9 μm (top pad metal)†. EM simulations showed that the inductance and maximum Q were 3.2 nH and 6.0 (at 5.0 GHz), respec-tively.
5. Experimental Results and Discussion
The designed LNA was fabricated in a 90 nm digital CMOS
Fig. 13 Micrograph of the fabricated LNA.
process without metal-insulator-metal (MIM) capacitors. A micrograph of the fabricated LNA is shown in Fig. 13. The active chip area excluding pads was 0.48×0.25 mm2. The
in-put and outin-put pads were not electrostatic-discharge (ESD) protected. Metal fills consisting of metal 1–6 layers were placed both inside and outside the fabricated transformer and inductor to meet metal density rules in the CMOS pro-cess. They were 1.5 μm by 1.5 μm squares with a spacing of 0.2 μm. The average horizontal distance between the metal fills and traces of the inductors was 15 μm. For measure-ments, a unity-gain CS amplifier with a 50Ω output resistor was used as a buffer. The S-parameters, noise, and linearity of the LNA were measured using on-wafer RF probes. The power consumption of the LNA and buffer were 2.5 mW and 4.0 mW, respectively, at a supply voltage of 1.0 V.
Figure 14 shows the measured and simulated S11 and
S21 of the LNA. The LNA achieved |S11| < −10 dB and
|S21| > 9.3 dB across 3.1–10.6 GHz. The discrepancy
between the measurements and simulations at frequencies above 4 GHz is mainly attributed to insufficient accuracy in the simulations of the transformer and inductor used. The HFSS simulation models of the transformer and inductor included no metal fills to solve convergence problems and reduce the memory requirement. The metal fills increase the parasitic capacitances and resistances of the transformer and inductor [28]–[30], which results in the discrepancy.
Figure 15 shows the measured and simulated S12 of
the LNA with the buffer. The LNA achieved |S12| < −34 dB
across 3.1–10.6 GHz. The measured S12 of the stand-alone
buffer (not shown) was less than −24 dB over the same fre-quency range. Thus, the S12 of the LNA without the buffer
was less than −10 dB. The poor reverse isolation perfor-mance is due to the transformer, and an additional stage may be required to improve the isolation performance.
Figure 16 shows the measured and simulated group
de-†The inductors L
pand L1 in the previous work [17] were
im-plemented by using metal 6 layers (0.9 μm thick) and Lsby using a
metal 5 layer (0.3 μm thick). This leads to the differences between the simulations/measurements shown in [17] and in Sect. 5.
Fig. 14 Measured and simulated S11and S21of the LNA.
Fig. 15 Measured and simulated S12of the LNA.
lays. The group delay variation increased around the edge of the UWB frequency band, as analyzed in Sect. 3.5. A group delay variation of approximately 60 ps was achieved for the entire band.
Figure 17 shows the measured and simulated NF of the LNA. Note that these results included the noise of the out-put buffer, which increased the overall NF by 0.8 dB for an LNA gain of 10 dB in simulation. The LNA with the buffer achieved an NF of 3.8–4.4 dB†across the entire UWB band. This means that the proposed LNA with an additional CS amplifier like the buffer can achieve NF < 4.4 dB. The difference between the measurements and simulations can be explained by the extra input-referred noise of the buffer, caused by the lower measured gain than the simulated one.
Figure 18 shows the measured output power of the fun-damental tone and third-order intermodulation (IM3)
prod-ucts for two tones (3.000 GHz and 3.001 GHz). The mea-sured input third-order intercept point (IIP3) and 1-dB
com-pression point (including the effect of the output buffer) were approximately−9.3 dBm and −20 dBm, respectively. Figure 19 shows IIP3 and IIP2measured by applying two
tones ( fI1and fI2) with 1-MHz spacing. The measured
fre-quency range of 3–6 GHz was limited by a signal
genera-Fig. 16 Measured and simulated group delays of the LNA.
Fig. 17 Measured and simulated NF of the LNA.
tor, and IM3and IM2products were measured at 2 fI1− fI2
and fI1 + fI2††, respectively. The LNA obtained IIP3 >
−9.3 dBm and IIP2 > −6.3 dBm in the frequency range.
Table 1 shows a summary of the LNA performance and a comparison with previously reported wideband CMOS LNAs. The proposed LNA achieved input impedance matching and comparable noise performance across the en-tire UWB band with the lowest reported power consumption and supply voltage. The LNA also consumed the smallest chip area among the 3.1–10.6 GHz LNAs employing induc-tors [10], [11], [16], [24].
An additional amplifier stage can allow the proposed LNA to achieve more and flatter gain across 3.1–10.6 GHz. A relatively low gain of the implemented LNA (> 9.3 dB) leads to an increase in the overall NF of the receiver. For instance, the NF specification for RF receivers of the
MB-†We found noise measurement errors in the previous work
[17]. We overmeasured the loss of an input cable by approximately 1.0 dB. This resulted in smaller measured NF in [17] by 1.0 dB.
††Due to the wideband characteristic of a UWB LNA, IM 2
prod-ucts at fI1+ fI2generated by the LNA do not decrease and then
Fig. 18 Measured IIP3of the LNA at 3 GHz.
Fig. 19 Measured IIP3and IIP2of the LNA.
Table 1 Measured performance and comparison of wideband CMOS LNAs.
Reference TechnologyCMOS [GHz]BW∗ [dB]NF [dB]S21 [dBm]IIP3 Supply[V] Power[mW]† [mmArea2] Topology
This work 90 nm 2.8–12 3.8–4.4‡ 9.3–13.1‡ −9.3 1.0 2.5 0.12 Transformer noise-canceling CG
[4] 90 nm 0.5–6.2 1.9–2.6 25 −16 2.7 35.2 0.025 Resistive feedback CS [6] 90 nm 0.5–5.0 2.3–2.6 21–22 −8.8 1.8 12 0.012 Resistive feedback CS [7] 90 nm 0–6 3.4–4.3 12.5–15.3 N/A 1.0 3.4 0.0017 Common-drain feedback CS [8] 130 nm 1–7.4 >2.4 15–17 −4.1 1.4 25 0.019 Common-drain feedback CS [10] 130 nm 3.1–10.6 2.1–2.9 13.7–16.5 −8.5 1.2 9.0 0.40 Reactive feedback CS [11] 180 nm 0–14.1 4.5–5.1‡ 12.0–13.7‡ −6.2 1.8 20 0.50 Noise-canceling CG using CS [13] 65 nm 0.2–6.2 2.8–4.2 9.9–15.6 0 1.2 14 0.009 Noise-canceling CG using CS [14] 130 nm 3.7–8.8 3.6–4.5 8.1–11 −7.2 1.5 19 0.05 Noise-canceling CS [16] 180 nm 1–11 2.9–3.0 8–9 −3.55 1.8 21.6 0.20 Distributed [24] 180 nm 2.6–10.7 4.4–5.3‡ 6.0–8.5‡ 7.4 1.8 4.5 0.40 Capacitor cross-coupled CG ∗Input bandwidth†Without buffers‡3.1–10.6 GHz frequency range Voltage gainInput-output differential topology
flatter gain (|S21| > 20 dB) and the same noise performance
as the LNA without the CS amplifier (NF < 4.3 dB) across 3.1–10.6 GHz. The group delay variation (not shown) was reduced to approximately 20 ps. Considering the measure-ments of the fabricated LNA, we conclude that the proposed LNA with the CS amplifier can achieve|S21| > 20 dB and
NF< 4.4 dB across 3.1–10.6 GHz with an additional power
consumption of 2.0 mW and chip area of 55× 55 μm2.
6. Conclusion
We have demonstrated a transformer noise-canceling UWB CMOS LNA with an output series inductor. The trans-former partly cancels the noise of the common-gate tran-sistor and load retran-sistor, thereby improving the LNA noise performance. The output series inductor improves both the gain and input bandwidths. Circuit analysis showed
Fig. 21 Simulated S21 and NF of the LNAs with and without the
common-source amplifier.
that the best turn ratio for the noise performance is one and input impedance matching depends not only on the common-gate transistor but also on the load resistor. The LNA designed for UWB applications was fabricated in a 90 nm digital CMOS process. The fabricated LNA occu-pied 0.12 mm2, and achieved|S
11| < −10 dB, NF < 4.4 dB,
and|S21| > 9.3 dB across 3.1–10.6 GHz, while consuming
2.5 mW from a 1.0 V supply. The proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.
Acknowledgment
The chip in this study was fabricated through the chip fabrication program of the VLSI Design and Education Center (VDEC), the University of Tokyo, in collaboration with Semiconductor Technology Academic Research Cen-ter (STARC), Fujitsu Limited, Matsushita Electric Industrial Company Limited., NEC Electronics Corporation, Renesas Technology Corporation, and Toshiba Corporation. In addi-tion, this study was financially supported by a grant to the Osaka University Global COE Program, “Center for Elec-tronic Devices Innovation” from the Ministry of Education, Culture, Sports, Science and Technology of Japan, and Ini-tiatives for Attractive Education in Graduate Schools from Japan Society for the Promotion of Science (JSPS).
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Takao Kihara received the B.S., M.S., and Ph.D. degrees in electronic engineering from Osaka University, Osaka, Japan, in 2005, 2006, and 2009, respectively. His current research in-terests include CMOS RF transceivers.
Toshimasa Matsuoka received the B.S., M.S., and Ph.D. degrees in electronic engineer-ing from Osaka University, Osaka, Japan, in 1989, 1991, and 1996, respectively. During 1991–1998, he worked for the Central Research Laboratories, Sharp Corporation, Nara, Japan, where he was engaged in the research and devel-opment of deep submicron CMOS devices and ultra thin gate oxides. Since 1999, he has been working for Osaka University, where he is As-sociate Professor now. His current research in-cludes MOS device modeling and CMOS RF circuits. Dr. Matsuoka is a member of the Japan Society of Applied Physics (JSAP), the Institute of Electrical Engineers of Japan (IEEJ), and the Institute of Electrical and Electronic Engineers (IEEE).
modeling and the design of MOS LSI fabri-cation technology. He was a Visiting Scien-tist at Massachusetts Institute of Technology, Cambridge, from July 1982 to November 1983. Presently, he is a Professor of Electrical, Elec-tronic and Information Engineering at Osaka University. His current re-search interests are analog circuits, radio frequency circuits, device physics and process technology. Prof. Taniguchi is a member of the Japan Society of Applied Physics (JSAP), the Institute of Electrical Engineers of Japan (IEEJ), and the Institute of Electrical and Electronic Engineers (IEEE).
