NCV5171JP - 1.5 A 280 kHz/560 kHz 昇圧レギュレータ

(1)

昇圧レギュレータ

NCV5171/73 製高率 1.5 A

集積

蔵

280 kHz/560 kHz

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−40 ° C 125 ° C

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517xE = Specific Device Code x = 1 or 3

A = Assembly Location L = Wafer Lot

Y = Year

W = Work Week G = Pb−Free Package

SOIC−8 D SUFFIX CASE 751

V_CC SS

1

517xEALYWG

8

AGND Test

PGND FB

V_SW V_C

MARKING DIAGRAM AND PIN CONNECTIONS

Device Package Shipping^† ORDERING INFORMATION

NCV5171EDR2G SOIC−8 (Pb−Free)

2500 Units / Box

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

NCV5173EDR2G SOIC−8 (Pb−Free)

2500 Units / Box www.onsemi.jp

(2)

+

NCV5171/73

1

2

3

4 5

6 7

8 V_OUT

L1

5 V

C3 22 mF V_C

FB Test

SS V_CC

AGND PGND V_SW

+

MBRS120T3 D1

22 mH

C2 22 mF R3

1.28 k 3.72 k R2

C1

SS 3.3 V

R1 5 k 0.01 mF

Figure 1. Applications Diagram

MAXIMUM RATINGS

Rating Value Unit

Junction Temperature Range, T_J −40 to +150 °C

Storage Temperature Range, T_STORAGE −65 to +150 °C

Package Thermal Resistance Junction−to−Case, R_qJC Junction−to−Ambient, R_q_JA

45 165

°C/W

Lead Temperature Soldering: Reflow (Note 1) 260 Peak

(Note 1) °C

ESD, Human Body Model 1.2 kV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

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1. 60−180 seconds minimum above 237°C.

MAXIMUM RATINGS

Pin Name Pin Symbol V_MAX V_MIN I_SOURCE I_SINK

IC Power Input V_CC 35 V −0.3 V N/A 200 mA

Shutdown/Sync SS 30 V −0.3 V 1.0 mA 1.0 mA

Loop Compensation V_C 6.0 V −0.3 V 10 mA 10 mA

Voltage Feedback Input FB 10 V −0.3 V 1.0 mA 1.0 mA

Test Pin Test 6.0 V −0.3 V 1.0 mA 1.0 mA

Power Ground PGND 0.3 V −0.3 V 4 A 10 mA

Analog Ground AGND 0 V 0 V N/A 10 mA

Switch Input V_SW 40 V −0.3 V 10 mA 3.0 A

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ELECTRICAL CHARACTERISTICS (2.7 V< V_CC < 30 V; −40°C < T_J < 125°C unless otherwise stated)

Characteristic Test Conditions Min Typ Max Unit

Positive and Negative Error Amplifiers

FB Reference Voltage V_C tied to FB; measure at FB 1.246 1.276 1.300 V

FB Input Current FB = V_REF −1.0 0.1 1.0 mA

FB Reference Voltage Line Regulation V_C = FB − 0.01 0.03 %/V

Positive Error Amp Transconductance I_VC = ±25 mA 300 550 800 mMho

Positive Error Amp Gain (Note 2) 200 500 − V/V

V_C Source Current FB = 1.0 V, V_C = 1.25 V 25 50 90 mA

V_C Sink Current FB = 1.5 V, V_C = 1.25 V 200 625 1500 mA

V_C High Clamp Voltage FB = 1.0 V; V_C sources 25 mA 1.5 1.7 1.9 V

V_C Low Clamp Voltage FB = 1.5 V; V_C sinks 25 mA 0.25 0.50 0.65 V

V_C Threshold Reduce V_C from 1.5 V until switching stops 0.6 1.05 1.30 V

Oscillator

Base Operating Frequency NCV5171, FB = 1 V 230 280 310 kHz

Base Operating Frequency NCV5173, FB = 1 V 460 560 620 kHz

Reduced Operating Frequency NCV5171, FB = 0 V 30 52 120 kHz

Reduced Operating Frequency NCV5173, FB = 0 V 60 104 160 kHz

Maximum Duty Cycle NCV5171 90 94 − %

Maximum Duty Cycle NCV5173 82 90 − %

FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V Sync/ Shutdown

Sync Range NCV5171 320 − 500 kHz

Sync Range NCV5173 640 − 1000 kHz

Sync Pulse Transition Threshold Rise time = 20 ns 2.5 − − V

SS Bias Current SS = 0 V

SS = 3.0 V

−15

−

−3.0 3.0

− 8.0

mA

Shutdown Threshold − 0.40 0.85 1.20 V

Shutdown Delay 2.7 V ≤ V_CC≤12 V

12 V < V_CC≤30 V

12 12

80 36

350 200

ms Power Switch

Switch Saturation Voltage I_SWITCH = 1.5 A, (Note 2) I_SWITCH = 1.0 A, 0°C ≤T_J≤85°C I_SWITCH = 1.0 A, −40°C ≤T_J≤0°C I_SWITCH = 10 mA

−

0.8 0.55 0.75 0.09

1.4

−

− 0.45

V

Switch Current Limit 50% duty cycle, (Note 2) 80% duty cycle, (Note 2)

1.6 1.5

1.9 1.7

2.4 2.2

A

Minimum Pulse Width FB = 0 V, I_SW = 4.0 A, (Note 2) 200 250 300 ns

DI_CC/ DIV_SW 2.7 V ≤ V_CC≤12 V, 10 mA ≤I_SW≤1.0 A 12 V < V_CC≤30 V, 10 mA ≤I_SW≤1.0 A

2.7 V ≤ V_CC≤12 V, 10 mA ≤I_SW≤1.5 A, (Note 2) 12 V < V_CC≤30 V, 10 mA ≤I_SW≤1.5 A, (Note 2)

−

10

− 17

−

30 100

mA/A

Switch Leakage V_SW = 40 V, V_CC = 0V − 2.0 100 mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

()

(4)

ELECTRICAL CHARACTERISTICS (2.7 V< V_CC < 30 V; −40°C < T_J < 125°C unless otherwise stated)(continued)

Characteristic Test Conditions Min Typ Max Unit

General

Operating Current I_SW = 0 − 5.5 8.0 mA

Shutdown Mode Current V_C < 0.8 V, SS = 0 V, 2.7 V ≤ V_CC≤ 12 V V_C < 0.8 V, SS = 0 V, 12 V ≤ V_CC≤ 30 V

−

12

−

60 100

mA Minimum Operation Input Voltage V_SW switching, maximum I_{SW =}10 mA − 2.45 2.70 V

Thermal Shutdown (Note 2) 150 180 210 °C

Thermal Hysteresis (Note 2) − 25 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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2. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION Package

Pin #

Pin

Symbol Function

1 V_C Loop compensation pin. The V_Cpin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1.

2 FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency.

3 Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running.

4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation.

5 V_CC Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to AGND.

6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate.

7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential.

8 V_SW High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.

(5)

PGND V_SW

+ −

+

−

V_CC

SS

FB

AGND

Positive Error Amp

PWM Compar- ator

Ramp Summer Slope

Compensation Thermal

Shutdown 2.0 V

Regulator Delay

Timer

Sync Shutdown

Oscillator

Frequency Shift 5:1

S PWMLatch R

Q Driver Switch

63 mW

0.4 V Detector

1.276 V

V_C

×5

Figure 2. Block Diagram

(6)

TYPICAL PERFORMANCE CHARACTERISTICS

0

Temperature (°C)

Figure 3. I_CC (No Switching) vs. Temperature

Current (mA)

7.2 7.0 6.8 6.6 6.4 6.2 6.0 5.8

V_CC = 30 V

5.6 50 100

V_CC = 12 V

V_CC = 2.7 V

0

Temperature (°C)

Figure 4. DI_CC/ DIV_SW vs. Temperature

(mA/A)

70 60 50 40 30 20 10

50 100

V_CC = 30 V

V_CC = 12 V V_CC = 2.7 V I_SW = 1.5 A

0

I_SW (mA) Figure 5. V_CE(SAT) vs. I_SW VCE(SAT) (mV)

1200 1000 800 600 400 200

0 500 1000

−40 °C 85 °C

25 °C

Temperature (°C)

Figure 6. Minimum Input Voltage vs. Temperature VIN (V)

1.5 1.6 1.7 1.8 1.9

0 50 100

Temperature (°C)

Figure 7. Switching Frequency vs. Temperature (NCV5171)

fOSC (kHz)

255 260 265 270 275

0 50 100

280 285

0

V_FB (mV) fOSC (% of Typical)

100 75 50 25

350 V_CC = (12 V)

380 400 420 450

85°C 25°C

−40°C

Figure 8. Switching Frequency vs. Temperature (NCV5173)

Figure 9. Switching Frequency vs. V_FB

Temperature (°C) fOSC (kHz)

540 545 550 555 560

0 50 100

565 570

535 530 525 520

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TYPICAL PERFORMANCE CHARACTERISTICS

Temperature (°C)

Voltage (V)

1.268 1.270 1.272 1.274 1.276

0 50 100

1.278 1.280

V_CC = 12 V

V_CC = 2.7 V

V_CC = 30 V

Temperature (°C) IFB (mA)

0.08 0.10 0.12 0.14 0.16

0 50 100

0.18 0.20

Figure 10. Reference Voltage vs. Temperature Figure 11. I_FB vs. Temperature

Temperature (°C)

Current (A)

2.20 2.30 2.40 2.50

0 50 100

2.60

V_CC = 12 V

V_CC = 30 V

V_CC = 2.7 V

Temperature (°C) Duty Cycle (%)95

96 97 98

0 50 100

99

V_CC = 30 V

V_CC = 2.7 V

94 93

V_CC = 12 V

Figure 12. Current Limit vs. Temperature Figure 13. Maximum Duty Cycle vs. Temperature

Temperature (°C)

Voltage (V)

0.5 0.6 0.7 0.8 0.9

0 50

1.0 1.1

0.4 Temperature (°C)

Voltage (V)

0.7 0.9 1.1 1.3

0 50 100

1.5 1.7

V_C High Clamp Voltage

V_C Threshold

Figure 14. V_C Threshold and High Clamp Voltage vs. Temperature

Figure 15. Shutdown Threshold vs. Temperature

(8)

TYPICAL PERFORMANCE CHARACTERISTICS

Temperature (°C)

Delay (ms)

80 100 120 140

0 50 100

160

V_CC = 12 V V_CC = 30 V V_CC = 2.7 V

60 40

V_SS (V) ISS (mA)

10 20 30 40

1 5 7

−40°C

0

−10

85°C 25°C

3 9

Figure 16. Shutdown Delay vs. Temperature Figure 17. I_SS vs. V_SS

V_IN (V) ICC (mA)

20 30 40

10

−40°C

10 0

85°C 25°C

Temperature (°C) gm (mmho)

450 500

0 50 100

550 600

Figure 18. I_CC vs. V_INDuring Shutdown Figure 19. Error Amplifier Transconductance vs. Temperature

V_REF−V_FB (mV) IOUT (mA)

20 60 100

0

−20

−60 −255 −175 −125 −75 −25 25

Temperature (°C)

Current (mA)

2.6

0 50 100

2.5 2.4 2.3 2.2 2.1 2.0

Figure 20. Error Amplifier I_OUT vs. V_FB Figure 21. Switch Leakage vs. Temperature

(9)

アプリケーション情報動作原理電流モード制御

+

−

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CO R_LOAD V_SW

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D1 V_CC

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L

63 mW

Figure 22. Current Mode Control Scheme

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IRIPPLE+VCC(VOUT*VCC) (f)(L)(VOUT)

f = 280 kHz (NCV5171) )= 560 kHz (NCV5173) X.T.電流平Ï電流RO+

a電流Ð=電流*®

T.飽¯生°1!?R必要|}

))=式D路O+a電流許容

差RÂ!JT.¤選択4IRÑ 照4I)O+a電流*小w!iF

"#Ke小wy1}電流p#能#

gIy14!{点*|})棒)=樽RÒ

=形状K8高!磁界放射Ç/*|})

比較的安Æ小\MtTa12k l形状K8磁気a+閉°J!=B

EMI 防止I)

入力コンデンサの選択

Figure 29 R示4>}昇$D路T.*

"#,Vav部R1}) Figure 28 R示4>

}連続67"#電流波形Ó角形 gIyLa w=電流W)J!)H5 R?bJ"#Ke選択R課w条 Ô*減})連続導通67X. X.

T.O+a電流.PQ説明

()(= Figure 28 mGm4>}T.

(12)

V_CCripple

Figure 28. Boost Input Voltage and Current Ripple Waveforms

I_IN

I_L

+

−

Figure 29. Boost Circuit Effective Input Filter

V_CC C_IN

R_ESR

I_L I_IN

,-.D路状況*異1})"#電

流×連続gI1La 電流*"#K

eR流)(=*bJ,-.

o¸a[存>?@,VaO 4! 2 z条Ô*KeR求B) +R対(J安定(=電源電$維持R 20

m

F Dc ESR Ê電用Ke*必要 T.R?bJ生°ª«c減R V

_CC

4-7間+I¾_近y R 1.0

m

F -§.Ke挿"()

V_OUTripple

I_L

Figure 30 R示波形調Ø4p#電流O+a

* 2 z1N z)}Ke ESR 4p#

KeÊ放電m生°4*m})

昇$D路LZ *q,R14

I

_L

* p#KeR流瞬間的1D V = I

_IN×

ESR *

発生()S時R電流

I

_L

− I

_OUT

*KeÊ

電(p#電$徐ÙR昇wH)LZ

*qR14 I

_l

*-7RP;Mw I

_OUT

R?}p#Ke*放電w) I

_L

O+a*Ö小w!iF I

_L

v定¤4(J扱

4*I"#電流 I

_IN

R等(y1})

要約4p#電$X. X.O+a

À¢?R計算I)

VOUT(RIPPLE)+(IIN*IOUT)(1*D) (COUT)(f) ) IOUTD

(COUT)(f))IIN ESR

À¢?R式 V

_CC

V

_OUT

>?@ I

_OUT

u

用(J設計RÚ{1方法表現I)

VOUT(RIPPLE)+IOUT(VOUT*VCC) (COUT)(f)

1 (COUT)(f) )(IOUT)(VOUT)(ESR)

VCC

Ke RMS O+a電流次式決)}

)

IRIPPLE+

Ǹ

(IIN*IOUT)2(1*D))(IOUT)2(D)

+IOUT VOUT*VCC

Ǹ

VCC

式昇$D路RE

適用I)*,-

.D路Rz!JS様式導y4*I)

電流制限の低減

v部8+OÕPQ設計者*

電流A限¤4(J 1.5 A ¢D¤希望 4*|})]^_P;M V

_C

X4-7

間R接続(J.-+電$c減4*I)

結果的R部LZM- 電流電

流A限*k称¤mc減w)

V

_C

X電$次式評ÆI)

VC+ISWREAV

R

E

= 0.063 W部o§抵抗¤

A

V

= 5 V/V 電流 8+

R

_E

>?@ A

_V

o7ÛÜ (

設計者

) *j更I 1! 電流 1.5 A

未満RA限=B

Ru用IÝv方法?}c!電$ V

_C

X .-+4最g 電流)=

最gT.電流式RÞ"4望)(

!.-+電$*得)

(13)

Figure 31 R示4>}簡1Tq7.- +u用(J V

_C電$抵抗

R3 電$RTq 7電$降¢=¤R.-+4*

I)残念1* V

_IN

安定精度*×Ö1 iFv般的R?1簡1D路u用I) H5

Figure 31. Current Limiting using a Diode Clamp V_C

D1

V_CC

R1 V_IN

C2 C1 R2

R3

電流A限題R対Ì解決策抵抗u用(J 流電流]部測定

4k?1D路 Figure 32 R示()

− +

Figure 32. Current Limiting using a Current Sense Resistor

V_C

R_SENSE Q1

V_CC

R1 V_IN

C2 C1 R2

C3

Output Ground

PGND AGND

電流次¤RA限w)

ISWITCH(PEAK)+VBE(Q1)

RSENSE

V

BE(Q1)

= Q1 o§電$降¢ 0

標準

.65 V

改w=D路正常R&'wH安定電$×要D路±的1率観点

{Ú性/()残念1Þ

必要

設計者"#-74p#-7ß通 1!4R注意必要|}))=電流

抵抗 R

_SENSE

追4m1}gI

1電#損à*生°kRábJ:Ve

.a²()抵抗 R2 4Ke C3 *tL

,Va形成(Jª«除â()

(14)

低調波発振

c調波発振 (SHM) 電流67A御P :Ã見

題:Ve.a* 50% 超i FR×安定R1}) SHM 連続T.電

流*流 E発生

()×安定性KR4bJ有害 1y通常p#電$安定R影響ãä(

)H5 SHM R?bJKm放射 EM ª

«²(v定状況¢T.高C波

聴ª«放射能性*|})

SHM 容易R改I題T.電

流立å*} t+部æ t+補

ç補完w:Ve.a×安定性

*次 e.aRÍG防止(

) NCV5171/73 q時間±R

対(J標準

180 mA/

mgIw t+補* 追wJ!)

v部Õ qÄ7 t+補*

存(J!J

SHM 題414|})

題è簡1対é法 t+補g Iy(J望)(y1!発振防ê4k

Õ Figure 33 R示]部D路追(J

u用 t+補量gIy4*I )D路必要4w 2 3

点部

E|}蔵補D路Ræ追çw)

Figure 33. Technique for Increasing Slope Compensation

V_C

R1

C2 C1

R2

R3 V_SW

C3

V_SW

破線長方形%)=部o-8+

帯幅A限通常補D路抵抗 R2 >

?@ R3 V

_SW

Xm電$ëD路形成() 通常&' V

_SW

方形波 RÒJ!)*

KMÈtR?bJ異1})昇$M Èt>?@,-.MÈtR>_ V

_SW

計算=B式.PQæ V

_SW電$A限ç

R記載(J!) *q,4I V

_SW

電$Ke

C3 *Ê電w V

_C

X電$

方Rj() qR14 C3 R3

経由放電w

V

_C

X負 t+*生成w )負 t+R?bJ t+補

*実現w)

D路R?bJ追w t+補量

次式?R1})

DI

DT+VSW

ǒ

_R2)R3^R3

Ǔ ǒ

¹^*^e^R3C3fSW^*(1*D)

Ǔǒ

₍₁_*^fSW_D)REAV

Ǔ

D

I/

D

T =

追w t+補量

(A/s)

V

_SW

= M- *q,R14I ª7電$

(V)

f

_SW

= C波数標準 280 kHz (NCV5171) )= 560 kHz (NCV5173) D = :Ve.a

R

_E

= 0.063

W部o§抵抗¤

A

_V

= 5 V/V 電流 8+

t+補D路R対適1¤選択際 R設計者)ì{Ú性高!Ke

選択

(次R R2 >?@ R3 ¤選択(追w t

+補量 100 mA/

m

s R4>íB()

k後必要R応°J R2 ²減能性*|

})当然直接続 R2 4 R3 組EFGH V

_SW

m過³1電流引I込)1!?RÖ

RgIy必要*|}))=A御a+

安定性確実R改=BR追KÈ¸

MR?}形成w時定数次式?R選択必要*|})

R3C3t1*D fSW

最後R t+補追Rá!:V

e.a安定4過渡応答間RM7q,

関î*|4説明¾_Æ¤*|})o-

8+適1&'ï£]部D路 *®

t+補ðy追32過渡応答

遅y1})

ソフトスタート

]部D路追4 NCV5171/73

部,§O

RN,M M機能追I)N,M MD路 V

_C

X起&時R急速RR14 防止(T.電流急1 t+²

4防止()

(15)

Figure 34 R示D路必要4w部

数*最小

SS Xu用(JK¶起&

4IR!zN,M MD路*起&

I?R()

Figure 34. Soft Start V_C

R1

C2 C1 D1 D2

V_CC

C3 V_IN

SS SS

抵抗

R1 4Ke C1 >?@ C2 *補D路形成 ()q時R V

_C

X電$*昇(

始BPQM9Tq7

D2 通°JK e C3 Ê電( V

_C

X電$.-+(J V

_C

*標準 1.05 V V

_C

PQa7R達4

*開始w?R() (

温度j 詳細Rz!J-,Ñ照

)

VC+VF(D2))VC3

(=*bJ C3 V

_C

X電$A限4 D路起&遅y() C3 容量*gIy1 RzJN,M M時間長y1})｡

SS tiFTq7 D1 通°J C3 放

電w) P;MTU機能

u用(1!iF D1 ÉN7 V

_IN

R接続必

要*|})

接合部温度の計算

NCV5171/73 安±&'[証=BR設計者

q+消費電#計算(ñ期w接F

部温度求B必要*|})接F部温度*

180

°

C

±

30

°

C D4部熱[護D路R?bJ q,R1})=¾(k?1高温 0復&'4&'寿ò確実R縮)})

接F部温度計算×正確*簡1'業｡

最óR電#損à定量必要*|})

NCV5171/73 RÀ¢ 3 z1電#損à源*|}

)

発振r´Oô8?1部A御

D路 *q,4I少量電#必

要4()D路R起標準&'電流

I

_Q

*

5.5 mA |4*PMõ様.

PQmGm})&'電流対温度-,m 追T 得)-, IQ "#電$ V

_IN

>?@温度RgIy左öw 4示(J!)(=*bJ次式?R1}

)

PBIAS+VINIQ

qÄ7 NPN M- |

=B 7-電流考慮R"必要*

|})A御D路電流RJ電流* V

_IN

X m

引

I p w )

駆

&

電流

D

I

_CC

/

D

I

_SW

)= M- KT.

4(Jõ様R記載wJ!)述?R

設計者-,追T 見z_4

*I)k情÷u用(J設計者次式

?R計算I)

PDRIVER+VINISW ICC

DISW D

I

_SW

= 通過電流

D = :Ve.a)= q

時間ëF

I

_SW

>?@ D K+R?bJ異1}

)

昇$K ISW(AVG)^IL(AVG) D 1

Efficiency D^VOUT*VIN

VOUT

,-.K

ISW(AVG)^VOUTILOAD

VIN

1 Efficiency

1 D D^ VOUT

VOUT)^NS_NPVIN

飽¯電$ V

_(CE)SAT

q+電#

損

à R関

要

1源 4 ( J

最後

V

_(CE)SAT

部 NPN M- * 駆&電流 R?}飽¯領駆&w4IK. o§

電$ V

_(CE)SAT

R関¤æ 飽¯

電$ç4(Jõ様)=-,m得)

(=*bJ

PSAT^V(CE)SATISW D

最後Rq+F計電#損àÀ¢?R

1})

PD+PBIAS)PDRIVER)PSAT

(16)

熱ù配gIwÉPMR

qJA

)=接F部 C%熱抵抗4(J掲載wJ!) q

JA

表面近y空気温度>?@

q+消費電#*Gm4q+接 F部温度計算I)

TJ+TA)(PDqJA)

T

_J

= )= FET 接F部温度 (

°

C) T

_A

= C%温度 (

°

C)

P

_D

=

該当消費電#

(W)

qJA

=

接F部úC%熱抵抗

(

°

C/W) NCV5171/73 q

JA

= 165

°

C/W

設計者

T

_J

計算4 NCV5171/73 *8+OÕ

PQu用能m2m4!題解決I ) T

_J

*絶対最g許容接F部温度| 150

°

C

DiF NCV5171/73 k8+OÕPQR

適(J!)H5

T

_J

* 150

°

C R近!iF設計者接F部温度¢£

実現能1方法考慮必要*|})Ì KMÈt選択(J 電流小 wy4考)+表面R沿b=

空気流²´4

T

_A

¢能性考

)

電流レイアウトのガイドライン

2?1 電源正(y&'w HD路8UM非常R重要高速

電流4M T.

組EFGH4題引I起能性|

電$過渡生°)=B8UMR関 (JÀ¢7-R従必要|})

ûü

昇$D路Tq7p#Ke

>?@q+LZM- m

成a+gI1

AC

電流*循環() 関î|M >?@O7長wI

¾_短y(J>y必要|}),- .D路 AC g電流a+M- ý·R存() 1

次·a+"#

KeM- >?@q+L ZM- m成} 2

次·

M- 整流Tq7>?@p#K eÌa+形成()昇$D路i F4±yS°?R AC g電流WþØJ M >?@O7短y(J>y必要

ÿü |})

小電流nh-7電源-7m離

用(Jy¾w!

3ü

電$,V7.抵抗 I¾

_近yR配置(J敏感1,V7.配線短y(J>!Jy¾w!,V7.抵

抗小電流8¬t-7R接続(Jy

¾w!

(17)

NCV5171/73 3.3 V_IN

V_C(1 ) FB (2) 0.1 mF

V_CC(5)

AGND (6) PGND (7)

V_SW(8)

200 pF

MBRS120T3

22 mF 22 mH

Figure 35.

Additional Application Diagram,

3.3 V Input, 5.0 V/ 400 mA Output Boost Converter 10 mF

GND

5.0 k

3.6 k

GND 5.0 V_O

1.3 k

+ + +

NCV5171/73

+12 V

V_C(1 ) FB (2) V_CC(5)

AGND (6) PGND (7)

V_SW(8)

MBRS140T3

22 mF

47 mF

Figure 36. Additional Application Diagram, 2.7 to 13 V Input, +12 V/ 200 mA Output Flyback Converter 1.0 mF

GND

2.0 k

10.72 k

GND

1.28 k

47 mF

47 nF 4.7 nF

V_CC −12 V

T1

1:2 P6KE−15A

1N4148

MBRS140T3

NCV5171/73 V_C(1 )

FB (2) V_CC(5)

AGND (6) PGND (7)

V_SW(8) 2.2 mF

15 mH GND

300

GND 5.0 k

.01 mF 200 pF

V_IN

−5.0 V_OUT 1.1 k

22 mF Low ESR

(18)

NCV5171/73

+

V_C(1 )

FB (2) V_CC(5)

AGND (6) PGND (7)

V_SW(8) 22 mF

Figure 38. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter GND

12.76 k

GND

5.0 k .01 mF 200 pF

V_CC

22 mH

LowESR 22 mF

22 mH 22 mF 37.24 k

5.0 V

NCV5171/73

V_C FB

AGND PGND V_SW

Figure 39. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with Output Voltage Multiplier

GND

GND .01 m

V_CC

4.0 V

Test SS 1 2 3 4

8 7 6 5 C11

R1 R2

R3 C10

.1 m

C8 C9

C1 C2 C3

C4 C5 C6

C7 .1 m

.1 m .1 m .1 m

50 V

50 V 50 V 50 V

.1 m 50 V .1 m

50 V .1 m

50 V

D1 D1 D1 D1 D1 D1 D1

1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 1N4148 99.755 k/0.1 W, 1%

1.245 k/0.1 W, 1%

2.0 k .1 m

10 m

100 V_O

+

NCV5171/73

V_C FB

V_CC AGND PGND V_SW

GND GND

0.01 mF 200 pF

22 mF 15 mH

22 mF

1.28 k 5.0 k

SS Test 1 2 3

4 5

6 7 8

+5.0 V SS

C6 C1 R1

R2 R3

10.72 k

C5 22 mF C3 D2 D3

L1

D1

−12 V

+12 V C4

0.1 mF

(19)

PACKAGE DIMENSIONS

SOIC−8 NB CASE 751−07

ISSUE AK

SEATING PLANE 1

4 5 8

N

J

X 45_ K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

A

B S

H D

C

0.10 (0.004)

DIM A

MIN MAX MIN MAX

INCHES 4.80 5.00 0.189 0.197 MILLIMETERS

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020

G 1.27 BSC 0.050 BSC

H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050

M 0 8 0 8

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

−X−

−Y−

G

Y M

0.25 (0.010)M

−Z−

Y 0.25 (0.010)M Z ^S X ^S

M

_ _ _ _

1.52 0.060

7.0 0.275

0.6 0.024

1.270 0.050 4.0 0.155

ǒ

_inches^mm

Ǔ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

(20)

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NCV5171JP - 1.5 A 280 kHz/560 kHz 昇圧レギュレータ

昇圧レギュレータ

NCV5171/73 製高率 1.5 A

280 kHz/560 kHz

､ 2.7 30 V 広!"#電$範%&'() 設計柔軟性*高!+昇$,- .､順方/0転 SEPIC 123452電源構成&' () 電流6789:.;採用 (負荷4-<=安定>?@電流A限=

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1.5 A [証

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2.7 30 V

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• LT1372/1373 4XY換

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−40 ° C 125 ° C

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TYPICAL PERFORMANCE CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

NCV5171/73

PWM -+nh生成電流67A御

+p#4比較(電源 q時間A御 ()発振rs定C波数.t.4(Ju用(

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明確1OM*損1G4|}

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NCV5171/73 t+補 方式採用(発振r発生s定-+電

18% C波数精度[証?R調整 wJ!) Figure 22 R示4>}､発振rp#､

280 kHz (NCV5171) )= 560 kHz (NCV5173) C波

PWM KL p#R?bJLZ q,R1 })

SS X TTL Y換S期"#|} 発振r C波数最g 1.8 C波数S期4*I)

Figure 23 R示4>}?}高!C波数S期

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SS Xt.taR維持4 *P;MTUw電源電流*減少(

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R:Ve.a* 50% D状況c

NCV5171/73 t+補方式採用(発振r発生s定-+電

18% C波数精度[証?R調整 wJ!) Figure 22 R示4>}､発振rp#､

SS X TTL Y換S期"#|} 発振r C波数最g 1.8 C波数S期4*I)

=BR発振rp#*R1R正遷移 u用(JLZ qR(結果発

SS Xt.taR維持4 P;MTUw電源電流減少(

FB X* PQa7MO

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PWM KL 最小La 幅R?bJA限w)

q,時間R?bJ最小:V e.a*減少(]^_部4 自[

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部電流振幅生°J!LZ qR1b=4説明I)

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C波数補目的P :Ã安定性[証(

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À¢?Ro-8 +p#抵抗4 C1 求B4*I)

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