6.6 kW On Board EV Charger (SiC Model) Evaluation Board User's Manual SEC-6D6KW-OBC-SIC-GEVB

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Charger (SiC Model)

Evaluation Board User's Manual

SEC-6D6KW-OBC-SIC-GEVB

SPECIFICATION

Device Application Input Voltage Output Power Topology I/O Isolation

FAN9673Q NCV4390 NCV1077P065G NCP51705MNTXG NCV57000DWR2G NVHL020N090SC1 NVHL060N090SC1 NCV890100PDR2G NCV2003SN2T1G

…

On Board EV

Charger 90 − 264 Vac 6.6 kW 3CH Interleave PFC+ Full Bridge LLC

Yes

OTHER SPECIFICATION

Output 1 Output 2

Output Voltage 250 − 450 Vdc 12 Vdc

Ripple 5% (Meet QCT 895 2011) 5%

Max Current 16 A 0.6 A

Min Current 0 0

PFC (Yes/No) Yes

Typical Efficiency 94%

Inrush Limiting 48A

Operating Temp. Range −20 − 85°C

Cooling Method Force Air or Liquid cooling. Depend on the Heatsink

Signal Level Control On/Off, CC, CV, Bus Voltage

Dimension 254 x 198 x 70 mm + Heatsink

www.onsemi.com

EVAL BOARD USER’S MANUAL

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Figure 1. Evaluation Board

KEY FEATURES

Whole Solution

• 3CH Interleave PFC to get high efficiency and power density. Decrease the current ripple at mean time

• Full bridge LLC to boost efficiency by high bus voltage usage

• Hardware PFC and LLC control approach for easily designing and less malfunction.

• Full functional solution including input/output current/voltage sensing and CC/CV PWM control interface.

• Bus voltage adjustable to optima the efficiency according to the output voltage.

• Adopting SiC MOSFETs and Diodes to enhance the efficiency.

PFC Controller FAN9673

• Continuous Conduction Mode with Average Current Mode Control

• Three−Channel Interleave Operation

• Programmable Operation Frequency Range:

18 kHz~40 kHz or 55 kHz~75 kHz

• Programmable PFC Output Voltage

• Two Current−Limit Functions

• TriFault Detect t Protects Against Feedback Loop Failure

• SAG Protection

• Programmable Soft−Start

• Under−Voltage Lockout (UVLO)

• Differential Current Sensing

LLC Controller NCV4390 (AEC Qualified Version of FAN7688)

• Secondary Side PFM Controller for LLC Resonant Converter with Synchronous Rectifier Control

• Charge Current Control for Better Transient Response and Easy Feedback Loop Design

• Adaptive Synchronous Rectification Control with Dual Edge Tracking

• Closed Loop Soft−Start for Monotonic Rising Output

• Wide Operating Frequency (39 kHz~690 kHz)

• Green Functions to Improve Light−Load Efficiency

• Symmetric PWM Control at Light−Load to Limit the Switching Frequency while Reducing Switching Losses

• Protection Functions (with Auto−Restart)

♦

Over−Current Protection (OCP)

♦

Output Short Protection (OSP)

♦

NON Zero−Voltage Switching Prevention (NZS) by Compensation Cutback (Frequency Shift)

♦

Power Limit by Compensation Cutback (Frequency Shift)

♦

Overload Protection (OLP) with Programmable Shutdown Delay Time

• Over−Temperature Protection (OTP)

• Programmable Dead Times for Primary Side Switches and Secondary Side Synchronous Rectifiers

• VDD Under−Voltage Lockout (UVLO)

• Wide Operating Temperature Range −40°C to +125°C

• Automotive Qualification

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SCHEMATICS

1

AND CIRCUIT DESCRIPTION

The system diagram is on Figure 2. The key elements of the OBC are marked in the color blocks.

Figure 2. System Diagram of the 6.6 kW OBC VBus

15 Vdc

PWM signal for CC/CV

Control

Vin, Iin Monitor Io Monitor

PWM signal for Vbus Control 3Ch Interleave

PFC NVHL020N090SC1

FFSP3065A_F085

3Ch PFC Controller

& Drivers FAN9673Q NCP51705MNTXG

Auxiliary Power NCV1077P060G NCV890100PDR2G

Drivers NCV57000DWR2G

Full Bridge LLC

NVHL060N090SC1 Full Bridge Rectifier FFSP3065A_F085

Io Sensing NCV210RSQT2G

Current mode LLC Controller CC/CV Control NCV4390 NCV2003SN2T1G

Control and Interface add

on Board HV Output 250 − 450Vdc

16 A max.

Vo Monitor 15 Vdc

12 Vdc Iin Sensing

NCV210RS- QT2G AC in 90 − 265 V

32 A max.

Following the AC input is the PFC stage. The key elements of the PFC stage are the controller FAN9673 and the triple boost power devices. The triple boost power devices schematic is shown in figure 3. The PFC inductors L20, L30, L40 were used to connect L20 and L20C, L30 and L30C, L40 and L40C. Two rectifier bridges in parallel were used to connect AC1, AC2, REC+ and REC−.

The FAN9673 circuit is showed in figure 4. More details of the FAN9673 please refer the datasheet and the application notes of the device on the web site https://www.onsemi.com/PowerSolutions/product.do?id=

FAN9673.

The bus voltage is adjustable by the duty of the PWM signal BSPWM. This function allowed the system designer optimize the system efficiency according to the input and output condition. The adjusting range is: When duty is changed from 0% to 100%, the Vbus will be changed from 210.83 to 412.45 Vdc.

The ON/OFF of PFC is controlled by the PFCEN signal.

When PFC is OK, the PFC enabled the LLC stage by the

RDY signal. So we used the PFCEN and RDY signal to

realize the Power ON timing control.

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2 RDY

3

1 3 5 7 9 11 13 15 17 19 21 23

Figure 3. Schematic of the Main Board

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R34 12.4KF R20

1M

C92 103

C25

103/50V C39 222/50V

C35 103/50V

C22 104 C21

474 C29

102/50V

C27

471/50V R33

12.4KF R19

510R

R31 33K C20

473/50V R28 2MF

C41 222/50V

R21 1M

C36 471/50V R39

10K L22

1uH

R40 47K

R26 24K

OPFC3 25

OPFC2 26

OPFC1 27 28 VDD

FBPFC 29 30 VEA 31 SS

IAC

BIBO1 PVO2 Ilimit3 GC4 RI5 RLPK6 Ilimit27 LPK8

32 RDY 9

IEA1 10 IEA2 11 IEA3 12 CVM1 13 CVM2 14 CVM3 15

VIR

LS17

CS3−18

CS3+19CS2−20CS2+21CS1−22

CS1+23GND24

16

U20 FAN9673

R36 18K

R22 200K C23 471/50V

R30 75K

R23 36K R27

2MF

C37 106/25V

C24 224/50V R29

2MF

C30

101/50V RDY

+15V

R46 C40 470

102/50V

Vin

C43

102/50V

C46

102/50V C45

222/50V C47

222/50V C44

222/50V

C42

222/50V R45 470 R44 470 R43 470 R42 470 R41 470

R18 510R R17 510R

C31

102/50V R37 18K

C32

101/50V C33

102/50V 18KR38

C34 101/50V

C28 103/50V R35 8.2K R32

39K C26

471/50V R16

12.4KF R1512.4KF

C17 225/25V C16

101/50V

C18 103/50V PFC3 PFC2 PFC1

PFCEN

CS1+ CS1− CS2+ CS2− CS3+ CS3−

32

1 Q23

2N7002

PFCO’

Vin

R3 1M

R4 1M

Vin−Test RDY

PFCEN +15V

PFC3

PFC1 PFC2

CS2+

CS1−

CS2−

CS3−

CS3+

CS1+

+15V

Vin

1 2 3 4 5 6 7 8 9 10

11 12 13 14 15 16 17 18 19 20 CON1

PFC Control

BSPWM PFCO’

Vin−Test

R1 10K

R2 470R BSPWM

3 1

2 D1 BAV99

+15V

Figure 4. Schematic of the PFC Control Board

The connector CON1 connects the PFC stage to the main board. The table 1 shows the signals.

Table 1. SIGNALS OF THE CON1 ON THE PFC CONTROL BOARD

Pin No. Direction Description

1 PFC3 The channel 3 driver

2 +15V The Power Supply for the FAN9673 3 CS3+ The positive current signal of channel 3 4 CS3− The GND of the current signal of channel 3 5 Vin The rectified voltage signal from the AC input

6 −

7 Vin−Test The Voltage signal for testing the Vin 8 RDY The signal to enable the LLC

11 BSPWM The PWM Signal to control the Vbus Voltage from the analog control board 12 PFCEN The PFC Enable signal from the analog control board

13 PFCO’ The Vbus Voltage signal

14 CS2+ The positive current signal of channel 2 15 CS2− The GND of the current signal of channel 2 16 GND The GND of the PFC control board

18 +15V The Power Supply for the FAN9673 19 CS1− The GND of the current signal of channel 2 20 CS1+ The positive current signal of channel 2

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Another key element of the OBC is the DC/DC stage. It is marked in blue in figure 2. The schematic of the DCDC stage is shown in figure 5. We adopt the single full bridge LLC topology to get the high efficiency and reasonable cost.

It’s composed by U60 and Q60, Q62, Q70, Q72 etc. The NCV4390 (U60) is a current mode advanced LLC controller. It is a pin to pin compatible device of the FAN7688. If you cannot find the device on the website, you can refer the description of FAN7688. More details of the part please refer the datasheet and the application notes.

Because of the high output voltage (250 − 450 Vdc), the Synchronous Rectifier cannot help too much on the rectifier

conduction loss. So we omitted the SR function of the NCV4390.

NCV57000 is a high − current single channel IGBT driver with internal galvanic isolation. It’s used to driver the SiC MOS in the LLC Stage and the NCL30059 is used to provide the power supply for the High side drivers as shown in figure 6.

The transformer with integrated resonate inductor (please refer the datasheet of the transformer at below) and the resonate capacitor are glued on the aluminum box for better heat sink.

M B R540 MB R 0540

MB R 0540 M B R 0540

0540

D29 D31

220 M B R 0540 M B R 0540

M B R 0540

R 63 1K

R 98 100K C 90 100P/50V

R 73 200K

R 86 2.2K

R 81 10K

R 91 4.75K F

C 81 103/50V

C 83 102/50V R 72

51K

C 75 471/50V C 72

472/50V

C 76 473/50V

C 82 471/50V

C 84 225/25V R 77

68K

C 73 224/50V

R 71 5.1K

C 91 225/25V

R 85 10K

R 90 220

C 85 100P/50V R 70

18K

R 92 4.75K F

R 74 15K

R 79 200K

R 83 4.75K F

R 69

C 74 475/25V

R 96 33K

C 70 10P/50V

R 62 1K

R 84 10K

R 76 NC D76

B AS16H

R 78 12.4K F

C 80 104/50V

R 80 1165V BGN D 215PW MSV D D 313FM I NPR OUT 2 414FBPR OUT 1 512C OM PSR OUT 1 611SSSR OUT 2 710I C SSR 1D S 89C SR D TU60 10R

NC P4390

C 77 221/50V

R 75 10K C 63

474/25V

C 71 471/50V

+5V B

C S +5V B

+5V B DR 1

DR 2 R 131 470

R 145 470

C C PWM C V PWM L C C V C C

V FB

2 S 3

1 T 72F 4

E E 8 R 97 47R C 61

102/50V C S C 106

106/25V C 122 106/25V

DR 1 +5V

C 110 104/50V C 109 106/25V

−5V HV 1 HV 1

+15V HV 1

C 142 100P/50V

M B R

C 52 100P/50V

+15V HV 1 HV 1

DE SAT 1

DrH1

DrL 1 C L A MP 1

C 130 106/25V

+15V

C 155 106/25V

−5V

DR 2 +5V

C 136 104/50V C 135 106/25V

C 146 100P/50V D35

D34 C 116 100P/50V

+15V

DrL 2 DrH2

C L A MP 2

C 60 106/25V C 124 106/25V DR 2

+5V C 112 104/50V C 111 106/25V

HV 2

−5V HV 2 +15V HV 2

C 143 100P/50V D32 D33

0C 115 100P/50V

+15V HV 2 HV 2

DE SAT 3

DrH3

DrL 3 C L A MP 3

C 131 106/25V

+15V

C 162 106/25V

−5V DR 1

+5V C 139 104/50V C 138 106/25V

C 147 100P/50V D36 D37

C 119 100P/50V

+15V

DrH4

DrL 4 C L A MP 4 DE SAT 4

C V PWM C C PWM V FB L C C V C C

Iou−C S +15V

+5V

C L A MP 1

HV 1 DrH1 DrL 1

DrH2 DrL 2

DrH3 HV 2

DrH4 DrL 4

C L A MP 2 C L A MP 4

C L A MP 3 DE SAT 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18

19 20 21 22 23 24 25 26 27 28 29 30 16

31 32 33 34 35 36 C ON1

P_1* 36 DE SAT 1

DE SAT 3 1

32

Q90 2N7002

−

+ 3

2

1 4

5U80

NC V 2003SN2T1G R 82 4.75kf Iou−C S

1

32

Q80 2N7002

−5V

−5V +15V HV 2 +15V HV 2

−5V HV 2

+15V HV 1

−5V HV 1

HV 1

1 2 3 4

5 6 7 8 C ON4

P_1* 8 DE SAT 2

DE SAT 2

DrL 3

−5V +15V

D1 SZMMS Z15T1G

D2 SZMMS Z15T1G

1 2 3 4 6

7 8 9 5

10 11 12 C ON2

P_1* 12 V E E 2A

1

DE SAT 2

3 GND2 OUT H 4

V DD2 5

OUT L 6

C L A MP 7

V E E 2

8 GND1A 9

IN + 10 IN − 11 R DY 12 FLT 13 R ST 14 V DD1 15 GND1 16 U18

NC V 57000 V E E 2A 1

DE SAT 2

3 GND2 OUT H 4

V DD2 5

OUT L 6

C L A MP 7

V E E 2

8 GND1A 9

NC V 57000

V E E 2A 1

DE SAT 2

3 GND2 OUT H 4

V DD2 5

OUT L 6

C L A MP 7

V E E 2

8 GND1A 9

NC V 57000

V E E 2A 1

DE SAT 2

3 GND2 OUT H 4

V DD2 5

OUT L 6

C L A MP 7

V E E 2

8 GND1A 9

NC V 57000 R 4

2.2R

R 3 2.2R R 2 2.2R R 1

2.2R C 1 104/50V

C 2 104/50V

C 4 104/50V

C 3 104/50V

C 8 104/50V

C 7 104/50V C 6

104/50V

C 5 104/50V

Figure 5. Schematic of the LLC Control Board

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The table 2 shows the signals on the CON1 on the LLC

control board. The NCV4390 get power supply when both of the PFC

RDY and the LLC enable signal are active.

Table 2. SIGNALS OF THE CON1 ON THE LLC CONTROL BOARD

Pin No. Direction Description

1 CVPWM PWM signal for content voltage setting.

2 Iou−CS Current sensing for Iout limited control 3 VFB Output Voltage sensing for feedback control 4 CCPWM PWM signal for constant current setting 5 LCCVCC Power Supply for the LLC controller 6 +5V Input side power Supply for the NCV57000 7 S_GND Ground reference on the secondary side 8 −5V Power Supply for the NCV57000 on the low−side

9 +15V Output side positive power supply for the NCV57000 on the low side 10 P_GND Ground reference on the primary side

11 P_GND Ground reference on the primary side 12 HV2 High−side source of channel 2

13 DESAT4 Input of NCV57000 (U19) for detecting the desaturation 14 DrH4 Driver high output of NCV57000 (U19)

15 DrL4 Driver low output of NCV57000 (U19)

16 CLAMP4 Clamping output of NCV57000 (U19) for protecting MOS from parasitic turn−on

17 −−−−−

18 −−−−−

19 −−−−−

23 CLAMP3 Clamping output of NCV57000 (U17) for protecting MOS from parasitic turn−on 24 P_GND Ground reference on the primary side

25 −−−−−

29 CLAMP2 Clamping output of NCV57000 (U16) for protecting MOS from parasitic turn−on 30 HV1 High−side source of channel 1

31 −−−−−

32 −−−−−

36 CLAMP1 Clamping output of NCV57000 (U18) for protecting MOS from parasitic turn−on

We used NCL30059 to provide the power supply for the

high−side driver. Figure 6 show the schematic of NCL30059

circuit.

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1 2 3 4

5 6 7 8 CON2

P_1*8 1

2

3

5 6

4

Q1NVMFD5C680NL R8

22

R11

10K R10

22

R12 10K

6 4

3 2 1 T2

EP7 C6 473/50V

D4 BAT54S

D6 BAT54S

D5 MMSZ4V7T1G C7

106/25V

C9 106/25V

R43.3K R5

3.3K R6

3.3K 6

4

3 2 1 T1

EP7 C1 473/50V

D1 BAT54S

D3 BAT54S

D2 MMSZ4V7T1G C2

106/25V

C4 106/25V

R1

3.3K R2

3.3K R3

3.3K C3

106/25V

C8106/25V C5

105/25V +15V

−5VHV2 HV2 +15VHV2

−5VHV1 +15VHV1

HV1

−5V +15V HV2 +15VHV2

−5VHV2

+15VHV1

−5VHV1

HV1

−5V 1 +15V

2 3 4 6

7 8 9 5

10 11 12 CON1

P_1*12 1 VCC

2 Rt 3 BO

4 GND ML 5

HB 6 MU 7 Vboot 8

U1 NCL30059 C10

105/50V R7 100R

R9 18K

R14 2K R13 5.1K

C11473/50V

C12 473/50V

Figure 6. Schematic of the Power Supply for the LLC Control Board

We also need 2 pairs of +15 V and −5 V floating voltage

on the Vcc and Vee of the high side MOSFETs gate drive.

These voltages are powered by the circuits shown in Figure 6. In general, it is two channels, open loop, push−pull, series resonate DCDC converter. U1 generates the near 50% duty−cycle, alternate on/off, 133 kHz driving signals on pin 5 and pin 7. Q1 and T1 − T2 forms 2 channels parallel push−pull converter which powered by +15 V. The leakage inductance of the transformer T1 − T2 is around 15.2 H. Together with the capacitors C1, C6, C11, C12, the resonance frequency is same with the push−pull signal. Both

of the Q1 and D1, D3, D4, D6 operate on soft switching. The gain of the converter keep stable. +20V voltages output after the full bridge rectifiers. The Zener diode D2, D5 and R1 − R6 separate the +20 V to +15 V and −5 V.

The detail of the NCL30059 please refer the datasheet on the web site: https://www.onsemi.com/products/power−

management/led−drivers/ac−dc−led−drivers/ncl30059.

Except the main stages of PFC and DC/DC, we also need

an auxiliary power on the OBC to supply the Vcc/Vdd to the

controller and driver circuits. Figure 7 shows the schematic

of the auxiliary power of this reference design.

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Figure 7. Schematic of the Auxiliary Power

The main topology of the auxiliary power is the fly−back

which controlled by the AEC qualified Switching Regulator NCV1077P065G. The detail of the device please refer the datasheet on the web site: https://www.onsemi.com/produc ts/power−management/ac−dc−controllers−regulators/offlin e−regulators/ncv1076−77.

This OBC has 3 separate GNDs. They are primary GND, Secondary GND, and HV GND. These GNDs are isolating each other. The auxiliary power supplies 3 insolating outputs according to the 3 separate GNDs. The +15 V output powers the PFC controller, PFC MOSFETs driver, LLC MOSFETs driver and the Relay; the −5 V and +5 V output power the NCV57000;

The +12Vsec powers the circuits on the control board and the off−board devices such as cooling FANs; the +12VHV power the LLC controller. The controller of the auxiliary power feedback the output of the primary side +15 V to save the optical coupler. Then the outputs of the secondary side and HV side will not be regulate due to the cross−regulation phenomena. So we inserted 2 Buck mode DCDC to the transformer outputs and the Loads. They are achieved by

two pieces of NCV890100PDR2G. This device is a non−SR buck switching regulator with SO8−EP package. The switching frequency is up to 2 MHz. The performance cost ratio is high and easy for application.

In this design, we put the interface circuits on an add−on

board for the flexibility. The features of the full function

interface board could include the (1) Can communication

with the BMS system to report the information like: Input

voltage, Input current, Output voltage, Output current, Bus

voltage, Output miss−connection, Temperature of the key

components. (2) Can communication with the BMS to

receive the following command: Power−up, Output voltage,

Output current, Power off. (3) Output the CC, CV PWM

signals and the power−on and relay−on signals to the main

board. (4) Setting the Bus voltage according to the Vin, Vo

and LLC switching frequency to get the maximum system

efficiency. (5) Connect to Strata Developer Studio for

evaluate the solution easily. But, the full function interface

board is not ready so far. We use a simple manual control

board instead of the full function one. Figure 8 show the

schematic of the manual control interface board.

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1

1 3 5 7 9 11 13 15 17 19 21 23

Figure 8. Schematic of the Manual Control Interface Board

The SW1 powers ON/OFF the PFC and LLC stage in the

secondary side for safety. It is delivery to the primary and HV stage by U224 and U244. The Vcc of the U223 and U224 is powered by the REY signal, thus the power−up will be AND with the relay active. The REY signal is 3 second delayed by U200 from the 12 V LV active moment to guarantee the Bus Caps is full charged. The BSPWM, CC

and CV PWM signals are generated by the U220, U246 and

U247 and the peripherals components. The variable

resistors VBUS, CC and CV control the duty of the PWM

signals. The sensing signals like Vin, Iin, Vbus, Vo and Io

was connected to the test points for customer testing by the

voltage meter.

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MEGNATICS DESIGN DATA SHEET PFC Inductors (By Sunloard): 3 pcs. Fill in aluminum box. Monte to heat sink.

Figure 9.

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PFC Inductors: 3 pcs (By Magsonder). Fill in aluminum box. Monte to heat sink.

Figure 10.

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Auxiliary Transformer: T150.

Figure 11.

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Current Transformer: T72.

Figure 12.

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LLC Transformers: Fill in aluminum box. Monte to heat sink.

Figure 13.

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LLC Transformers: Fill in aluminum box. Monte to heat sink.

Figure 14.

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DCDC Transformers: T1, T2 of the Power Supply for the LLC Control Board.

Figure 15.

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