NCP1605, NCP1605A, NCP1605B Power Factor Controller, Enhanced, High Voltage and Efficient Standby Mode

(1)

NCP1605B

Power Factor Controller,

Enhanced, High Voltage and Efficient Standby Mode

The NCP1605 is a controller that exhibits near−unity power factor while operating in fixed frequency, Discontinuous Conduction Mode (DCM) or in Critical Conduction Mode (CRM).

Housed in a SOIC−16 package, the circuit incorporates all the features necessary for building robust and compact PFC stages, with a minimum of external components. In addition, it integrates the skip cycle capability to lower the standby losses to a minimum.

General Features

•

Near−Unity Power Factor

•

Fixed Frequency, Discontinuous Conduction Mode Operation

•

Critical Conduction Mode Achievable in Most Stressful Conditions

•

Lossless High Voltage Current Source for Startup

•

^{Soft Skip}t Cycle for Low Power Standby Mode

•

Switching Frequency up to 250 kHz

•

Synchronization Capability

•

Fast Line / Load Transient Compensation

•

Valley Turn On

•

High Drive Capability: −500 mA / +800 mA

•

Signal to Indicate that the PFC is Ready for Operation (“pfcOK” Pin)

•

^VCC range: from 10 V to 20 V

•

Follower Boost Operation

•

^{Two V}CC Turn−On Threshold Options:

15 V for NCP1605 & NCP1605B; 10.5 V for NCP1605A

•

These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Safety Features

•

Output Under and Overvoltage Protection

•

Brown−Out Detection

•

Soft−Start for Smooth Startup Operation

•

Overcurrent Limitation

•

Zero Current Detection Protecting the PFC stage from Inrush Currents

•

Thermal Shutdown

•

Latched Off Capability Typical Applications

•

PC Power Supplies

•

All Off Line Appliances Requiring Power Factor Correction

SOIC−16 D SUFFIX CASE 751B

Device Package Shipping^† ORDERING INFORMATION

MARKING DIAGRAMS

x = A or B

A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package 1

NCP1605G AWLYWW

1 2 3 4 5 6 7 8

16 15 14

12 11 10 9 (Top View) CS_in

STBY BO V_control FB CS_out/ZCD Ct OSC/SYNC

HV NC

pfcOK/REF5V V_CC

GND OVP/UVP

DRV 13 STDWN PIN CONNECTIONS

†For information on tape and reel specifications, including part orientation and tape sizes, please

1

NCP1605DR2G SOIC−16 (Pb−Free)

2500/Tape & Reel 16

NCP1605ADR2G SOIC−16 (Pb−Free)

2500/Tape & Reel NCP1605xG

AWLYWW 1

16

NCP1605BDR2G SOIC−16 (Pb−Free)

2500/Tape & Reel www.onsemi.com

(2)

EMI Filter Ac line

LOAD L1

D1

Rcs

M1 Cbo

1 2 3 4 13

16 14 15

5 6 7 8 9

12 10 11 Ct

pfcOK STBY control

FB

OVP

Rzcd

Rdrv C_in

R_ocp R_bo2

R_bo1

+ V_out +

V_CC

CV_CC

I_coil V_in

C_bulk V_CC

V_out

C_osc

R_ovp1

R_ovp2 R_out1

CV_ref CV_ctrl

R_out2

I_coil

Figure 1.

MAXIMUM RATINGS

Pin Rating Symbol Value Unit

11 Power Supply Input V_CC −0.3, +20 V

11 Maximum Transient Voltage (Note 1) V_CC −0.3, +25 V

1, 2, 4, 5, 6, 7, 8, 13 and 14

Input Voltage V_I −0.3, +9 V

6 Maximum Current I_CSOUT/ZCD −3, 10 mA

3 V_CONTROL Pin V_CONTROL −0.3, V_CONTROLMAX

(Note 2)

V

16 High Voltage Pin V_HV −0.3, 600 V V

Power Dissipation and Thermal Characteristics:

Maximum Power Dissipation @ T_A = 70°C Thermal Resistance Junction−to−Air

P_D R_q_JA

550 145

°mWC/W

Operating Junction Temperature Range T_J −55 to +125 °C

Maximum Junction Temperature T_Jmax 150 °C

Storage Temperature Range T_Smax −65 to +150 °C

Lead Temperature (Soldering, 10 s) T_Lmax 300 °C

ESD Capability, HBM Model (all pins except HV) (Note 3) HBM 2000 V

ESD Capability, MM Model (all pins except HV) (Note 3) MM 200 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability must be observed as well.

2. “V_CONTROLMAX” is the pin clamp voltage.

3. This device series contains ESD protection rated using the following tests:

Human Body Model (HBM) 2000V per JEDEC Standard JESD22, Method A114E.

Machine Model (MM) 200V per JEDEC Standard JESD22, Method A115A.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

(3)

TYPICAL ELECTRICAL CHARACTERISTICS

(Conditions: V_CC = 16 V, V_HV = 50 V, V_Pin2 = 2 V, V_Pin13 = 0 V, T_J from 0°C to +125°C, unless otherwise specified;

For NCP1605DR2G: for typical values T_J = 25°C, for min/max values T_J = −55°C to +125°C, unless otherwise specified) (Note 7)

Symbol Rating Min Typ Max Unit

Gate Drive Section

T_rise Output Voltage Rise Time @ C_L = 1 nF, from 1 V to 10 V − 40 − ns

T_fall Output Voltage Fall Time @ C_L = 1 nF, from 10 V to 1 V − 20 − ns

R_OH Source Resistance @ I_Pin10= 100 mA − 15 25 W

I_source Source Current capability (@ V_Pin10 = 0 V) − 500 − mA

R_OL Sink Resistance @ I_Pin10= 100 mA − 7 15 W

I_sink Sink Current Capability (@ V_Pin10 = 10 V) − 800 − mA

Regulation Block

V_REF Voltage Reference NCP1605/A

NCP1605B

2.425 2.430

2.500 2.500

2.575 2.550

V

I_EA Error Amplifier Current Capability − ±20 − mA

G_EA Error Amplifier Gain 100 200 300 mS

IB_Pin4 Pin 4 Bias Current @ V_Pin4 = V_REF −500 − 500 nA

V_CONTROL

− V_CONTROLMAX

− V_CONTROLMIN

− D V_CONTROLl

Pin 2 Voltage:

− @ V_Pin4 = 2 V

− @ V_Pin4 = 3 V

−

− 2.7

3.6 0.6 3.0

−

− 3.3

V

V_OUTL / V_REF Ratio (V_OUT Low Detect Threshold / V_REF) (Note 6) 95.0 95.5 96.0 % H_OUTL / V_REF Ratio (V_OUT Low Detect Hysteresis / V_REF) (Note 6) − − 0.5 % I_BOOST Pin 2 Source Current when (V_OUT Low Detect) is activated 190 240 290 mA Shutdown Block

I_LEAKAGE Current Sourced by Pin 13 @ V_Pin14 = 2.3 V −500 − 500 nA

V_STDWN Pin 13 Threshold for Shutdown 2.375 2.500 2.625 V

Over and Under Voltage Protections

V_OVP Overvoltage Protection Threshold 2.425 2.500 2.575 V

V_OVP / V_REF Ratio (V_OVP / V_REF) (Note 5) 99.5 100.0 100.5 %

V_UVP / V_REF Ratio UVP threshold over V_REF 8 12 16 %

IB_Pin14 Pin 13 Bias Current:

@ V_Pin14 = V_OVP

@ V_Pin14 = V_UVP

−500

−

500 500

nA

Ramp Control

I_RAMP− 1.00 V

Pin 7 Source Current: @ V_Pin4 = 1.00 V

T_J = 0°C to +125°C NCP1605, T_J = −40°C to +125°C NCP1605, T_J = −55°C to +125°C

54 52 51

60

−

69 69 69

mA

I_RAMP − 1.75 V I_RAMP − 2.50 V

Pin 7 Source Current:

@ V_Pin4 = 1.75 V

@ V_Pin4 = 2.50 V 156 313

182 370

214 428

mA

Vcl_ff Pin 7 Clamp Voltage @ V_Pin4 = V_Pin2 = 2 V and V_Pin6 = 0 V − 5 − V V_CLCRM Pin 7 Clamp Voltage @ V_Pin4 = 0 V, V_Pin2 = 2 V and V_Pin6 = 1 V 0.9 1 1.1 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Not tested; guaranteed by characterization 6. Not tested; guaranteed by design

7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

(4)

R_CT Ratio (Pin 7 Clamp Voltage / (Pin 7 Charge Current) (V_CLCRM / I_RAMP) @ V_Pin6 = 0 V and

− V_Pin4 = 1.00 V

− V_Pin4 = 1.75 V

− V_Pin4 = 2.50 V

−

16.7 5.4 2.7

−

kW

T_ONMIN Delay (V_Pin7 > 5 V) to (DRV low) − 90 200 ns

C_INT Average Pin 7 Internal Capacitance (V_Pin7 varying from 0 and 1 V) Guaranteed by design

− 15 25 pF

V_INIT Maximum Pin 7 Voltage Allowing the Setting of the PWM Latch − 50 90 mV

I_{RAMP_SINK} Pin 7 Sink Current (Drive low) @ V_Pin7 = 1 V − 10 − mA

Current Sense Block

Off100 Current Sense Pin Voltage, NCP1605/A

100 mA being drawn from Pin 5 NCP1605B

−20

−5.0

6.0 6.0

20 15

mV

Off10 Current Sense Pin Voltage, 10 mA being drawn from Pin 5 3.0 8.0 13 mV

I_MAX Overcurrent Protection Threshold 230 250 265 mA

T_OCP (Ipin5 > 250 mA) to (DRV low) Propagation Delay (Note 5) − 100 200 ns

K_CS10 Ratio (I_Pin6/I_Pin5) @ I_Pin5 = 10 mA 99 108 117 %

K_CS200 Ratio (I_Pin6/I_Pin5) @ I_Pin5 = 200 mA 98 101 103 %

V_ZCD Pin 6 Comparator Threshold 50 100 200 mV

T_ZCD Delay from (V_Pin6 < V_ZCD) to (DRV high) − 120 240 ns

Standby Input

V_STBY Standby Mode Threshold (V_Pin1 falling) 280 310 340 mV

H_STBY Hysteresis for Standby Mode Detection 25 30 50 mV

V_SKIPOUT_/V_OUTL Ratio (Pin 4 Voltage to terminate a SKIP period) over the (V_OUTLow Detect Threshold) (Note 6)

99 100 101 %

Oscillator / Synchronization Block

I_charge Oscillator Charge Current

90 89 88

100

−

110 110 110

mA

I_disch Oscillator Discharge Current

90 89 88

100

−

110 110 110

mA

V_{sync_H} Comparator Upper Threshold − 3.0 − V

V_{sync_L} Comparator Lower Threshold − 2.0 − V

Swing Comparator Swing (V_{sync_H}− V_{sync_L}) 0.9 1.0 1.1 V

T_{sync_min} Minimum Synchronization Pulse Width for Detection − − 500 ns

pfcOK / REF5V

V_pfcOKL Pin 12 Voltage @ V_Pin13 = 5 V, 250 mA being sunk by Pin 12 − 60 120 mV Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

(5)

TYPICAL ELECTRICAL CHARACTERISTICS

V_pfcOKH (Pin 12 Voltage @ V_Pin13 = 0 V and NCP1605/A V_Pin3 = 5 V, with a 250 mA sourced by Pin 12) NCP1605B (Pin 12 Voltage @ V_Pin13 = 0 V and NCP1605/A V_Pin3 = 5 V, with a 5 mA sourced by Pin 12) NCP1605B

4.7 4.75

4.5 4.5

5.0 5.0 5.0 4.72

5.3 5.3 5.3 5.0

V

Icap_ref Current Capability 5 .0 10 − mA

Brown−Out Detection Block

V_BOH Brown−Out Comparator Threshold (V_Pin2 rising) NCP1605/A NCP1605B

0.9 0.93

1.0 1.0

1.1 1.07

V V_BOL Brown−Out Comparator Threshold (V_Pin2 falling) NCP1605/A

NCP1605B 0.45 0.465

0.50 0.50

0.55 0.535

V

IB_BO Pin 2 Bias Current @ V_Pin2 = 0.5 V and 1 V −500 − 500 nA

Thermal Shutdown

T_LIMIT Thermal Shutdown Threshold − 155 − °C

H_TEMP Thermal Shutdown Hysteresis − 15 − °C

V_CC UNDERVOLTAGE Lockout Section

V_CCON Turn on Threshold Level, V_CC Raising Up NCP1605 NCP1605A NCP1605B

14 9.5 14.2

15 10.5

15

16 11.5 15.55

V

V_CCOFF Minimum Operating Voltage after Turn−on NCP1605/A NCP1605B

8.0 8.6

9.0 9.0

10 9.35

V

H_UVLO Difference (V_CCON − V_CCOFF) NCP1605/B

NCP1605A 5.0 1.2

6.0 1.5

−

V V_CCSTUP V_CC Threshold below which the Startup Current Source Turns on 5.5 7.0 8.0 V

H_LATCHOFF Difference (V_CCOFF − V_CCSTUP) 0.6 2.0 − V

V_CCRST V_CC Level at which the Logic Resets 2.0 4.0 5.0 V

V_CCINHIBIT Threshold which IC2 stops working & switches to IC1, I_C2 = 1 mA NCP1605, T_J = 0°C to +125°C NCP1605, T_J = −40°C to +125°C NCP1605, T_J = −55°C to +125°C NCP1605A NCP1605B

− 0.3 0.3

− 0.3

2.1

−

− 2.1 1.8

− 2.5 2.55

− 2.2

V

Internal STARTUP Current Source

IC1_hv (High−Voltage Current Source NCP1605/A

sunk by Pin 16, V_CC = 13.5 V) NCP1605B 5.0 7.0

12 12

20 17

mA IC1_Vcc (Startup Charge Current flowing NCP1605/A

out of the V_CC Pin, V_CC = 13.5 V) NCP1605B 5.0 6.5

12 12

20 16.5

mA IC2 High−Voltage Current Source, V_CC = 0 V NCP1605/A

NCP1605B

− 0.375

0.5 0.5

1.0 0.87

mA Device Consumption

I_{cc_op1} I_{cc_op2} I_{cc_OFF} Icc_latchOFF

Power Supply Current:

Operating (@ V_CC = 16 V, no load, no switching) Operating (@ V_CC = 16 V, no load, switching) Off Mode (@ V_CC = 16 V, Pin 2 grounded)

Latched−Off Mode (@ V_CC = 13.5 V and V_Pin13 = 5 V)

− 2.0 310 310

2.5 3.5 570 550

5.0 7.0 780 750

mA mA mA mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

(6)

Pin

Number Name Function

1 STBY An external signal (typically, a portion of the feedback signal of the downstream converter or a filtered portion of the SMPS drive pulses) should be applied to Pin 1. When the Pin 3 voltage goes below 300 mV, the circuit enters a burst mode operation where the bulk voltage varies between the regulation voltage and 95.5% of this level.

2 Brown−Out /

Inhibition

Apply a portion of the averaged input voltage to detect brown−out conditions. If V_Pin2 is lower than 0.5 V, the circuit stops pulsing until V_Pin2 exceeds 1 V (0.5 V hysteresis).

Ground Pin 6 to disable the part.

3 V_CONTROL /

Soft−Start

The error amplifier output is available on this Pin. The capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios.

Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft−start).

4 Feedback This pin receives a portion of the pre−converter output voltage. This information is used for the regulation and the “output low” detection (V_OUTL) that drastically speed up the loop response when the output voltage drops below 95.5% of the wished level.

5 Current Sense Input

This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the maximum coil current and detect the core reset (coil demagnetization).

6 Current Sense Output

This pin sources the Pin 5 current. Place a resistor between Pin 6 and ground to build the voltage proportional to the coil current and detect the core reset. The impedance between Pin 6 and ground should not exceed 3 times that of the Pin 5 to ground. You can further apply the voltage from an auxiliary winding to improve the valley detection of the MOSFET drain source voltage.

7 Ct

(Ramp)

The circuit controls the power switch on−time by comparing the Pin 7 ramp to an internal voltage (“V_ton”) derived from the regulation block and the sensed “dcycle” (relative duration of the current cycle over the corresponding switching period).

Pin 7 sources a current proportional to the squared output voltage to allow the Follower Boost operation (optional) where the PFC output voltage stabilizes at a level that varies linearly versus the ac line amplitude. This technique reduces the difference between the output and input voltages, to optimize the boost efficiency and minimize the size and cost of the PFC stage

8 Oscillator / synchronization

Connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. If the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. Hence, the PFC stage can operate in CRM in the most stressful conditions.

9 GND Connect this pin to the pre−converter ground.

10 Drive The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs.

11 V_CC This pin is the positive supply of the IC. The circuit starts to operate when V_CC exceeds 15 V (10.5 V for NCP1605A) and turns off when V_CC goes below 9 V (typical values). After startup, the operating range is 10 V up to 20 V.

12 PfcOK / REF5V The Pin 12 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and that hence, it can start operation.

13 STDWN Apply a voltage higher than 2.5 V on Pin 13 to permanently shutdown the circuit. This pin can be used to monitor the voltage across a thermistor in order to protect the application from an excessive heating and/or to detect an overvoltage condition.

To resume operation, it is necessary to decrease the circuit V_CC below V_CCRST (4 V typically) by for instance, unplugging the PFC stage and replugging it after V_CC is discharged.

14 OVP / UVP The circuit turns off when V_Pin14 goes below 300 mV (UVP) and disables the drive as long as the pin voltage exceeds 2.5 V (OVP).

15 NC Creepage distance.

16 HV Connect Pin 16 to the bulk capacitor. The internal startup current source placed between Pin 16 and the V_CC terminal, charges the V_CC capacitor at startup.

(7)

2.41 2.43 2.45 2.47 2.49 2.51 2.53 2.55 2.57 2.59

VREF, (V)

T_J, JUNCTION TEMPERATURE (°C)

−40 −15 10 35 60 85 110

Figure 2. Reference Voltage vs. Temperature

235 240 245 250 255 260 265

−40 −15 10 35 60 85 110

IREF, (mA)

T_J, JUNCTION TEMPERATURE (°C) Figure 3. Reference Current vs. Temperature

2.40 2.44 2.48 2.52 2.56 2.60

Figure 4. Overvoltage Threshold vs. Temperature VOVP, (V)

−40 −15 10 35 60 85 110

97 98 99 100 101 102 103

Figure 5. Ratio Overvoltage Threshold Overvoltage Reference vs. Temperature VOVP/VREF, (%)

−40 −15 10 35 60 85 110

2.36 2.41 2.46 2.51 2.56 2.61

VSTDWN, (V)

−40 −15 10 35 60 85 110

Figure 6. Shutdown Threshold vs. Temperature

(8)

0 0.1 0.2 0.3 0.4 0.5

VUVP, (V)

−40 −15 10 35 60 85 110

Figure 7. Undervoltage Protection Threshold vs.

Temperature

7 9.04 11.08 13.12 15.16

VUVPVREF, (%)

−40 −15 10 35 60 85 110

Figure 8. Ratio (V_UVP/V_REF) vs. Temperature

13.9 14.2 14.5 14.8 15.1 15.4

VCCON, (V)

−40 −15 10 35 60 85 110

Figure 9. V_CC Turn on Threshold vs.

Temperature (V_CC Raising Up) − NCP1605/B

7.9 8.2 8.5 8.8 9.1 9.4 9.7

VCCOFF, (V)

−40 −15 10 35 60 85 110

Figure 10. V_CC Minimum Operating Voltage After Turn On − NCP1605/B

5.2 5.5 5.8 6.1 6.4 6.7

HUVLO, (V)

−40 −15 10 35 60 85 110

Figure 11. Difference (VCC_ON − VCC_OFF) vs.

Temperature − NCP1605/B

4.8 5.3 5.8 6.3 6.8 7.3 7.8 8.3 8.8

VCCSTUP, (V)

−40 −15 10 35 60 85 110

Figure 12. V_CC Threshold Below which the Startup Current Source Turns on vs. Temperature

(9)

0.5 1 1.5 2 2.5 3 3.5 4

Figure 13. Difference (V_CCOFF−V_CCSTUP) vs.

Temperature HLATCHOFF, (V)

−40 −15 10 35 60 85 110

0 1 2 3 4 5 6

VCCRST, (V)

−40 −15 10 35 60 85 110

Figure 14. V_CC Level Below Which the Logic Resets vs. Temperature

4 6 8 10 12 14 16 18 20

IC1_HV, (mA)

−40 −15 10 35 60 85 110

Figure 15. High−Voltage Current Source (Sunk by Pin 16) vs. Temperature (@ V_CC = 13.5 V)

4 6 8 10 12 14 16 18 20

Figure 16. Startup Charge Current Flowing Out of the V_CC Pin vs. Temperature (@ V_CC = 13.5 V)

−40 −15 10 35 60 85 110

IC1_VOFF, (mA)

0 0.3 0.6 0.9 1.2

Figure 17. High−Voltage Current Source vs.

Temperature (@ V_CC = 0 V)

IC2, (mA)

−40 −15 10 35 60 85 110

0 10 20 30 40 50 60 70 80 90

HV_LEAKAGE, (mA)

−40 −15 10 35 60 85 110

Figure 18. Pin 16 Leakage Current vs.

Temperature (@ V_PIN16 = 500 V and V_CC = 16 V)

(10)

12 14 16 18 20 22

IEA_SOURCE, (mA)

−40 −15 10 35 60 85 110

Figure 19. Source Current Capability of the Error Amplifier vs. Temperature

−24

−22

−20

−18

−16

−14

IEA_SINK, (mA)

−40 −15 10 35 60 85 110

Figure 20. Sink Current Capability of the Error Amplifier vs. Temperature

60 100 140 180 220 260 300

GEA, (mS)

−40 −15 10 35 60 85 110

Figure 21. Error Amplifier Gain vs. Temperature

−150

−100

−50 0 50 100 150

IBPIN4, (nA)

−40 −15 10 35 60 85 110

Figure 22. Feedback Pin Bias Current vs.

Temperature (@ V_PIN4 = V_REF)

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

Figure 23. V_CONTROL Maximum Voltage vs.

Temperature VCONTROLMAX, (V)

−40 −15 10 35 60 85 110

2.6 2.7 2.8 2.9 3 3.1 3.2 3.3

D(VCONTROL), (V)

−40 −15 10 35 60 85 110

Figure 24. V_CONTROL Maximum Swing (DV_CONTROL) vs. Temperature

(11)

95.1 95.2 95.3 95.4 95.5 95.6 95.7 95.8 95.9

VOUTL/VREF, (%)

−40 −15 10 35 60 85 110

Figure 25. Ratio (V_OUT Low Detect Threshold) / V_REF vs. Temperature

190 200 210 220 230 240 250 260 270

IBOOST, (mA)

−40 −15 10 35 60 85 110

Figure 26. Pin 3 Source Current when (V_OUT Low Detect Threshold) is Activated vs. Temperature

80 90 100 110

Figure 27. Oscillator Charge Current vs.

Temperature ICHARGE, (mA)

−40 −15 10 35 60 85 110

80 90 100 110

IDISCH, (mA)

−40 −15 10 35 60 85 110

Figure 28. Oscillator Discharge Current vs.

Temperature

0.91 0.93 0.95 0.97 0.99 1.01

SWING, (V)

−40 −15 10 35 60 85 110

Figure 29. Oscillator Swing vs. Temperature

0 25 50 75 100 125 150

−40 −15 10 35 60 85 110

pfcOK_L (mV)

Figure 30. pfcOK Pin Low Level Voltage vs.

Temperature 85

95 105

85 95 105

(12)

4.5 4.7 4.9 5.1 5.3

−40 −15 10 35 60 85 110

pfcOK_H, (V)

Figure 31. pfcOK Pin High Level Voltage vs.

Temperature (250 mA Load)

0 1 2 3 4

−40 −15 10 35 60 85 110

ICC_OP1, (mA)

Figure 32. Operating Consumption vs.

Temperature (V_CC = 16 V, No Load, No Switching)

1 2 3 4 5 6

−40 −15 10 35 60 85 110

ICC_OP2, (mA)

Figure 33. Operating Consumption vs.

Temperature (V_CC = 16 V, No Load, Switching)

300 400 500 600 700 800

−40 −15 10 35 60 85 110

ICCOFF, (mA)

Figure 34. Off Mode Consumption vs.

Temperature (V_CC = 16 V, Pin 2 Grounded)

300 400 500 600 700 800

−40 −15 10 35 60 85 110

ICCSTDOWN, (mA)

Figure 35. Shutdown Mode Consumption vs.

Temperature (V_CC = 16 V, Pin 2 GND)

(13)

0.9 0.95 1 1.05 1.1

−40 −15 10 35 60 85 110

VCBOH, (V)

Figure 36. Brown−Out Upper Threshold vs.

Temperature

0.4 0.45 0.5 0.55 0.6

−40 −15 10 35 60 85 110

VCBOL, (V)

Figure 37. Brown−Out Lower Threshold vs.

Temperature

−2 0 2 4 6 8 10 12 14

−40 −15 10 35 60 85 110

OFF100, (mV)

Figure 38. Current Sense Pin Voltage vs.

Temperature (100 mA Being Drawn from Pin 5)

2 4 6 8 10 12 14

−40 −15 10 35 60 85 110

OFF10, (mV)

Figure 39. Current Sense Pin Voltage vs.

Temperature (10 mA Being Drawn from Pin 5)

52 54 56 58 60 62 64 66 68

−40 −15 10 35 60 85 110

IRAMP_1.00 V, (mA)

Figure 40. Pin 7 Source Current

@ V_PIN4 = 1.0 V vs. Temperature

158 168 178 188 198 208

−40 −15 10 35 60 85 110

IRAMP_1.75 V, (mA)

Figure 41. Pin 7 Source Current

@ V_PIN4 = 1.75 V vs. Temperature 163

173 183 193 203

(14)

325 335 345 365 375 385 405

−40 −15 10 35 60 85 110

IRAMP_2.50 V, (mA)

Figure 42. Pin 7 Source Current @ V_PIN4 = 2.5 V vs. Temperature

3 4 5 6 7

Figure 43. Ratio Pin 7 Clamp Voltage / (Pin 7 Charge Current) that is (V_CLCRM / I_RAMP)

@ V_PIN6 = 0 V and V_PIN4 = 1.75 V T_J, JUNCTION TEMPERATURE (°C)

−40 −15 10 35 60 85 110

RCT (kW)

104 106 108 110 112

−40 −15 10 35 60 85 110

TZCD, (ns)

Figure 44. Ratio (I_PIN6 / I_PIN5) @ I_PIN5 = 10 mA vs.

Temperature

40 60 80 100 120 140 160 180 200

−40 −15 10 35 60 85 110

VZCD, (mV)

Figure 45. Pin 6 Comparator Threshold vs.

Temperature

40 60 80 100 120 140 160 180 200 220

−40 −15 10 35 60 85 110

Kcs10, (%)

Figure 46. Delay from (ZCD Pin Low) to (DRV High) vs. Temperature

260 280 300 320 340

VSKIPH, (V)

−40 −15 10 35 60 85 110

Figure 47. Skip Cycle Threshold (V_PIN1 Falling) vs. Temperature 270

290 310 330 355

395

(15)

0 20 40 60 80 100 120 140 160 180

tOMIN, (ns)

−40 −15 10 35 60 85 110

Figure 48. Minimum On−Time vs. Temperature

8 10 12 14 16 18 20 22 24 26

ROH, (W)

−40 −15 10 35 60 85 110

Figure 49. Gate Drive Source Resistance vs.

Temperature

2 4 6 8 10 12 14 16

ROL, (W)

−40 −15 10 35 60 85 110

Figure 50. Gate Drive Sink Resistance vs. Temperature