with Full Digital Circuit and Self-Calibration

(1)

Timing Measurement BOST Architecture with Full Digital Circuit and Self-Calibration

Using Characteristics Variation Positively for Fine Time Resolution

Congbing Li, Junshan Wang, Haruo Kobayashi Ryoji Shiota

Gunma University, Socionext Inc.

21

^st

IEEE International Mixed-Signal Testing Workshop Catalunya, Spain

July 5, 2016 9:00-9:30am

Conference Room: Goya

(2)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(3)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(4)

Introduction

“Fine time resolution” and “high linearity”

TDC is essential for jitter, timing BOST

・ High linearity TDC

→Self-calibration circuit

・ Fine time resolution TDC

→Stochastic architecture

(5)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(6)

Time to Digital Converter （ TDC ）

T Start

Stop

Start

Stop TDC D ^out

10 20 30 40 50

LSB [p s]

Higher resolution with CMOS scaling

● time interval → Measurement → Digital value

● Key component of

time-domain analog circuit

● Higher resolution can be

obtained with scaled CMOS

(7)

Time to Digital Converter （ TDC ）

Start

Stop

D0=1 D1=1 D2=1 D3=0 D4=0 Timing chart

T

Start

Stop

D Q D

Q D

Q

Encoder

D0 D1 D2

τ τ τ τ

Dout

Start

Stop

D Q

D Q D

D Q D Q

Q D

D Q D Q

Q

Encoder

D0 D1 D2

τ τ τ τ

Dout

Start

Stop

Thermometer code binary code

Encoder

(8)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(9)

Encoder Circuit

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 2 1 1 1 0 0 0 0 0 3 1 1 1 1 0 0 0 0 4 1 1 1 1 1 0 0 0 5 1 1 1 1 1 1 0 0 6 1 1 1 1 1 1 1 0 7 1 1 1 1 1 1 1 1 8 DFF outputs Dout

Buffer delay

DFF offset mismatch

Bubble error

1 0 1 0 0 0 0 0 2 1 1 1 0 0 0 0 0 3 1 1 1 0 1 0 0 0 4 1 1 1 0 1 0 1 0 5 1 1 1 0 1 0 1 1 6

Encoder Circuit

STOP START

D Q D Q D Q D Q

Dout=2

1 1 0 0



2



1

^

₃



_n

bubble

thermometer

(10)

Encoder Circuit

Count the number of “1” outputs from DFFs

To ensure monotonicity of the TDC

Encoder Circuit

STOP START

D Q D Q D Q D Q

Dout=2

1 1 0 0



2



1

^

₃



_n

(11)

Encoder Circuit

# of 1’s counter

IN OUT

IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0

OUT3 OUT2 OUT1 OUT0 1

1 1

1 0

0 0

0

1

0 0 0

0 Bubble error

bubble

Bubble error effects

are suppressed.

(12)

Encoder Circuit

FA

Ci a b

S

Co

FA

Ci a b

S

Co

FA

Ci a b

S

Co

FA

Ci a

b S

Co

FA

Ci a

b S

Co

a2 a1 a0 b0 b1

3bit Adder 1

1 1

1 0 0

0 0 0

1 0 0

0 「 0100 」＝ 4

four

1 1

1 0

0 0

0 0 1

1 0 IN8

IN7 IN6

IN5 IN4 IN3

IN2 IN1 IN0

OUT3 OUT2 OUT1 OUT0

(13)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(14)

TDC Architecture with Self-Calibration

M U START X

STOP

# of 1’s counter

Histogram Engine & Digital Error Correction

Test mode



1

M U

X



2



1



₁



₁



₁



₁



₁



2



₂



₂



₂



₂



₂

D Q D Q D Q D Q D Q D Q D Q

(15)

Self-Calibration Mode

Test mode

M U START X

STOP

# of 1’s counter

Histogram Engine & Digital Error Correction

Test mode



1

M U

X



2



1



₁



₁



₁



₁



₁



2



₂



₂



₂



₂



₂

NOT

Synchronized

15

(16)

Normal Operation Mode

normal mode

M U START X

STOP

# of 1’s counter Digital Error Correction

Test mode



1

M U

X



1



₁



₁



₁



₁

(17)

Measurement with Histogram Random dots

S ¹

S ²

N 1

N ²

Area ratio

# of dots ratio N ¹ N 2

S ¹

S 2 ₁₇

(18)

Histogram in Ideal Case

Test mode

The two oscillators are different from each other

and not synchronized

^{# of}

“1” output

Code

22 20 18 16 22 20 18 16 20 18 16 0 500 1000 1500 2000 2500 3000

The histograms in all bins will be equal,

after collection of a sufficiently large number of data,

if the TDC has perfect linearity

(19)

Delay Variation Measurement

Histogram

TDC digital output



2





3





4





5





1

      

₂

   

₃

   

₄

TDC is non-linear

buffer delay

D Q D Q D Q

(20)

Histogram Data is Proportional to Delay Value

Elapsed Time (ps)

Histogram

Histogram bin of digital code with large delay is high.

Histogram bin of digital code with small delay is low.

(21)

Principle of Self-Calibration

T

n Dout  f (T ) Histogram

TDC digital output

Histogram of ideally

Histogram

TDC digital output Nonlinear TDC

① ②

③ ④

Linearized by inverse function

T

n

Linear TDC

INL calculation

21

(22)

0 2 4 6 8 10 12 14 16 18 20 22 0

0.5 1 1.5 2 2.5x 10⁶

Simulation Result of Self-Calibration

before calibration

code

Sampling points 28,848,432

ps 69

1

 60 ～



0 2 4 6 8 10 12 14 16 18 20 22

0 0.5 1 1.5 2 2.5x 10⁶

after calibration

code

MATLAB

Histogram for each bin is the same

# of “1” output # of “1” output

(23)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(24)

Stochastic TDC Structure

D Q

1 ₁



1



₁



₁



₁

START

STOP

Encoder Dout

+ -

random offset

D Q

(25)

D Q

Stochastic TDC for Fine Time Resolution

M U

X M

U

X 

¹

^

¹

^

¹



₁



₁



₁



₁



2

START

STOP

# of “1”s Counter, Histogram Engine & Digital Correction ^Dout

+ -



2



₂



₂



₂



₂



₂

+ -

DFF random offsets

D Q D Q D Q D Q D Q D Q

(26)

Stochastic Variation of Delay at Sub-Picosecond Level

Example:

Statistical process variation on gate leakage, subthreshold leakage, dynamic power and propagation delay in a 2-input NAND gate

Circuit performance characteristics like voltage, delay, slew and power are stochastic processes.

stochastic variation in propagation delay is at sub-picosecond level

(27)

Delay Variation in Stochastic TDC

Setup /hold times of each DFF are different due to stochastic variation

Setup/hold times = 19.31ps

19.36ps 19.40ps

19.60ps 19.82ps

19.31ps 19.82ps

(28)

Input-Output Characteristics of Stochastic TDC

Ex.

DFF number = 400

Setup/hold times of 400 DFFs are normally distributed

Mean = 20ps, standard deviation = 6ps

20ps

26ps 14ps

Digital output code

Time resolution = 0.08ps

But nonlinear !!

(29)

How to Convert a Nonlinear TDC into a Linear TDC?

Convert

Self-calibration is applied to improve linearity !!

nonlinear TDC linear TDC

(30)

Input-output Characteristics Before and After Calibration

before calibration

after calibration

Time difference (ps)

Digital output code

Time difference (ps)

Digital output code

Digital output code

DFF = 200 DFF = 100

DFF = 400

TDC linearity is improved

after calibration !!

(31)

INL Reduction After Calibration

-50 -40 -30 -20 -10 0 10 20 30

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97

Stage of buffers

INL value

-60 -40 -20 0 20 40 60

1 8 15 22 29 36 43 50 57 64 71 78 85 92 99 106113120127134141148155162169176183190197

INL value

-100 -50 0 50 100 150 200

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254 265 276 287 298 309 320 331 342 353 364 375 386 397

INL value

# of DFFs = 100

# of DFFs = 200

# of DFFs = 400

31

(32)

Measurement Time Resolution

Time resolution after calibration can reach sub-picosecond level !!

DFF Number Time Resolution

100 0.3258ps

200 0.1613ps

400 0.0876ps

Comparison with other TDC architectures

(33)

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

(34)

Conclusions

■ Fine digital CMOS implementation

・ Verification

・ Self-calibration

・ Consists of digital cells

・ High linearity TDC

→Self-Calibration circuit

・ Fine time resolution TDC

→Stochastic architecture

・ High linearity TDC

→Self-Calibration circuit

・ Fine time resolution TDC

→Stochastic architecture

Note: Stochastic ADC linearity calibration is NOT easy.

(35)

with Full Digital Circuit and Self-Calibration

Timing Measurement BOST Architecture with Full Digital Circuit and Self-Calibration

Using Characteristics Variation Positively for Fine Time Resolution

Congbing Li, Junshan Wang, Haruo Kobayashi Ryoji Shiota

Gunma University, Socionext Inc.

21

IEEE International Mixed-Signal Testing Workshop Catalunya, Spain

July 5, 2016 9:00-9:30am

Conference Room: Goya

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

Introduction

“Fine time resolution” and “high linearity”

TDC is essential for jitter, timing BOST

・ High linearity TDC

→Self-calibration circuit

・ Fine time resolution TDC

→Stochastic architecture

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

Time to Digital Converter （ TDC ）

T Start

Stop

Start

Stop TDC D out

LSB [p s]

Higher resolution with CMOS scaling

● time interval → Measurement → Digital value

● Key component of

time-domain analog circuit

● Higher resolution can be

obtained with scaled CMOS

Time to Digital Converter （ TDC ）

Start

Stop

D0=1 D1=1 D2=1 D3=0 D4=0 Timing chart

T

Start

Stop

τ τ τ τ

τ τ τ τ

Thermometer code binary code

Encoder

Outline

• Introduction

• Time to Digital Converter （ TDC ）

• Encoder Circuit

• Self-Calibration

• Stochastic TDC Structure

• RTL Simulation

• Conclusions

Encoder Circuit

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 2 1 1 1 0 0 0 0 0 3 1 1 1 1 0 0 0 0 4 1 1 1 1 1 0 0 0 5 1 1 1 1 1 1 0 0 6 1 1 1 1 1 1 1 0 7 1 1 1 1 1 1 1 1 8 DFF outputs Dout

Buffer delay

DFF offset mismatch

Bubble error

1 0 1 0 0 0 0 0 2 1 1 1 0 0 0 0 0 3 1 1 1 0 1 0 0 0 4 1 1 1 0 1 0 1 0 5 1 1 1 0 1 0 1 1 6

Encoder Circuit

STOP START

Dout=2

Stop TDC D ^out

^

^