1
ESP1104 Introduction to Electronic Systems
Tutorial 9
1)
a) Assuming the initial state of the shift register shown in the following figure is Q0=1, Q1=Q2=0. The D flip-flops are positive-edge triggered. Find the successive states.
D0 Q0
C
D1 Q1
C
D2 Q2
C Clock in
D0 Q0
C
D1 Q1
C
D2 Q2
C Clock in
b) Repeat the problem if the AND gate is replaced by an OR gate. c) Repeat the problem if the AND gate is replaced by an XOR gate.
2) The D flip-flops in the following figure are positive-edge triggered. Assuming that prior to the t=0, the states are Q0=Q1=0. Sketch the timing diagram for Q0 and Q1.
D0 Q0
C
D1 Q1
C
Clock in
Q0 Q1
D0 Q0
C
D1 Q1
C
Clock in
Q0 Q1
Clock in
1 2
t
10
Clock in
1 2
t
10
2
3) If a circuit is constructed from 3 D-type flip-flops, with: 1
2 ,
1
, 1 2
2
0 Q D Q Q D Q
D = = ⊕ = .
a) Draw the circuit diagram.
b) Assuming the circuit starts with all flip-flops SET, sketch a timing diagram which shows the outputs of all three flip-flops.
4) The flip-flop with the characteristic given in the following figure, where A and B are the inputs to the flip-flop and Q is the next state output. Make a T flip-flop from the flip- flop with necessary logic gates.
5) Construct a JK flip-flop from a negative-edge-triggered D flip-flop with necessary logic gates.
