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J140 e IEICE 2008 3 最近の更新履歴 Hideo Fujiwara J140 e IEICE 2008 3

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Fig. 2 Buffer-based test architecture enables parallel test application while utilizing a shared functional TAM.
Fig. 3 Effect of repetitive packet delivery sequence for different packet sizes.
Fig. 5 Core test architecture with input and output buffers to temporarily hold the test vectors and test responses, respectively.
Fig. 7 Power-constrained scheduling with variable test frequencies al- al-lows better power utilization to minimize the test application time.
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