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J153 e IEICE 2010 7 最近の更新履歴 Hideo Fujiwara J153 e IEICE 2010 7

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Fig. 2 An example of RTL datapath and its corresponding gate level circuit.
Fig. 3 Relation between equivalent faults and functionality of respective signal lines.
Table 1 Circuit characteristics. Circuit #bit #PI #PO #reg Area (#gate)
Table 3 shows the signal line and path mapping re- re-sults in detail. Rows “#Ptotal”, “#Punique”, “#Stried”, “#Smapped” and “#Pmapped” show the total number of RTL paths, the number of paths uniquely identified with the I/O mapping information, the number
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